Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor
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1 Triode Working FET
2
3 Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the threshold voltage. Discuss various physical structures of MOSFETs, including enhancement and depletion mode devices. Derive the ideal current voltage relationship of the MOSFET. Develop the small-signal equivalent circuit of the MOSFET. Derive the frequency limiting factors of the MOSFET.
4 10.1 THE TWO-TERMINAL MOS STRUCTURE The heart of the MOSFET is the MOS capacitor. The metal may be aluminum or some other type of metal, although in many cases, it is actually a high-conductivity polycrystalline silicon that has been deposited on the oxide; however, the term metal is usually still used. The parameter tox in the figure is the thickness of the oxide and εox is the permittivity of the oxide.
5 Energy Band Diagrams The majority carrier holes would experience a force toward the oxide semiconductor interface. An accumulation layer of holes at the oxide semiconductor junction corresponds to the positive charge on the bottom plate of the MOS capacitor.
6 Energy Band Diagrams
7 Energy Band Diagrams Positive electron energy is plotted upward and positive voltage is plotted downward. Figure 10.5 shows that the intrinsic Fermi level at the surface is now below the Fermi level. Created an inversion layer of electrons at the oxide semiconductor interface. The same type of energy band diagrams can be constructed for a MOS capacitor with an n type semiconductor substrate.
8 Depletion Layer Thickness The potential Φfp is the difference (in V) between Efi and EF and is given by The conduction and valence bands are bent even more and the intrinsic Fermi level has moved above the Fermi level. The space charge width Xd, εs is the permittivity of the semiconductor.
9 7.2.3 Space Charge Width The total depletion or space charge width W is the sum of the two components.
10 Depletion Layer Thickness P-type n-type
11 Depletion Layer Thickness Summary The electron concentration at the surface is the same as the hole concentration in the bulk material. This condition is known as the threshold inversion point. The applied gate voltage creating this condition is known as the threshold voltage. If the gate voltage increases above this threshold value, the conduction band will bend slightly closer to the Fermi level, but the change in the conduction band at the surface is now only a slight function of gate voltage. The electron concentration at the surface is an exponential function of the surface potential. The surface potential may increase by a few (kt/e) volts, which will change the electron concentration by orders of magnitude, but the space charge width changes only slightly. In this case, then the space charge region has essentially reached a maximum width.
12 Surface Charge Density The inversion charge density increases by a factor of 10 with a 60 mv increase in surface potential. The electron inversion charge density increases rapidly with small increases in surface potential, which means that the space charge width essentially reaches a maximum value.
13 Work Function Differences If we sum the energies from the Fermi level on the metal side to the Fermi level on the semiconductor side, we have
14 Work Function Differences In the degenerately doped polysilicon, we will initially assume that EF = Ec for the n + case and EF = Ev for the p + case. For the n + polysilicon gate, For the p + polysilicon gate,
15 Work Function Differences However, for degenerately doped n + polysilicon and p + polysilicon, the Fermi level can be above Ec and below Ev, respectively, by 0.1 to 0.2 V. The experimental φms values will then be slightly different from the values calculated.
16 Flat Band Voltage The flat band voltage is defined as the applied gate voltage such that there is no band bending in the semiconductor and, as a result, zero net space charge in this region. For zero applied gate voltage, If a gate voltage is applied,
17 Threshold Voltage The threshold inversion point, in turn, is defined as the condition when the surface potential is φs=2φfp for the p type semiconductor and Φs=2φfn for the n type semiconductor. The space charge width has reached its maximum value. There is an equivalent oxide charge Q ss and the positive charge on the metal gate at threshold is Q mt.
18 Threshold Voltage VTN is the threshold voltage that creates the electron inversion layer charge. The surface potential is Φs=2Φfp at threshold.
19 Threshold Voltage For n-type substrate, More Na, V TN more positive. More Nd, VTP more negative.
20 10.2 CAPACITANCE VOLTAGE CHARACTERISTICS As mentioned previously, the MOS capacitor structure is the heart of the MOSFET. where dq is the magnitude of the differential change in charge on one plate as a function of the differential change in voltage dv across the capacitor. There are three operating conditions of interest in the MOS capacitor: accumulation, depletion, and inversion.
21 Ideal C V Characteristics Accumulation Depletion Inversion
22 Ideal C V Characteristics The point on the curve that corresponds to the flat-band condition is of interest. The flat-band condition occurs between the accumulation and depletion conditions.
23 Frequency Effects Two sources of electrons that can change the charge density of the inversion layer. Diffusion of minority carrier electrons from the p type substrate across the space charge region. Thermal generation of electron hole pairs within the space charge region. In general, high frequency corresponds to a value on the order of 1 MHz and low frequency corresponds to values in the range of 5 to 100 Hz.
24 Fixed Oxide and Interface Charge Effects The C V measurements are a valuable diagnostic tool to characterize a MOS device. For a given MOS structure, φms and Cox are known, so the ideal flat band voltage and flat band capacitance can be calculated. The experimental value of flat band voltage can be measured from the C V curve. The value of fixed oxide charge can then be determined.
25 Fixed Oxide and Interface Charge Effects These allowed energy states are referred to as interface states. Charge can flow between the semiconductor and interface states, in contrast to the fixed oxide charge.
26 Fixed Oxide and Interface Charge Effects There is a net positive charge trapped in the donor states. There is now a net negative charge in the acceptor states.
27 Fixed Oxide and Interface Charge Effects C V curves become smeared out!
28 10.3 THE BASIC MOSFET OPERATION A positive gate voltage induces the electron inversion layer, which then connects the n type source and the n type drain regions.
29 Current Voltage Relationship Concepts In the p channel enhancement mode device, a negative gate voltage must be applied to create an inversion layer of holes that will connect the p type source and drain regions.
30 Current Voltage Relationship Concepts
31 Current Voltage Relationship Concepts
32 Current Voltage Relationship Concepts If VGS increases, the initial slope of ID versus VDS increases. The value of VDS (sat) is a function of VGS.
33 Current Voltage Relationship Concepts In the non-saturation region, In the saturation region,
34 * Current Voltage Relationship Mathematical Derivation Assumptions: 1. The current in the channel is due to drift rather than diffusion. 2. There is no current through the gate oxide. 3. A gradual channel approximation is used in which Ey/ y > Ex/ x. This approximation means that Ex is essentially a constant. 4. Any fixed oxide charge is an equivalent charge density at the oxide semiconductor interface. 5. The carrier mobility in the channel is constant.
35 * Current Voltage Relationship Mathematical Derivation 1 3 The contributions of surfaces 1 and 2 cancel each other. Surface 3 is in the neutral p region, so the electric field is zero at this surface. Surface 4 is the only surface that contributes. 2
36 * Current Voltage Relationship Mathematical Derivation 4
37 * Current Voltage Relationship Mathematical Derivation 5
38 * Current Voltage Relationship Mathematical Derivation 6 For very small values of VDS,
39 * Current Voltage Relationship Mathematical Derivation 7 P-chanel MOSFET
40 Transconductance The MOSFET transconductance is defined as the change in drain current with respect to the corresponding change in gate voltage, In the non-saturation region, In the saturation region,
41 Substrate Bias Effects (Body effects)
42 10.4 FREQUENCY LIMITATIONS
43 Frequency Limitation Factors and Cutoff Frequency Limitation Factors The channel transit time, usually not the limiting factor. The gate or capacitance charging time.
44 Frequency Limitation Factors and Cutoff Frequency Cutoff Frequency
45 *10.5 THE CMOS TECHNOLOGY In most cases, the p type substrate doping level must be larger than the n type substrate doping level to obtain the desired threshold voltages. The larger p doping can easily compensate the initial n doping to form the p well. The notation FOX stands for field oxide, which is a relatively thick oxide separating the devices. The FOX prevents either the n or p substrate from becoming inverted and helps maintain isolation between the two devices.
46 *10.5 THE CMOS TECHNOLOGY Major problem in CMOS circuits has been latch up. Latch up refers to a high current, low voltage condition that may occur in a four layer pnpn structure. Preventing latch up kill the minority carrier lifetime by gold doping or neutron irradiation. using proper circuit layout techniques the silicon on insulator technology.
47 *10.5 THE CMOS TECHNOLOGY
48 *10.5 THE CMOS TECHNOLOGY
49 *10.5 THE CMOS TECHNOLOGY
50 *10.5 THE CMOS TECHNOLOGY
51 *10.5 THE CMOS TECHNOLOGY
52 *10.5 THE CMOS TECHNOLOGY
53 *10.5 THE CMOS TECHNOLOGY
54 *10.5 THE CMOS TECHNOLOGY
55 *10.5 THE CMOS TECHNOLOGY
56 *10.5 THE CMOS TECHNOLOGY
57 *10.5 THE CMOS TECHNOLOGY
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