MOS Transistor I-V Characteristics and Parasitics

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1 ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes a finite amount of current Depends on terminal voltages Derive current-voltage (I-V) relationships Transistor gate, source, drain all have capacitances I = C ( V/ t) -> t = (C/I) V Capacitance and current determine speed Also explore what a degraded level really means ECEN

2 MOS Capacitor Gate and body form a MOS capacitor Operating modes Accumulation Depletion Inversion (a) V g < polysilicon gate 00 silicon dioxide insulator 0 < V g < V t depletion region + - (b) V g > V t + - inversion region depletion region (c) ECEN Terminal Voltages for NMOS Mode of operation depends on V g, V d, V s = V g V s V gd = V g V d V ds = V d V s = -V gd Source and drain are symmetric diffusion terminals By convention, source is the terminal at a lower voltage Hence V ds 0 V g nmos body is grounded. + + Three regions of operation V gd Cutoff - - Linear V s - Saturation V + ds V d ECEN

3 nmos Cutoff No channel = 0 I ds = s g V gd d n+ n+ b ECEN nmos Linear Channel forms Current flows from d to s e - from s to d I ds increases with V ds Similar to a linear resistor > V t + - s n+ n+ g b + - V gd = d V ds = 0 > V t + - s n+ n+ g 0 b + - > V gd > V t d I ds 0 < V ds < -V t ECEN

4 nmos Saturation Channel pinches off I ds independent of V ds (approximately) We say the drain current saturates > V t + - s n+ n+ g b + - V gd < V t d I ds V ds > -V t Similar to a voltage controlled current source ECEN I-V Characteristics In Linear region, I ds depends on How much charge is in the channel? How fast is the charge moving? ECEN

5 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = t ox 00 polysilicon 00 gate W 0 00 n+ L n+ SiO2 gate oxide (good insulator, ε ox = 3.9) gate V + g + C g V gd source - - drain channel n+ - + n+ V s V ds V d ECEN Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = CV C = t ox polysilicon 000 gate 000 W n+ L n+ SiO2 gate oxide (good insulator, ε ox = 3.9) gate V + g + C g V gd 000 source - - drain channel n+ - + n+ V s V ds V d ECEN

6 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = CV C = C g = ε ox WL/t ox = C ox WL V = C ox = ε ox / t ox t ox 00 polysilicon 00 gate W 0 00 n+ L n+ SiO2 gate oxide (good insulator, ε ox = 3.9) gate V + g + C g V gd source - - drain channel n+ - + n+ V s V ds V d ECEN Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = CV C = C g = ε ox WL/t ox = C ox WL V = V gc V t = ( V ds /2) V t C ox = ε ox / t ox t ox polysilicon 000 gate 000 W n+ L n+ SiO2 gate oxide (good insulator, ε ox = 3.9) gate V + g + C g V gd 000 source - - drain channel n+ - + n+ V s V ds V d ECEN

7 Carrier velocity Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v = ECEN Carrier velocity Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v = µe E = µ called mobility ECEN

8 Carrier velocity Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v = µe µ called mobility E = V ds /L Time for carrier to cross channel: t = ECEN Carrier velocity Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v = µe µ called mobility E = V ds /L Time for carrier to cross channel: t = L / v ECEN

9 nmos Linear I-V Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross I ds = ECEN nmos Linear I-V Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross I ds Q = t = channel ECEN

10 nmos Linear I-V Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross I ds Qchannel = t W V = µ C V V V L V = β V ds gs V t V 2 ds ds ox gs t 2 ds W β = µcox L ECEN nmos Saturation I-V If V gd < V t, channel pinches off near drain When V ds > V dsat = V t Now drain voltage no longer increases current I ds = ECEN

11 nmos Saturation I-V If V gd < V t, channel pinches off near drain When V ds > V dsat = V t Now drain voltage no longer increases current V I = β V V dsat V 2 ds gs t dsat ECEN nmos Saturation I-V If V gd < V t, channel pinches off near drain When V ds > V dsat = V t Now drain voltage no longer increases current V I = β V V dsat V 2 β = ( V ) 2 gs Vt 2 ds gs t dsat ECEN

12 nmos I-V Summary Shockley 1 st order transistor models 0 Vgs < Vt V I = β V V ds V V < V 2 β ( V V ) 2 V > V 2 ds gs t ds ds dsat gs t ds dsat cutoff linear saturation ECEN For a 0.6 µm process t ox = 100 Å µ = 350 cm 2 /V*s V t = 0.7 V Plot I ds vs. V ds = 0, 1, 2, 3, 4, 5 Use W/L = 4/2 λ Example AV / L L L 14 W W W ox 8 β = µ C = ( ) = µ I ds (ma) = 2 V 0 gs = V ds = 5 = 4 = 3 ECEN

13 pmos I-V All dopings and voltages are inverted for pmos Source is the more positive terminal Mobility µ p is determined by holes Typically 2-3x lower than that of electrons µ n 120 cm 2 /V s in AMI 0.6 µm process Thus pmos must be wider to provide same current In this class, assume µ n / µ p = 2 I ds (ma) = -4 = -3 = -2 = -1 = V ds ECEN Non-ideal I-V Effects Velocity saturation Due to lateral E-field Mobility degradation Due to vertical E-field Channel length modulation Leakage current Body effect Temperature dependence And many more ECEN

14 Channel Length Modulation Ideally, Ids is independent of V ds in saturation Reverse-biased p-n junction between drain and body forms a depletion region with width L d L EFF = L L d L d increases with V db or V ds I ds increases slightly with V ds ECEN Velocity Saturation Ideally, carrier drift velocity increases linearly with lateral field ( V ds / L ) If lateral field is very strong, the velocity saturated due to scattering α-power law model As velocity saturated, increasing has less effect As velocity saturated, no benefit to raise V DD ECEN

15 Velocity Saturation Velocity saturation Impact of the lateral electrical field υ n (m/s) υ sat = 10 5 Constant velocity Constant mobility (slope = µ) ξ c = 1.5 ξ (V/µm) ECEN Velocity Saturation Velocity saturation I D Long-channel device V GS = V DD Short-channel device V DSAT Not V GS -V T!!! V GS -V T V DS ECEN

16 Mobility Degradation Strong vertical field ( ) causes scattering, reduces carrier mobility Captured in α-power law model By α ECEN Short-Channel Effects (5) Mobility degradation Impact of vertical electric field u n (cm 2 /Vs) E t (V/um) ECEN

17 Subthreshold leakage Vgs Vt nvt Ids = Ids0 e (1 Leakage Current e V v Thermal voltage: V T = kt/q ~26mv) k: Boltzmann s constant T ds ) Junction leakage Gate tunneling ECEN Body Effect V sb affects threshold voltage Vt = Vt0 + γ ( 2 φ + Vsb 2 φ ) F F φ F : Fermi potential (in bulk) Body voltage affects both speed and leakage Forward body bias (FBB) Reverse body bias (RBB) ECEN

18 Temperature Dependence When temperature increases Carrier mobility decreases, ON current decreases Threshold voltage decreases, leakage increases ECEN Capacitance Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important Creates channel charge necessary for operation Source and drain have capacitance to body Across reverse-biased diodes Called diffusion capacitance because it is associated with source/drain diffusion ECEN

19 Gate Capacitance Approximate channel as connected to source C gs = ε ox WL/t ox = C ox WL = C permicron W C permicron is typically about 2 ff/µm t ox polysilicon gate W n+ L n+ SiO2 gate oxide (good insulator, ε ox = 3.9ε 0 ) ECEN Diffusion Capacitance C sb, C db Undesirable, called parasitic capacitance Capacitance depends on area and perimeter Use small diffusion nodes Comparable to C g for contacted diff ½ C g for uncontacted Varies with process ECEN

20 Diffusion Capacitance We assumed contacted diffusion on every s / d. Good layout minimizes diffusion area Ex: NAND3 layout shares one diffusion contact Reduces output capacitance by 2C Merged uncontacted diffusion might help too Shared Contacted Diffusion Merged Uncontacted Diffusion 2C 2C 3C 3C 3C Isolated Contacted Diffusion C 3C 3C ECEN Activity 1) If the width of a transistor increases, the current will 2) If the length of a transistor increases, the current will 3) If the supply voltage of a chip increases, the maximum transistor current will 4) If the width of a transistor increases, its gate capacitance will 5) If the length of a transistor increases, its gate capacitance will 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will ECEN

21 Activity 1) If the width of a transistor increases, the current will 2) If the length of a transistor increases, the current will 3) If the supply voltage of a chip increases, the maximum transistor current will 4) If the width of a transistor increases, its gate capacitance will 5) If the length of a transistor increases, its gate capacitance will 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will ECEN

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