The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

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1 igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002

2 Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models for SPICE simulation Analysis of secondary and deep-submicron effects Future trends

3 The iode B Al A SiO 2 p n Cross-section of pn-junction in an IC process A p n B One-dimensional representation Al A B diode symbol Mostly occurring as parasitic element in igital ICs

4 epletion Region p Charge ensity hole diffusion electron diffusion hole drift electron drift - ρ + n x istance (a) Current flow. (b) Charge density. Φ Φ 0 T Built-in potential N N A = ΦT ln 2 ni KT = = 26 mv at q 300K Electrical Field ξ x (c) Electric field. N A : acceptor concentrations N : donor concentrations n i : intrinsic carrier concentration Potential V ψ 0 -W 1 W 2 Zero-Bias x (d) Electrostatic potential.

5 iode Current eviation due to recombination

6 Forward Bias I I dnp, n _ dx p = qa n p0 = qa p W n p n p0 dn dx W 1 p e V Φ T 1 p n (W 2 ) L p I I dpn, p _ dx p = qa = qa p n p dp dx pn0 W W 2 n p n0 e V Φ T 1 p-region -W 1 0 W 2 I = I + p I n n-region x diffusion Typically avoided in igital ICs

7 Reverse Bias p n0 n p0 p-region -W 1 0 W 2 n-region x diffusion The ominant Operation Mode

8 Models for Manual Analysis V + I = I S (e V /φt 1) V + + I V on (a) Ideal diode model (b) First-order diode model

9 Junction Capacitance Junction Capacitance ( ) Φ + = Φ + = A A si j A A si j N N N N A C V N N N N q A Q ε ε

10 iffusion Capacitance τ T : mean transit time Small signal capacitance

11 Secondary Effects 0.1 I (A) V (V) Avalanche Breakdown

12 iode Model R S + V - I C

13 SPICE Parameters

14 What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron

15 The MOS Transistor Polysilicon Aluminum

16 MOS Transistors - Types and Symbols G G S NMOS Enhancement NMOS S epletion G G B PMOS S Enhancement S NMOS with Bulk Contact

17 Threshold Voltage: Concept S - V GS + G n+ n+ n-channel p-substrate epletion Region B

18 The Threshold Voltage

19 The Body Effect V T T 0 + γ ( ) 2Φ + V Φ = V 2 F S B F V T (V) V SB forward bias V T decrease V SB reverse bias V T increase V BS (V)

20 Current-Voltage Relations A good ol transistor -4 x 10 6 VGS= 2.5 V 5 4 Resistive Saturation VGS= 2.0 V I (A) 3 V S = V GS -V T Quadratic Relationship 2 VGS= 1.5 V 1 VGS= 1.0 V V S (V)

21 Transistor in Linear V V GS G > V T > V T V < S V S _ sat V GS S G V S I n + V(x) + n + L x p-substrate B MOS transistor and its bias conditions

22 Transistor in Saturation V GS G V S > V GS - V T S n+ - V GS - V T + n+ Pinch-off

23 Current-Voltage Relations Long-Channel evice

24 A model for manual analysis

25 Current-Voltage Relations The eep-submicron Era 2.5 x Early Saturation VGS= 2.5 V 1.5 VGS= 2.0 V I (A) 1 VGS= 1.5 V Linear Relationship 0.5 VGS= 1.0 V V S (V)

26 Velocity Saturation υ n (m/s) υ sat = 10 5 Constant velocity Constant mobility (slope = µ) ξ c = 1.5 ξ (V/µm)

27 Perspective I Long-channel device V GS = V Short-channel device V SAT V GS -V T V S

28 I versus V GS 6 x x quadratic linear I (A) 3 I (A) V GS (V) Long Channel 0.5 quadratic V GS (V) Short Channel

29 I versus V S I (A) 6 x VGS= 2.5 V Resistive Saturation VGS= 2.0 V V S = V GS -V T VGS= 1.5 V I (A) x 10 VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V 1 VGS= 1.0 V 0.5 VGS= 1.0 V V S (V) Long Channel V S (V) Short Channel

30 A unified model for manual analysis G S B

31 Simple Model versus SPICE 2.5 x 10-4 V S =V SAT Velocity Saturated I (A) 1 Linear 0.5 V SAT =V GT V S =V GT Saturated V S (V)

32 A PMOS Transistor 0 x 10-4 VGS = -1.0V -0.2 VGS = -1.5V -0.4 I (A) -0.6 VGS = -2.0V Assume all variables negative! -0.8 VGS = -2.5V V S (V)

33 Transistor Model for Manual Analysis

34 The Transistor as a Switch V GS V T S Ron I V GS = V R mid R 0 V /2 V V S

35 The Transistor as a Switch 7 x R eq (Ohm) V (V)

36 The Transistor as a Switch

37 MOS Capacitances ynamic Behavior

38 ynamic Behavior of MOS Transistor G C GS C G S C SB C GB C B B

39 The Gate Capacitance Polysilicon gate Source n + x d x d W rain n + L d Top view Gate-bulk overlap t ox Gate oxide n + L n + Cross section

40 Gate Capacitance G G G S C GC C GC C GC S S Cut-off Resistive Saturation Most important regions in digital design: saturation and cut-off

41 Gate Capacitance WLC ox C GC WLC ox C GC 2WLC ox WLC ox 2 C GC B C GCS = C GC WLC ox 2 C GCS C GC 3 V GS 0 V S /(V GS -V T ) 1 Capacitance as a function of VGS (with VS = 0) Capacitance as a function of the degree of saturation

42 iffusion Capacitance Channel-stop implant N A 1 Side wall W Source N Bottom x j L S Side wall Substrate N A Channel

43 Junction Capacitance

44 Linearizing the Junction Capacitance Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest

45 Capacitances in 0.25 µm m CMOS process

46 The Sub-Micron MOS Transistor Threshold Variations Subthreshold Conduction Parasitic Resistances

47 Threshold Variations V T V T Long-channel threshold Low V S threshold Threshold as a function of the length (for low V S ) L V S rain-induced barrier lowering (for low L)

48 Sub-Threshold Conduction Linear The Slope Factor I ~ I 0 e qv nkt GS, n =1+ C C ox I (A) Quadratic S is V GS for I 2 /I 1 = Exponential V T V GS (V) Typical values for S: mv/decade

49 Sub-Threshold I vs VGS qvgs nkt I I0e 1 e qv = kt S V S from 0 to 0.5V

50 Sub-Threshold I vs VS I qvgs qv = nkt kt I e 0 1 e S ( 1+ λ V ) S V GS from 0 to 0.3V

51 Summary of MOSFET Operating Regions Strong Inversion V GS >V T Linear (Resistive) V S <V SAT Saturated (Constant Current) V S V SAT Weak Inversion (Sub-Threshold) V GS V T Exponential in V GS with linear V S dependence

52 Parasitic Resistances G Polysilicon gate L rain contact V GS,eff S W R S R rain

53 Latch-up

54 Future Perspectives 25 nm FINFET MOS transistor

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