Lecture 12: MOS Capacitors, transistors. Context

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1 Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those results to: MOS Capacitors ( ): Accumulation, Depletion, Inversion Threshold Voltage CV Curve And start the discussion of transistors

2 MOS structures MOS stands for Metal*-Oxide-semiconductor MOS structures are the heart of field effect transistors. The MOS structure gives a control mechanism for the carriers in a layer called the channel by changing the voltage on a nearby layer called the gate *The metal is usually a doped polysilicon layer these days MOS The MOS structure can be viewed as a PN diode, with one heavily doped side (the metal ), and an extra insulating layer. The extra insulating layer stops currents from flowing, but the electric fields still penetrate

3 Charge distribution in a MOS structure Oxide Depletion region Semiconductor (n type) At equilibrium, there is a depletion region into the semiconductor, but since the metal has a LOT of carriers per unit volume, it has little or no depletion depth into it, and any charge on it is at its surface Reverse Bias Oxide Depletion region Semiconductor (n type) Under a reverse bias, there isn t much difference between a PN diode and a MOS stack, the insulator just blocks the minority carriers, so there is zero current instead of very little current

4 Forward Bias Oxide Depletion region Semiconductor (n type) Under a forward bias, the insulating layer blocks diffusion, so the depletion layer narrows, but there is still no vertical current. Accumulation Oxide Semiconductor (n type) Under a higher forward bias, the mobile carriers get pushed up against the barrier, and start to pile up in a thin layer there, the accumulation layer The bias where accumulation starts is called flat band

5 Inversion Oxide Depletion region Semiconductor (n type) Under a strong reverse bias, the potential at the surface of the semiconductor, next to the ide, can get high enough so that holes start to accumulate in a thin layer, the inversion layer Band edge diagram: accumulation Insulator Lots of electrons N type semiconductor

6 Band edge diagram: Flat band Insulator N type semiconductor Band edge diagram: forward bias Insulator N type semiconductor

7 Band edge diagram: equilibrium Insulator N type semiconductor Band edge diagram: reverse bias Insulator N type semiconductor

8 Band edge diagram: inversion Insulator N type semiconductor holes Band edge diagram: more inversion Insulator N type semiconductor lots of holes

9 P type body If the semiconductor is p type, rather than n type: The depletion has a negative fixed charge An inversion layer is an accumulation of electrons Transistor A field effect transistor often uses the appearance of the inversion layer to conduct laterally between two additional contacts

10 MOS Capacitor charge calculations Gate (n + poly) Body (p-type substrate) ε = 11.7ε s 0 0 x Oxide (SiO 2 ) ε = 3.9ε 0 Very Thin! ~1nm t NMOS p-type substrate, PMOS n-type substrate Because the inversion layer is of the opposite type! Accumulation: V GB < V FB Q = C ( V V ) G GB FB ρ( x) V GB < V FB + Q B = Q G Body (p-type substrate) φ( x) Essentially a parallel plate capacitor Capacitance is determined by ide thickness:

11 Depletion: V FB <V GB < V T V GB > V + FB Body (p-type substrate) Q = qn X ( V ) B a d GB Q ( V ) = Q G GB B ρ( x) φ( x) t Positive charge on gate terminates on negative charges in depletion region Potential drop across the ide and depletion region Charge has a square-root dependence on applied bias Inversion V GB = V T Body (p-type substrate) φ s ρ( x) φ( x) t xdep qφs kt s = i = a n n e N The surface potential increases to a point where the electron density at the surface equals the background ion density At this point, the depletion region stops growing and the extra charge is provided by the inversion charge at surface

12 Q-V Curve for MOS Capacitor Q G depletion inversion Q B,max Q ( V ) N GB accumulation V FB V Tn V ( ) GB V In accumulation, the charge is simply proportional to the applies gate-body bias In inversion, the same is true In depletion, the charge grows more slowly since the voltage is applied over a depletion region Flat band voltage V FB N+ semiconductor Insulator P type semiconductor Flat band will occur when the external applied voltage exactly cancels the built in fields, so: VFB = n+ ( φ φ ) p

13 Charge during accumulation N+ semiconductor Insulator P type semiconductor Since the charge at flat band is zero, and all Charge accumulated at lower voltages is at The interface: Q G = C for ( VGB VFB ) ( V GB < V FB ) Threshold voltage V tn φ s N+ semiconductor φ p Insulator φ s P type semiconductor Inversion will occur when the applied voltage pulls the conduction band edge down to the of the P doped material. We will consider the inversion to have started when the number of electrons at the surface is equal to N a n s = N a qφ qφ s p kt kt ns = nie = Na = nie φ = s φ p

14 Calculation of V tn The threshold voltage will have three terms: The flatband voltage V FB This is because the internal field is zero when an external bias is applied to cancel the built in field The voltage across the depletion region which is 2φ p twice the potential for the doping N a because we want that many (N a ) electrons too! The voltage across the ide V OX V = V 2φ + V tn FB p Calculating V tn The voltage across the ide is just the field times the distance. The field at the surface of the semiconductor is what we calculated in the last lecture, but we have to adjust for the different dielectric constant of the silicon diide. t V = Et = ε 2qε sna ( 2φ p ) So we have: t Vtn = VFB 2φ p + ε 2qε sna 2φ p ( )

15 Inversion Stops Depletion Assume that once inversion happens, the depletion region stops growing This is a good apprimation since the inversion charge is an exponential function of the surface potential Under this condition: Q ( V ) Q G Tn B,max Q ( V ) = C ( V V ) Q G GB GB Tn B,max Numerical Example MOS Capacitor with p-type substrate: 16 3 t = 20nm N a = 5 10 cm Calculate flat-band: V = ( φ φ ) = (550 ( 402)) = 0.95V FB n + p Calculate threshold voltage: 13 ε F/cm C = = -6 t 2 10 cm 1 VTn = VFB 2φ p + 2 qεs Na( 2 φp) C VTn =.95 2( 0.4) + = 0.52V C

16 Num Example: Electric Field in Oxide Apply a gate-to-body voltage: V GB = 2.5 < V FB Device is in accumulation The entire voltage drop is across the ide: E V VGB + φ + φ n p ( 0.4) V = = = = 8 10 t t cm The charge in the substrate (body) consist of holes: Q = C ( V V ) = C/cm B GB FB 7 2 Numerical Example: Depletion Region In inversion, what s the depletion region width and charge? V,max = φ φ = φ φ = 2φ = 0.8V B s p p p p V B,max 1 qn a = X 2 ε s 2 d,max X d,max 2ε V s B,max = = qn a 144nm Q,max = qn X,max = C/cm B a d 7 2

17 MOS CV Curve Q G C C C Q ( V ) N GB Q B,max V FB V Tn V ( ) GB V V FB V Tn V GB Small-signal capacitance is slope of Q-V curve Capacitance is linear and equal during accumulation and inversion because the incremental charge is accumulating at the surface of the ide in both cases Capacitance during depletion is smallest Capacitance is non-linear during depletion C-V Curve Equivalent Circuits accumulation C depletion C Inversion C C dep C dep = ε s x dep During depletion, the charge is accumulating across a voltage drop which is across the ide and the depletion region C tot C C C C = = = C C dep + C ε C ε dep dep s t x dep

18 MOSFET Cross Section gate body source drain diffusion regions p+ n+ n+ L p-type substrate Add two junctions around MOS capacitor The regions form PN junctions with substrate MOSFET is a four terminal device The body is usually grounded (or at a DC potential) For ICs, the body contact is at surface MOSFET Layout B S G D contact B S G D poly gate p+ n+ n+ L p-type substrate x j W L Planar process: complete structure can be specified by a 2D layout Design engineer can control the transistor width W and L Process engineer controls t, N a, x j, etc.

19 PMOS & NMOS B S G D B S G D p+ n+ n+ L x j n+ p+ p+ L x j p-type substrate n-type substrate NMOS PMOS A MOSFET by any other name is still a MOSFET: NMOS, PMOS, nmos, pmos NFET, PFET IGFET Other flavors: JFET, MESFET CMOS technology: The ability to fabricated NMOS and PMOS devices simultaneously CMOS B S G D B S G D p+ n+ n+ L x j n+ p+ p+ L x j n-type well NMOS PMOS p-type substrate Complementary MOS: Both P and N type devices Create a n-type body in a p-type substrate through compensation. This new region is called a well. To isolate the PMOS from the NMOS, the well must be reverse biased (pn junction)

20 Circuit Symbols N channel MOS FET P channel MOS FET The symbols with the arrows are typically used in analog applications The body contact is often not shown The source/drain can switch depending on how the device is biased (the device has inherent symmetry)

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