1. The MOS Transistor. Electrical Conduction in Solids

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1 Electrical Conduction in Solids!The band diagram describes the energy levels for electron in solids.!the lower filled band is named Valence Band.!The upper vacant band is named conduction band.!the distance between valence and Conduction band is the energy gap.

2 Energy Gap in Solids Material Metal Semiconductor Insulator Energy Gap none ev > 3 ev Fermi-Dirac Statisitcs Gives the probability of occupation of energy levels: 1 F(E) = 1+ e (E"E F )/ kt E F is the Fermi energy level 3 Fermi-Dirac distribution at different temperatures: At the Fermi level F(E F ) = 1/. Let Z(E) be the energy level distribution; the number of electrons in the energy interval E, E + de is given by: N(E)dE = Z(E)F(E)dE 4

3 The number of electrons in the conduction band is: n = E t " N e (E)dE = N e E c E t # de " (E)dE = " Z(E) 1+ e (E$E F )/ kt E c E c similarly the number of holes, p, in the valence band: p = E v " N h (E)dE = N h #$ E b E v " (E)dE = " Z(E) e(e#e F )/ kt de 1+ e (E#E F )/ kt If the Fermi level is in the middle of the energy gap, the material is referred to as intrinsic, and we have: E v #$ n = p = n i 5 n i is strongly dependent on the temperature. For the silicon (empirical relationship): n i = "10 16 T 3 / #1.1q / kt e at room temperature n i = cm -3 If donor or acceptor impurities are added to the semiconductor, localized energy levels are set in the forbidden gap. The activation energy are: III Group Activation Energy V Group Activation Energy B ev P ev Al Ga ev 0.07 ev As Sb ev ev In ev 6

4 Because of extremely low activation energy, even a low temperature one kt is enough to ionize the donor or the acceptor atoms (kt = 0.05 ev at 300 K). The electrons (or holes) concentration increases in the conduction or valence band. At room temperature: for n-type n ~ N D for p-type p ~ N A The Fermi level is shifted with respect to the intrinsic level of the amount: " F = # kt for p-doping [V]; q ln $ n ' i & ) " F = # kt % ( q ln $ N ' D & ) % ( N A n i for n-doping [V]; 7 Properties of Silicon Property Atomic density Density Atomic weight Reticular constant Thermal conductivity Intrinsic resistivity Relative dielectric constant Absolute dielectric constant Value Dimensions Atoms/cm 3 g/cm 3 g/mole nm!/cm ºC! cm _ F/cm 8

5 Conductivity!=! n +! p = q(nµ n + pµ p ) for a doped material we have n~n D for n-doping p~n A for p-doping hence: n p = n i! = qn D µ n for n-doping! = q N Aµ p for p-doping 9 Mobility The following figures show the surface mobility of electrons and holes as a function of the doping (at room temperature) and a resistivity as a function of the doping (at room temperature). 10

6 Resistance of thin layers Homogeneous material R = "L hw = R L W Diffused layer G = 1 R = W L h # 0 "(z)dz = 1 R $ W L 11 Polysilicon Grown from pyrolytic decomposition of silane (SiH 4 ) at about 600 C. The polycrystalline structure is made of monocrystal grains size in the range of "m. The typical layer are nm thick with long term standard deviation in the % range. The mobility is low because of the grain border resistance (30-40 cm /Vs). In order to have a low sheet resistance the polysilicon must be strongly doped ( cm -3 ). Part of the doping saturates the localized levels due to the grain border. The sheet resistance is in the range 0-40!/". The sheet resistance can be reduced by using sandwich layers (polysilicide) made of 00 nm of polysilicon covered with a film of refractory metal silicide (WSi, MoSi, TiSi ). The sheet resistance is reduced to 1-5!/". 1

7 Silicon dioxide Thermally grown from silicon in dry or wet conditions at C. Property Value density. dielectric strength resistivity (at 300 K) relative dielectric constant Dimension g/cm 3 V/cm! cm The silicon dioxide grown determine a silicon consumption: if d is the thickness of grown oxide, 0.44 d of silicon is consumed. 13 Growth speed: Silicon dioxide can also be grown from chemical vapour deposition (CVD): SiH 4 + O # SiO + H O by pyrolytic decomposition of silane in the presence of oxygen, at atmospheric pressure (AP-CVD) or at low pressure (LP-CVD). 14

8 The temperature ranges from 300 to 500 C. Growth speed, about one order of magnitude larger than the one of thermal dioxide. Charge voltage hysteresis effect when deposited on silicon (not suitable for capacitors). For surface protection p-doped to compensate the sodium ions action. Property Value density. dielectric strength resistivity (at 300 K) relative dielectric constant.7-4. Dimension g/cm 3 V/cm! cm Long term standard deviation 5-6% 15 Silicon nitride Its major use is to protect surface. It is grown by decomposition of silane or dichlorosilane and ammonia at C. 3SiH 4 + 4NH 3 # Si 3 H 4 + 1H 3SiH Cl + 4NH 3 # Si 3 N 4 + 6HCl + 6H Growth speed: 10-0 nm/min Resistivity: !/cm Dielectric strength: 5-10 MV/cm Long term standard deviation: 3-4% 16

9 CMOS technology Symbols of the MOS transistors 17 Typical CMOS process MOS technology integrates both n- channel and p-channel transistors on the same chip. If the substrate of the circuit is n- doped, the p-channel transistors sit directly on the substrate, whereas the n-channel devices need a well. Modern technologies use twin-well to make the two type of transistors inside wells regardless of substrate doping. This approach optimize the electrical behavior at the expense of additional step. 18

10 19 The MOS threshold voltage The threshold voltage is the voltage required at the gate to generate a conductive channel between source and drain. A conductive channel is generated when the oxidesemiconductor interface is in strong inversion (bandbending = -" FS ). In order to evaluate V Th, the following points must be taken into account: 0

11 $ Contact potential of the MOS structure. $ The energy gap E g. $ Fixed charge trapped at the oxide-semiconductor interface. $ For an ideal MOS structure (without interface charge) the contact potential is neutralized by the so called flat band voltage V FB (the band diagram in the semiconductor is flat). V FB = " FG + " FS # E g q + " FS $ In a real MOS structure, within a thin oxide layer at the semiconductor oxide interface, a charge Q SS is trapped Q SS = 10-8 C/cm for <111> Q SS = C/cm for <100> 1 The flat band voltage becomes: V FB, real = E g q + " FS # Q SS C ox The bending of the bands is obtained by depleting the semiconductor: Q gate = Q depletion ( V Th "V FB + # FS ) C ox = qn A x d x d = " qn A V SB # $ FS

12 ( ) V Th = E g q " # + Q SS + Q imp FS + $ V SB " # FS C ox " = q#n A C ox where # is the body effect coefficient. If V SB = 0 V Th,0 = V FB, real " # FS + $ # FS The threshold voltage can be expressed as: % V Th = V Th,0 + "' ( V SB # $ FS # $ & FS * ) 3 I-V characteristics $ Weak inversion region V GS < V Th $ Linear (or Triode) V Th < V GS > V DS + V Th $ Saturation region V Th < V GS < V DS + V Th 4

13 Weak inversion region The band diagram indicates that the structure in equivalent to two back to back p-n diodes where the saturation current depends on the barrier height. I S = I D0 e qv G / nkt e "qv B / nkt I D = I D0 e qv G / nkt e "qv B / nkt 1" e "qv DS ( / kt ) 5 Linear (or Triode) region V(x) is the drop voltage from source to x. The resistance of an incremental element x, x + dx in the channel is: dr = dx "A = dx Q inv (x)µw The drop voltage across the element is: dv = I D dr = The voltage exceeding the threshold determines an accumulation of mobile charge on the channel (inversion region). Q inv (x) = C ox ( V GS "V(x) "V TH (x)) I D dx Q inv (x)µw 6

14 V Th changes along the channel due to the body effect: % V Th = V Th,0 + "' ( V SB # $ FS #V(x) # $ & FS * ) V DS = L # 0 "V dx We get: W + I D = µc ox - L V "V " # $ GS Th,0 F, ( ) V DS " 1 V DS if the last term can be neglected W % I D = µc ox ' L V GS "V Th,0 " # $ F & + % 3 V " $ 3 / 3 / (. ' SB F " VDB " $ & F * 0 )/ ( ) V DS " 1 V DS ( * ) 7 Saturation region As V(x) increases Q inv (x) decreases. Its minimum is at the drain is if ( ) Q inv (L) = C ox V GS "V TH "V DS V DS = V sat = V GS "V TH Q inv (L) = 0 the drain is in the pinch-off condition. If V DS > V sat, the pinch-off point moves toward the source; the part of the V DS voltage exceeding V sat drops along the depleted region, $L, extending from the pinch-off to the drain. "L = # qn A ( V DS $V sat ) 8

15 The structure can be assumed equivalent to a transistor with the pinch-off at the drain but with length reduced of $L. It results: I D = 1 µc ox L L " #L = 1 $ 1" qn A L W ( L " #L V "V GS Th ) = 1 µc W ox ( L V "V GS Th ) L ( V "V DS sat) = 1+ $ L " #L qn A L V DS "V sat % 1+ &V DS having neglected V sat with respect to V DS " = # qn A L $ 107 L N A % = channel length modulation parameter # V -1 9 hence in saturation: I D = 1 µc ox W ( L V GS "V Th ) ( 1+ #V DS )!C ox is often represented by the symbol k n (k p ) that is called the process transconductance parameter. For a given CMOS technologies we can use the following figures t ox = 15 nm,! n = 50 cm /V s and! p = 180 cm /V s. Therefore we have: k n =! n C ox = 108 "A/V k p =! p C ox = 38 "A/V 30

16 Large signal equivalent circuit Non linear $ current source $ diodes Linear (1 st approximation) $ resistors $ C GS,ov, C GD,ov $ C GS, C BG, C GD, C BS, C BD 31 Typically: R D # R S # 10-50! C GS,ov = C GD,ov = W x ov C ox Diodes reversely biased; the reverse current is dominated by generation recombination term. A: area of the junction x j : depletion region width & 0 : mean lifetime for minority carriers I GR = A qn i x j " 0 I GR doubles for an increase of 10 K. Typically at room temperature I GR /A = A/"m. 3

17 Small signal equivalent circuit Obtained by a linearization of the large signal equivalent circuit. I D = I D (V GS, V DS, V BS ) The linearization of the current source generates three voltage controlled current sources: g m = $I D / $V GS transconductance g ds = $I D / $V DS drain output transconductance g mb = $I D / $V BS substrate transconductance 33 Transconductance $ Subthreshold region (like a bipolar transistor): g m = "g mb = I D n kt q $ Linear region: $ Saturation region: g m = µc ox W L V DS W g m = µc ox ( L V "V GS Th ) = I D V GS "V Th = µc ox W L I D 34

18 In the real situation g m is smaller than the value predicted by the given simple equation. Moreover g m changes because of the dependence of! from the temperature, the transversal and the mean lateral electric field. " µ = µ T % 0 $ ' # T 0 & ( 3 " 1+ E y $ # SPICE uses the fitting equation: µ = µ 0 E crit % ' & (m 1 1+ V DS LE sat $ u crit " si & % C ox V GS #V on #u tra #V DS ( ) ' ) ( u exp 35 $ Linear region: Drain output conductance (g ds ) ( ) W g ds = µc ox L V "V "V GS Th DS $ Saturation region (first order): g ds = "I D Second order effects $ The channel length reduction has been calculated taking into account only the lateral drop voltage. A more accurate analysis gives: 1 "L # 1 "L (1 st order) ( ) + '( V GS &V sat ) + C (% V &V ox DS GS * $ S )* V DS &V sat + -,- 36

19 $ The threshold voltage depends on the V DS (short channel) $ The mobility depends on the lateral mean field V DS / L $ The avalanche effect increases I D Avalanche current Mobile charges, accelerated by electric field in the drain depleted region, creates, by impact ionization, electron-holes pair. 37 The drain current I D and a substrate current I B increase due to this contribution. $ The substrate current may contribute to latch-up $ The device noise increases $ The output impedance decreases $ Carriers can be trapped on the oxide and V Th changes (hot electron effect) 38

20 $ Avalanche current worse in n-channel More accurate expression of the output conductance: $V g ds = "I D # g Th m + I D $µ + $I S $V DS µ $V DS $V DS (first order) (short channel) (velocity saturation) (avalanching) 39 $ Linear region: Capacitances C i = C ox WL C dep = " Si x dep WL C gs = C gsov + C i C gd = C gdov + C i C sb = C js + C dep C db = C jd + C dep 40

21 $ In the saturation region C gs = C gsov + C i 3 C gd " C gdov C sb = C js + C dep 3 C db = C jd C j = C j 0 1" V # T C gb " 1 10 C i " T = KT q ln # N NA & D % ( $ n i ' 41 Noise Thermal noise Due to the finite output resistance: v nth "f = 4#kT 1 g m # = /3, for I D = 50 "A, (V GS - V Th ) = 300 mv, V nth = 5.6 nv/'hz If the bandwidth BW of the system is f - f 1, the input referred noise voltage is: f V v n = # nth df = 4 "f 3 kt 1 BW g m f 1 4

22 Flicker noise Due to the trapping and detrapping of carriers by surface states at different energy levels. Modeled as: i nf "f = K I f D k C c ox L f # v nf "f = i nf "f g = K f I D k m C c ox L f # g = K f k m µ C +1 c ox W L f # Typically ( ) 1, k f ) 1, k c + 1 ) 1, V nf = 40 nv/'hz at 1 khz with W L = 1000 "m. 43 The power of the flicker noise is concentrated at low frequency. V nf = f v # nf df = f 1 "f K f µ C ox W L ln $ f ' & ) % ( f 1 Noise spectra for n-channel and p-channel transistors. Boron implanted p-mos has low 1/f noise (buried channel) 44

23 Avalanche noise Due to the statistical fluctuation in the number of carriers of the avalanche current (shot noise). Modeled as: i nav "f = q I av v nav = v nth v nav "f = i nav "f g = q I av m W µ C ox L If we compare thermal noise and avalanche noise, we have: q I av µ C ox W I D g m 4 " k T = V GS #V Th 4 " k T L q we get comparable noise if I D / I av is of the same order of (V GS - V Th ) / (kt/q). The avalanche current at V DS = 5 V can be of the order of "A. I av I D I D 45 To minimize noise $ Thermal noise: $ use large g m (large W / L) $ use low series resistance (connection and gate resistance) $ Flicker noise: $ use large device area (W L) $ use thin oxide (high C ox ) $ use "clean" technology (low N SS ) $ try to get buried channel $ use p-channel devices $ Avalanche noise: $ reduce V DS $ use p-channel devices 46

24 Layout Rules $ Use poly connections only for signal, never for current because the offset R I # 15 mv. $ Minimize line length, especially for lines connecting high impedance nodes (if they are not the dominant node). $ Use matched structure. If necessary common centroid arrangement. $ Respect symmetries (even respect power devices). $ Only straight-line transistors. $ Separate (or shield) the input from the output line, to avoid feedback. $ Shielding of high impedance nodes to avoid noise injection from the power supply and the substrate. $ Regular shape. 47 Layout of transistors The MOS transistor is a overlap of two rectangles: active area (not protected, to originate the source and the drain) and polysilicon gate. Key points: $ parasitic resistance at source and drain must kept as low as possible $ parasitic capacitances must be minimized $ matching between paired elements is very important 48

25 $ Use multiple contacts. Many contacts placed close to each another make the surface of metal connection smoother, preventing micro-cracks in the metal. $ Splitting the transistor in a number of equal parts connected in parallel reduces the area of the transistor and its parasitic capacitances. Two layouts: The one on the left reduces parasitic capacitances by two; the one on the right reduces parasitic capacitances by four. 49 Matching is very important when we design current mirrors and differential pairs. Bad matching produces high offset. $ Transistors with different orientation match badly (left). $ Mismatch may occur if current flows in opposite directions (right). $ Physical and technological parameters may change in points of the chip that are relatively far away. 50

26 The best method of achieving good matching is shows in the following figure: $ Each transistor is split into four equal parts with a proper interleaving. For each pair of fingers of the same transistor currents flow in opposite directions. $ Any noisy signal affecting the substrate or the well should be sunk by the biasing and should not affect the circuit. 51