Integrated Circuits & Systems


 Preston Wiggins
 1 years ago
 Views:
Transcription
1 Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1
2 ualwell TrenchIsolated CMOS Process (Current) Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 10.2
3 Circuit Symbols for MOS Transistors NMOS G G S B as 4terminal device S As 3terminal device Major carriers are electrons PMOS G G S S Major carriers are holes B as 4terminal device As 3terminal device Slide 10.3
4 NMOS Transistor ZeroOrder Model (Perfect Switch) S S G = 0 G = 1 S S Switch off (no electric current) S Switch on Electric current flows until =S Slide 10.4
5 PMOS Transistor ZeroOrder Model (Perfect Switch) G = 0 S S S S Switch on Electric current flows until =S G = 1 Switch off (no electric current) S Slide 10.5
6 NMOS Transistor Structure S +  V GS G Field oxide n + n + psubstrate Gate oxide substrate (bulk) contact Slide 10.6
7 NMOS Transistor for V GS =0 S +  V GS G n + n + psubstrate pn junctions are off (0V bias) Extremely high resistance between drain and source Slide 10.7
8 NMOS Transistor (Increasing V GS ) S V GS + G  n + n + psubstrate Referred to as the MOS Capacitor Slide 10.8
9 The MOS Capacitor in Accumulation Poly gate Silicon oxide psubstrate V GS > 0 (but V GS <<V T ) Source: R. Reis 1999 Slide 10.9
10 The MOS Capacitor in epletion epletion region V GS = V T Negative charges repels mobile holes from the channel surface, thus creating a depletion region below the gate oxide (similar to the one occurring in a pnjunction diode). Source: R. Reis 1999 Slide 10.10
11 The MOS Capacitor in epletion epletion region V GS = V T epletion region width: W d = 2ε siφ qn A Qd = 2qNAεsiφ epletion region space charge per unit: where N A is the substrate doping and is the voltage across the depletion layer (i.e., the potential at the oxidesilicon boundary) φ Slide 10.11
12 The MOS Capacitor in Strong Inversion Inversion layer epletion region V GS > V T As V GS increases, the potential at the silicon surface reaches a critical value and the silicon surface inverts to ntype material. This point marks the beginning of a phenomenon known as strong inversion, which occurs when V GS equals twice the Fermi Potential ( φ F ~= 0.3V for typical ptype silicon substrates): φ F = φ T ln N A n i Slide 10.12
13 The MOS Capacitor in Strong Inversion Inversion layer epletion region V GS > V T Further increases in V GS produce no further changes in the depletion region width (but result in additional electrons in the inversion layer, coming from the n+ source region). Slide 10.13
14 The MOS Capacitor in Strong Inversion In the presence of an inversion layer, the charge stored in the depletion region is fixed and equals: Q B0 = 2qN A ε si 2φ F But when a substrate bias voltage V SB is applied between source and body, the potential required for strong inversion increases, becoming: 2φ F + V SB And the charge stored in the depletion region is then expressed by: Q B = 2qN A ε si (( 2)φ F + V SB ) Slide 10.14
15 The Threshold Voltage The value of V GS where strong inversion occurs is called the threshold voltage (V T ) V T is function of several components (most are material constants): The oxide thickness The Fermi voltage The charge of impurities trapped at the surface between channel and gate oxide osage of ions implanted for threshold adjustment Slide 10.15
16 The Threshold Voltage and The Body Effect V SB has an impact on V T! V T under different bodybiasing conditions can be calculate by: V T = V T 0 + γ ( ( 2)φ F + V SB 2φ ) where V T0 is the V T for V SB =0, and coefficient. γ is called the bodyeffect V T0 is positive for NMOS transistor and negative for PMOS transistor Slide 10.16
17 The Threshold Voltage and The Body Effect Effect of Well Bias on the Threshold of an NMOS Transistor (assuming 2φ F = 0.6V and γ = 0.4V 0.5 ) V BS < 0 is equivalent to V SB > 0 V GS >0  + G n + n + psubstrate B In NMOS, V SB > 0.6 V to avoid diodes from being forward biased Slide 10.17
18 Inversion Mode: V GS > V T S V GS + G n + n + psubstrate epletion region Inversion layer (N channel) A channel between drain and source is created But no current flows in such channel Slide 10.18
19 Linear Region*: V GS > V T and V S < V GS V T (small V S ) S V GS + G V S < V GS V T I S n + n + psubstrate V(x) + L There is a continuous conductive channel between source and drain Current flows from drain to source * Also called Resistive or Nonsaturated or Triode Region Slide 10.19
20 Linear Region: V GS > V T and V S < V GS V T (small V S ) S V GS + G V S < V GS V T I S psubstrate V(x) + n + n + L If we know the amount of charge in the channel and the rate it moves, we can compute the current in the channel. Slide I = ΔQ Δt
21 Linear Region: V GS > V T and V S < V GS V T (small V S ) S V GS + G V S < V GS V T V(x) + n + n + L I S V GS + V(x) + + V GC x psubstrate At a point x along the channel, the voltage is V(x) and the gatetochannel voltage ( V GC ) at such point equals V GS V(x). Slide 10.21
22 Linear Region: V GS > V T and V S < V GS V T (small V S ) S V GS + G V S < V GS V T I S n + n + psubstrate V(x) + L Assuming that V GS V(x) > V T, the induced channel charge per unit area at point x can be computed by: Q i (x) = C ox [ V GS V (x) V T ] where and C ox = ε ox t ox Is the capacitance per unit area of the gate oxide ε ox = 3.97 ε 0 = F /m Slide 10.22
23 Linear Region: V GS > V T and V S < V GS V T (small V S ) Induced channel charge per unit area at point x (from previous slide): Q i (x) = C ox [ V GS V (x) V T ] I can be computed by: I = v n (x)q i (x)w drift velocity of carries available charge but v n = µ n ξ(x) = µ n dv dx Mobility (m 2 /V.s) Slide 10.23
24 Linear Region: V GS > V T and V S < V GS V T (small V S ) Combining the 3 equations in the previous slide leads to: Integrating over L leads to: I dx = µ n C ox W(V GS V V T )dv This term can be ignored for small values of V S W I = k' n L (V GS V T )V S V S 2 2 = k n (V GS V T )V S V S 2 2 Process transconductance parameter: k' n = µ n c ox = µ nε ox t ox Transistor gain factor: W k n = k' n L = µ W nc ox L Slide 10.24
25 Beginning of Saturation : V GS > V T and V S = V GS V T S V GS + G V S = V GS V T I S n + n + psubstrate At points x where V GS V(x) < V T the induced charge is zero and the conducting channel disappears. L V GS V(x=L) < V T and channel is pinchedoff Slide 10.25
26 Saturation Region: V GS > V T and V S > V GS V T S V GS + G V S > V GS V T I S n + V n + GS V T + psubstrate L Voltage difference over the channel (from pinchoff point to source) remains fixed at V GS V T, and I remains constant Slide 10.26
27 Saturation Region: V GS > V T and V S > V GS V T Replacing V S by V GS V T in the equation below W I = k' n L (V GS V T )V S V S 2 Yields the drain current for the saturation region: 2 I = k' n 2 W L (V GS V T ) 2 Notice: The square dependency I between and V GS I is no longer function of V S Slide 10.27
28 Channel Length Modulation I = k' n 2 A more accurate description of I is: W L (V GS V T )2 Increasing V S causes the depletion region at the drain junction to grow, reducing the length of the effective channel! I = I '(1+ λv S ) λ is an empirical parameter called channel length modulation (proportional to the inverse of the channel length). Slide 10.28
29 Velocity Saturation MOSFET When electric field along the channel reaches, the velocity of carriers tends to saturate (due to scattering effects) For a 0.25µm NMOS, only about 2V between drain and source are needed to reach velocity saturation Very pronounced in shortchannel NMOS v = ξ c µ nξ 1+ ξ /ξ c for ξ = ξ c v = v sat for ξ = ξ c Continuity requires that: ξ c = 2v sat /µ n Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 10.29
30 MOSFET Velocity Saturation (I for Linear Region) Replacing to: ξ c = 2v sat /µ n where κ(v ) = in the I equation for the linear region leads µ I = n C ox W 1+ (V S /ξ c L) L 1 1+ (V /ξ c L) (V GS V T )V S V S 2 = 2 W = µ n C ox (V L GS V T )V S V S 2 κ(v S ) 2 measures the degree of saturation and V S /L can be interpreted as the average field in the channel For longchannel devices (large L) or small V S, κ 1 For shortchannel devices, κ <1 and the derived current is less than it would normally be Slide 10.30
31 Velocity Saturation (I for Saturation Region) Increasing V S the electric field in the channel ultimately reaches the critical value and the carriers at the drain become velocity saturated. Assuming that drift velocity is saturated (= v sat ) in the former equation: I SAT = v sat C ox W(V GT VSAT) W = κ(v SAT )µ n C ox V L GT V SAT V S 2 2 where V SAT = κ(v GT )V GT (with V GT = V GS V T ) measures the degree of saturation Slide 10.31
32 Velocity Saturation (Perspective) For shortchannel devices and for large enough values of V GT, is substantially less than 1 and thus V SAT < V GT κ(v GT ) The saturation current I SAT displays a linear dependency w.r.t. V GS Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 10.32
33 Velocity Saturation Revisited Approximations made to simplify manual calculation 1. Velocity saturates abruptly at v = µ n ξ ξ c for ξ = ξ c v = v sat = µ n ξ c for ξ = ξ c 2. V SAT at which the critical electric field is reached and velocity saturation comes into play is constant and approximated as V SAT Lξ c = Lv sat µ n Slide 10.33
34 Velocity Saturation Revisited 1. Current equations for resistive region remain the same as for longchannel devices: W I = k' n L (V GS V T )V S V S 2 2 = k n (V GS V T )V S V S Once V SAT is reached the current abruptly saturates: I SAT = I (V S = V SAT ) W = µ n C ox (V L GS V T )V SAT V SAT 2 2 = v sat C ox W V GS V T V SAT 2 2 Slide 10.34
35 I V S Characteristics of NMOS (IV Curves) I (A 6 x 104 VGS = 2.5 V V S = V GS  V T Resistive Saturation V GS = 2.0 V V GS = 1.5 V V GS = 1.0 V Quadratic dependence on V GS I (A x V S = V GS  V T V = 2.5 V GS V SAT = κ(v GT )V GT Velocity Saturation V GS = 2.0 V V GS = 1.5 V V GS = 1.0 V Linear dependence on V GS V S (V) Longchannel NMOS (W/L = 1.5 and L d =10 µm) V S (V) Shortchannel NMOS (W/L=1.5 and L d =0.25 µm) Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 10.35
36 I V GS Characteristics of NMOS (IV Curves) 6 x 104 V S = 2.5 V (NMOS devices are saturated) 2.5 x 104 I (A) Subthreshold conductance Source: Rabaey; Chandrakasan; Nikolic, 2003 quadratic V GS (V) Longchannel NMOS (W/L = 1.5 and L d =10 µm) I (A Subthreshold conductance quadratic linear V GS (V) Shortchannel NMOS (W/L=1.5 and L d =0.25 µm) Slide 10.36
37 I V S Characteristics of PMOS 0" x 10"4" V GS = 1.0V I (A 0.2" 0.4" 0.6" V GS = 1.5V V GS = 2.0V The polarities of all voltages and currents are reversed 0.8" V GS = 2.5V 1" 2.5" 2" 1.5" 1" 0.5" 0" V S (V) Shortchannel PMOS (W d =0.375 and L d =0.25 µm, W/L=1.5 ) Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide 10.37
38 NMOS x PMOS (IV Curves) Minimumsize (shortchannel) NMOS and PMOS (W d =0.375 and L d =0.25 µm, W/L=1.5 ) 4 x V S = V GS  V T V = 2.5 V GS V SAT = κ(v GT )V GT Velocity Saturation V GS = 2.0 V 0.2" 0.4" 0" x 10"4" V GS = 1.0V V GS = 1.5V I (A 1 V GS = 1.5 V I (A 0.6" V GS = 2.0V 0.5 V GS = 1.0 V 0.8" V GS = 2.5V V S (V) Source: Rabaey; Chandrakasan; Nikolic, 2003 Slide " 2.5" 2" 1.5" 1" 0.5" 0" V S (V) Velocity saturation is less pronounced in PMOS (due to higher value of critical electrical field, resulting from smaller mobility of holes)
39 References MOSFET 1. RABAEY, J; CHANRAKASAN, A.; NIKOLIC, B. igital Integrated Circuits: a design perspective. 2 nd Edition. Prentice Hall, ISBN: WESTE, Neil; HARRIS, avid. CMOS VLSI esign: a circuits and systems perspective. AddisonWesley, 4 th Edition, ISBN Slide 10.39
CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationDigital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationFIELDEFFECT TRANSISTORS
FIELEFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancementtype NMOS transistor 3 IV characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation
More informationMOS Transistor IV Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor IV Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationMOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 14 The CMOS Inverter: dynamic behavior (sizing, inverter
More informationThe Devices: MOS Transistors
The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, AddisonWesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor
More informationLecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I curve (SquareLaw Model)
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationToday s lecture. EE141 Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
 Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
More informationLecture 12: MOSFET Devices
Lecture 12: MOSFET Devices GuYeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
More informationCourse Administration. CPE/EE 427, CPE 527 VLSI Design I L04: MOS Transistors. Review: CMOS Process at a Glance
Course Administration CPE/EE 7, CPE 7 VLI esign I L: MO Transistors epartment of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic ( www.ece.uah.edu/~milenka
More informationVLSI Design I; A. Milenkovic 1
Review: implified CMO Inverter Process CPE/EE 7, CPE 7 VLI esign I L: MO Transistor cut line epartment of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic (
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationLecture 5: CMOS Transistor Theory
Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos IV Characteristics
More informationChapter 2 CMOS Transistor Theory. JinFu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 2 CMOS Transistor Theory JinFu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor JinFu Li, EE,
More informationEE5311 Digital IC Design
EE5311 Digital IC Design Module 1  The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM
More informationEE105  Fall 2005 Microelectronic Devices and Circuits
EE105  Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture
More informationEEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationImportant! EE141 Fall 2002 Lecture 5. CMOS Inverter MOS Transistor Model
 Fall 00 Lecture 5 CMO Inverter MO Transistor Model Important! Lab 3 this week You must show up in one of the lab sessions this week If you don t show up you will be dropped from the class» Unless you
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOS Capacitor with External Bias
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 5: Januar 6, 17 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation! Level
More informationEE105  Fall 2006 Microelectronic Devices and Circuits
EE105  Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models MOS
More informationThe Devices. Jan M. Rabaey
The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models
More informationMOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA
MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the FieldEffect Transistor! Julius Lilienfeld filed a patent describing
More informationLecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos IV Characteristics pmos IV Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 2017 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2017 Khanna Lecture Outline! Semiconductor Physics " Band gaps "
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!
More informationChapter 4 FieldEffect Transistors
Chapter 4 FieldEffect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 41 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model
ELEC 3908, Physical Electronics, Lecture 23 The MOSFET Square Law Model Lecture Outline As with the diode and bipolar, have looked at basic structure of the MOSFET and now turn to derivation of a current
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationMOSFET Physics: The Long Channel Approximation
MOSFET Physics: The ong Channel Approximation A basic nchannel MOSFET (Figure 1) consists of two heavilydoped ntype regions, the Source and Drain, that comprise the main terminals of the device. The
More informationMOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor
MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET Calculation of t and Important 2 nd Order Effects SmallSignal Signal MOSFET Model Summary Material from: CMOS LSI Design By Weste
More informationThe Intrinsic Silicon
The Intrinsic ilicon Thermally generated electrons and holes Carrier concentration p i =n i ni=1.45x10 10 cm3 @ room temp Generally: n i = 3.1X10 16 T 3/2 e 1.21/2KT cm 3 T= temperature in K o (egrees
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 16 CMOS Combinational Circuits  2 guntzel@inf.ufsc.br
More informationLecture 11: MOS Transistor
Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Crosssection and layout
More information! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cutoff. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br
More informationVLSI Design The MOS Transistor
VLSI Design The MOS Transistor Frank Sill Torres Universidade Federal de Minas Gerais (UFMG), Brazil VLSI Design: CMOS Technology 1 Outline Introduction MOS Capacitor nmos IV Characteristics pmos IV
More informationLecture 12: MOS Capacitors, transistors. Context
Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those
More informationLong Channel MOS Transistors
Long Channel MOS Transistors The theory developed for MOS capacitor (HO #2) can be directly extended to MetalOxideSemiconductor FieldEffect transistors (MOSFET) by considering the following structure:
More informationECE315 / ECE515 Lecture2 Date:
Lecture2 Date: 04.08.2016 NMOS I/V Characteristics Discussion on I/V Characteristics MOSFET Second Order Effect NMOS IV Characteristics ECE315 / ECE515 Gradual Channel Approximation: Cutoff Linear/Triode
More informationLecture 04 Review of MOSFET
ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D
More informationPractice 3: Semiconductors
Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 29, 2019 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2019 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationMicroelectronics Part 1: Main CMOS circuits design rules
GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! medamine.miled@polymtl.ca!
More informationFinal Examination EE 130 December 16, 1997 Time allotted: 180 minutes
Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and crosssectional area 100µm 2
More informationMOS Transistor. EE141Fall 2007 Digital Integrated Circuits. Review: What is a Transistor? Announcements. Class Material
EEFall 7 igital Integrated Circuits MO Transistor Lecture MO Transistor Model Announcements Review: hat is a Transistor? Lab this week! Lab next week Homework # is due Thurs. Homework # due next Thurs.
More informationOperation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS
Operation and Modeling of The MOS Transistor Second Edition Yannis Tsividis Columbia University New York Oxford OXFORD UNIVERSITY PRESS CONTENTS Chapter 1 l.l 1.2 1.3 1.4 1.5 1.6 1.7 Chapter 2 2.1 2.2
More informationIntroduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline
Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and
More informationB.Supmonchai June 26, q Introduction of device basic equations. q Introduction of models for manual analysis.
June 26, 2004 oal of this chapter Chapter 2 MO Transistor Theory oonchuay upmonchai Integrated esign Application Research (IAR) Laboratory June 16th, 2004; Revised June 16th, 2005 q Present intuitive understanding
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More informationECEN474/704: (Analog) VLSI Circuit Design Spring 2018
ECEN474/704: (Analog) SI Circuit Design Spring 2018 ecture 2: MOS ransistor Modeling Sam Palermo Analog & MixedSignal Center exas A&M University Announcements If you haven t already, turn in your 0.18um
More informationFundamentals of the Metal Oxide Semiconductor FieldEffect Transistor
Triode Working FET Fundamentals of the Metal Oxide Semiconductor FieldEffect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the
More informationP. R. Nelson 1 ECE418  VLSI. Midterm Exam. Solutions
P. R. Nelson 1 ECE418  VLSI Midterm Exam Solutions 1. (8 points) Draw the crosssection view for AA. The crosssection view is as shown below.. ( points) Can you tell which of the metal1 regions is the
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOSFET NType, PType. Semiconductor Physics.
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 217 MOS Transistor Theory, MOS Model Lecture Outline! Semiconductor Physics " Band gaps " Field Effects! MOS Physics " Cutoff
More information! PN Junction. ! MOS Transistor Topology. ! Threshold. ! Operating Regions. " Resistive. " Saturation. " Subthreshold (next class)
ESE370: ircuitlevel Modeling, Design, and Optimization for Digital Systems Lec 7: September 20, 2017 MOS Transistor Operating Regions Part 1 Today! PN Junction! MOS Transistor Topology! Threshold! Operating
More informationThe Gradual Channel Approximation for the MOSFET:
6.01  Electronic Devices and Circuits Fall 003 The Gradual Channel Approximation for the MOSFET: We are modeling the terminal characteristics of a MOSFET and thus want i D (v DS, v GS, v BS ), i B (v
More informationQuantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current.
Quantitative MOSFET Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. V DS _ n source polysilicon gate y = y * 0 x metal interconnect to
More informationThe Devices. Devices
The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ FieldOxyde (SiO 2 ) psubstrate p+ stopper Bulk Contact CROSSSECTION of NMOS Transistor CrossSection of CMOS Technology MOS transistors
More informationESE370: CircuitLevel Modeling, Design, and Optimization for Digital Systems. Today. Refinement. Last Time. No Field. Body Contact
ESE370: CircuitLevel Modeling, Design, and Optimization for Digital Systems Day 10: September 6, 01 MOS Transistor Basics Today MOS Transistor Topology Threshold Operating Regions Resistive Saturation
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 18 CMOS Sequential Circuits  1 guntzel@inf.ufsc.br
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 13 The CMOS Inverter: dynamic behavior (delay) guntzel@inf.ufsc.br
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon
More informationCharge Storage in the MOS Structure. The Inverted MOS Capacitor (V GB > V Tn )
The Inverted MO Capacitor (V > V Tn ) We consider the surface potential as Þxed (ÒpinnedÓ) at φ s,max =  φ p φ(x).5 V. V V ox Charge torage in the MO tructure Three regions of operation: Accumulation:
More informationLecture 11: MOSFET Modeling
Digital Integrated Circuits (83313) Lecture 11: MOSFET ing Semester B, 201617 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 18 June 2017 Disclaimer: This course was prepared, in its entirety,
More information6.012 Electronic Devices and Circuits Spring 2005
6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) OPEN BOOK Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):
More informationECE305: Fall 2017 MOS Capacitors and Transistors
ECE305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525530, 563599) Professor Peter Bermel Electrical and Computer Engineering Purdue
More informationNon Ideal Transistor Behavior
Non Ideal Transistor Behavior Slides adapted from: N. Weste, D. Harris, CMOS VLSI Design, Addison Wesley, 3/e, 2004 1 Nonideal Transistor IV effects Non ideal transistor Behavior Channel Length ModulaJon
More informationECE321 Electronics I
EE31 Electronics I Lecture 8: MOSET Threshold Voltage and Parasitic apacitances Payman ZarkeshHa Office: EE Bldg. 3B Office hours: Tuesday :3:PM or by appointment Email: payman@ece.unm.edu Slide: 1
More informationMOS CAPACITOR AND MOSFET
EE336 Semiconductor Devices 1 MOS CAPACITOR AND MOSFET Dr. Mohammed M. Farag Ideal MOS Capacitor Semiconductor Devices Physics and Technology Chapter 5 EE336 Semiconductor Devices 2 MOS Capacitor Structure
More informationIntroduction and Background
Analog CMOS Integrated Circuit Design Introduction and Background Dr. Jawdat AbuTaha Department of Electrical and Computer Engineering Islamic University of Gaza jtaha@iugaza.edu.ps 1 Marking Assignments
More information! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cutoff. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 9, 019 MOS Transistor Theory, MOS Model Lecture Outline CMOS Process Enhancements Semiconductor Physics Band gaps Field Effects
More informationLECTURE 3 MOSFETS II. MOS SCALING What is Scaling?
LECTURE 3 MOSFETS II Lecture 3 Goals* * Understand constant field and constant voltage scaling and their effects. Understand small geometry effects for MOS transistors and their implications modeling and
More informationEE 560 MOS TRANSISTOR THEORY
1 EE 560 MOS TRANSISTOR THEORY PART 1 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE ptype doped Si (N A = 10 15 to 10 16 cm 3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM:
More informationSemiconductor Physics Problems 2015
Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and MK Lee 1. The purest semiconductor crystals it is possible
More informationExtensive reading materials on reserve, including
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationMetaloxidesemiconductor field effect transistors (2 lectures)
Metalidesemiconductor field effect transistors ( lectures) MOS physics (brief in book) Currentvoltage characteristics  pinchoff / channel length modulation  weak inversion  velocity saturation 
More informationClassification of Solids
Classification of Solids Classification by conductivity, which is related to the band structure: (Filled bands are shown dark; D(E) = Density of states) Class Electron Density Density of States D(E) Examples
More informationLecture 23: Negative Resistance Osc, Differential Osc, and VCOs
EECS 142 Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California,
More informationECE 497 JS Lecture  12 Device Technologies
ECE 497 JS Lecture  12 Device Technologies Spring 2004 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density
More informationEE105  Fall 2006 Microelectronic Devices and Circuits. Some Administrative Issues
EE105  Fall 006 Microelectronic evices and Circuits Prof. Jan M. Rabaey (jan@eecs Lecture 8: MOS Small Signal Model Some Administrative Issues REIEW Session Next Week Tu Sept 6 6:007:30pm; 060 alley
More informationLongchannel MOSFET IV Corrections
Longchannel MOSFET IV orrections Three MITs of the Day The body ect and its influence on longchannel V th. Longchannel subthreshold conduction and control (subthreshold slope S) Scattering components
More information! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February, 07 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance Model!
More informationStudent Number: CARLETON UNIVERSITY SELECTED FINAL EXAMINATION QUESTIONS
Name: CARLETON UNIVERSITY SELECTE FINAL EXAMINATION QUESTIONS URATION: 6 HOURS epartment Name & Course Number: ELEC 3908 Course Instructors: S. P. McGarry Authorized Memoranda: Nonprogrammable calculators
More informationCHAPTER 5 MOS FIELDEFFECT TRANSISTORS
CHAPTER 5 MOS FIELDEFFECT TRANSISTORS 5.1 The MOS capacitor 5.2 The enhancementtype NMOS transistor 5.3 IV characteristics of enhancement mode MOSFETS 5.4 The PMOS transistor and CMOS technology 5.5
More informationLecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor
Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE15 Spring 28 Lecture
More information1 cover it in more detail right away, 2 indicate when it will be covered in detail, or. 3 invite you to office hours.
14 1 8 6 IBM ES9 Bipolar Fujitsu VP IBM 39S Pulsar 4 IBM 39 IBM RY6 CDC Cyber 5 IBM 4381 IBM RY4 IBM 381 Apache Fujitsu M38 IBM 37 Merced IBM 36 IBM 333 Vacuum Pentium II(DSIP) 195 196 197 198 199 NTT
More informationLecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor
Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics t ti Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE105 Fall 2007
More information