MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA


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1 MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA
2 1930: Patent on the FieldEffect Transistor! Julius Lilienfeld filed a patent describing a threeelectrode amplifying device based on the semiconducting properties of copper sulfide. He did not demonstrate the device experimentally 2
3 MOS Transistor Demonstrated! Dawon Kahng John Atalla John Atalla and Dawon Kahng at Bell demonstrate the first successful MOS fieldeffect amplifier. 3
4 Outline Currentvoltage characteristics! Scaling and short channel behavior! Future MOS technologies! 4
5 MOS Transistor! The theory developed for the MOS capacitor can be extended directly to the MOS FieldEffectTransistor (MOSFET) by considering the following structure.! V g 0 y L n + source n + drain depletion region polysilicon gate x z ptype substrate Vbs gate oxide inversion channel V ds Enhancement mode MOSFET W V G provides control of surface carrier densities: Q=CV! For V G << V T, the structure consists of two diodes back to back and only leakage currents flow.! When V G is only slightly below V T a depletion region will be formed.! For V G > V T, an inversion layer, i.e., a conducting channel, exists between source and drain and current will flow.! For any further increase in V G the excess potential will result in an increase in the electron density in the channel! 5
6 NMOS Transistor 3D Band Diagram! Nchannel enhancement mode MOSFET, V T > 0! Pchannel enhancement mode MOSFET, V T < 0! V G = V D = 0 no carriers in the channel! electron current V G > 0, V D = 0 carriers in the channel but no movement between source and drain! V G > V T,, V D > 0 electrons flow from source to drain! Source: Sze (1981) 6
7 Variation of Drain Current with V D! (a) N+ Inversion Layer V (+) P G Depletion Region N+ +V D (small) Ι D I D Linear region! I D α V D! V D (b) N+ P V (+) G N+ +V D Ι D I D Before pinch off! V D (c) N+ Inversion layer pinches off V V D = V G D SAT ID N+ P Inversion layer pinch off! Onset of saturation! V D (d) N+ N+ Inversion layer ends V V D > V G D SAT I D P V D Saturation region I D constant with V D. (Assumption valid only for long channel)! 7
8 Complementary MOS (CMOS) Technology Nchannel MOSFET V g > 0 Pchannel MOSFET V g < 0 < 0 All the polarities for Pchannel MOSFET are opposite to that of Nchannel MOSFET 8
9 Currentvoltage characteristics! Increase in V G will result in an increase in the electron density in the channel and thus the drain current.! After pinch off drain current saturates.! Nchannel MOSFET Pchannel MOSFET I DS V DS V GS V G < V T! V GS V DS I DS For Pchannel MOSFET, all of the polarities are reversed and the inversion layer exists for V G < V T! 9
10 CMOS Inverter! V DD V DD PMOS R p V in V out V out V out NMOS R n V in = V DD V in = 0 For V g < V t the transistor is off represented by open circuit! For V g > V t the transistor is on represented by a resistor! Output is an inverted form of input waveform! CMOS inverter is the most important building block of modern logic circuits! What is the power dissipation in this circuit?! 10
11 Gradual Channel Approximation! Linear Region (small V D )! Beyond Pinchoff! p y Vertical field E x inversion layer charge! Lateral field E y flow of carriers from source to drain! Ex ρ ( x) = x ε si C ox V g = (Q i + Q d ) Q i = C ox ( Vg Vt ) inversion depletion 11 E x x E + y y = ρ ( x, y) ε E E x y >> x y Qi ( y) Cox ( Vg V ( y) Vt ) si
12 Current Voltage Dependence! dn(y) J e (y) = qd n dy Diffusion! + qµ n n(y)ε y Drift! Charge/Area! Q i (y) = qn s (y) C ox (V g V(y) V t ) y dq ( y) dy n s J J e e dv ( y dy i ) Cox 0 ( y) = n( x, y) dx & = q$ D % = D n n d ( Q ( y) / q) i dy & dqi ( y) # $! + µ nq % dy " i Sheet Charge density!, dv ( y) )# ( Q ( y) / q) * '! " + µ Current / Width (zdirection)! n i + dy ( & dv ( y) # ( y) $! % dy " 12 (1)!
13 Current vs Voltage! J e = D n & dqi ( y) # $! + µ nq % dy " i & dv ( y) # ( y) $! % dy " Diffusion! Drift! y Note that E y and Q i (y) are negative! When V GS >V T & V DS >V T diffusion current is negligible!! J J e L e 0 = µ Q ( y) n dy = µ C i n ox dv ( y) dy V DS 0 ( V GS V V t ) dv J D = W L µ # nc ox (V GS V t )V DS 1 2 V 2 DS $ % Qi ( y) Cox ( Vg V ( y) Vt ) & ( (2)! ' 13
14 For the case where backside is grounded (V B = 0) V T is given by the equation,! Threshold Voltage! V T = V FB + t ox 2ε ε s qn ( a 2 φ ) p 2φ p ox (3)! In many circuit applications backside is biased. For finite value of V B! V G = V FB + V ox + φ s  φ p + V B N+ V G N+ D P V B 14
15 Effect of Back Bias! V B = 0 V B < 0 15
16 Effect of Back Bias! In a normal MOS capacitor, application of V B will result mostly in change in V ox as φ s is fixed at φ p. If there is a nearby ntype region (drain) which contacts with the inverted surface layer the situation changes. When the surface is inverted, there is basically a PN junction at the surface. A reverse bias can be applied across the PN junction. If V B is zero, inversion occurs when φ s = φ p. If V B < 0, the semiconductor still attempts to invert when φ s reaches φ p. However, with V B < 0 any inversionlayer carriers that do appear at the semiconductor surface migrate laterally into the source and drain because these regions are at a lower potential. Not until φ s = φ p  V B, will the surface invert and normal transistor action begin. In essence, back biasing changes the inversion point in the semiconductor from φ p to φ p  V B. 16
17 Effect of Back Bias! An applied reverse bias between the induced surface nregion and the bulk increases the charge Q d in the depletion region. Since the negative charge induced by V G  V B is shared between the depletion and inversion layers, an increase of the charge in the depletion layer means that there is less charge available to form the inversion layer for a given gate voltage. Looked at another way, more gate voltage must be applied to induce the same number of electrons in the inversion layer when there is a reverse bias. With reverse bias present, the surface potential at the onset of strong inversion becomes φ s = φ p + (V D  V B ) rather than φ s = φ p. 17
18 With V D and V B applied: x dmax = 2κ sε o ( 2φ p +V D V B ) qn a V T = V D + V FB + t ox 2 K s ε o qn ( a V D 2φ p V ) B 2φ (4) p ε ox where ' C ox = ε ox t ox A = C ox A 18
19 For small values of V D and V B = 0, Expression for I D can be approximated by!!!!!!!!!!!!! This is known as LINEAR REGION.! These equations are valid only as long as an inversion layer exists all the way from source to drain (LINEAR REGION).! As V D, the effective voltage between the gate and the channel near the drain will become less than V T. This happens when V G  V T = V D. This value of drain voltage is called the saturation voltage V DSAT (or pinch off voltage because the channel is pinched off at the drain), and for higher drain voltages, a channel will not exist all the way to the drain.! I D = W L µ n ε ox t ox $ (V GS V t )V DS 1 2 V 2 DS % & N+ Inversion layer ends (pinches off) V V D > V G P ' ( ) W L µ ε ox n (V GS V t )V DS t ox N+ D SAT Depletion Region (5) 19
20 V V D > V G D SAT N+ Inversion layer ends (pinches off) P N+ Depletion Region Electrons drift along in the inversion layer and are injected into the depletion region. There the high electric field pulls them into the drain.! Further increase in V D does not change I D (to first order), I D is constant for V D > V DSAT (SATURATION REGION).! Exact V DSAT can be derived by letting Q I (y=l) = 0 in equation!! Q Q ( L) C ( V V, V ) = 0 i i ( y) Cox ( Vg V ( y) Vt ) ox g!!!!!!! V = ( V!! D, Sat! g! t!!!(6)! D V Sat ) 20 t!
21 If (6) is substituted into (5), the saturation current is!!!!!!!!!(7)! I DSAT W 2L µ n ε ox ( ) 2 t ox V G V T Further increase in V D does not change I D (to first order), I D constant for V D > V DSAT! SATURATION REGION.! 21
22 Why does the current remain constant past pinchoff (saturation): 5V V G> V T S N+ N+ D P Depleted Why doesn t increasing V D also increase I? If the current is constant, then the electric field, Ε, must also be constant along most of the channel. 22
23 Why the current remains constant past pinchoff (saturation):! 5V V G> V T S Voltage N+ N+ P Depleted D Near pinchoff, the voltage is decreasing approximately linearly, hence the Ε field is relatively constant throughout.! 23
24 Why the current remains constant past pinchoff (saturation):! 10V V G> V T S Voltage N+ N+ P Depleted D At higher V d, there is a larger depleted region, hence, greater voltage drop.! Ε is still linear in the channel but very large in depletion region.! Carriers rapidly get swept out of depletion region! 24
25 Exact Expressions! V T ( y) = V FB + 1 C ox! [ ( ( ))] 2φ p + V( y) 2ε s qn a 2φ p V B V y Q I ( y) = " [ ( )] + 2ε s qn a 2 φ p V B + V( y) C ox V G V FB + 2φ p V y [ ] I D = W L µ + % n C ox " V G V FB + 2φ p V ( D, & ' 2 ) * V D 23 2qε N % s a ' V D 2 φ p V B & ( ) 3 2 ( 2φ p V B ) 3 2 (/ * 0 ) 1 V DSAT = V G V FB + 2φ p + q ε s N a % & ( % 2 C ox '( ( ) q ε s N a C 2 ox V G V FB V B ) + * + 25
26 What about the Diffusion Current?! V GS =0 V DS =0! E c! J e = D n & dqi ( y) # $! + % dy " µ Q n i & dv ( y) # ( y) $! % dy " E f! Diffusion! Drift! E c! E fn! E v! E v! V GS ~0 V DS =+V DD! V DD! Subthreshold regime Most of the V DS drops across the reversebiased SD Junction. The Channel bands are still ~ flat. Therefore J drift is negligible Gradient of free carriers along channel is large. Diffusion component J diffusion dominates. 26
27 Subthreshold Behavior! I D Log[I D ] Fermi Dirac distribution channel Subthreshold current Ideal source V T V GS V GS V G When the surface is in weak inversion (i.e., 0 < φ s < φ p, V G < V T ), a conducting channel starts to form and a low level of current flows between source and drain.! Diffusion current due to carriers from source spilling over source barrier into channel due to application of V G to lower φ s! Weak dependence on V DS in longchannel FET! drain 27
28 I OFF Log[I D ] V T Subthreshold Conduction! $ I ON Q e (y) exp φ ' s Inversion charge & ) % kt /q( Subthreshold swing S is limited to mkt/q V G φ S = where Drain current C ox C ox + C S ( ( ) = V G V T ) V G V T m m = C + C ox S C ox $ I D Q e exp V G V T ' & ) % mkt /q( V G! φ s C ox C s = Channel Capacitance S = Subthreshold swing V G (logi D ) = V G φ S Gate to channel potential coupling m > 1 in MOSFET φ S (logi D ) = $ 1+ C S & % C ox ' ) kt ( q 60 mv/dec due to FermiDirac distribution 28
29 V T Extraction " I DSAT W 2 L µ n = W 2 L µ n V D = V G!! ε ox ( V G V T ) 2 t ox ε ox ( V D V T ) 2 t ox The intercept of I D vs V D gives the value of threshold voltage V T. This technique is widely used to extract the value of V T.! The region depicted by the dotted curve below V T is the WEAK INVERSION REGION.! 29
30 Effect of Substrate (Back Gate) Bias! For small V D N+ V P G V B N+ The change in V T due to V B is described as! D [ ]! ΔV! T = 1! 2ε C # s qn! a! 2φ p V! B! 2φ p!!(8)! ox!!!!!!!!!! 1 2ε C ox # s qn a V B = γ V B V T = V FB + t ox 2 K s ε o qn ( a 2φ p V ) B 2φ p ε ox 30 The body voltage (or backside bias) makes it easier or harder to reach inversion: > Change in threshold voltage (V T ). (9)!
31 Where!! γ = 1 2ε!! C #! s qn! a = body factor (10) ox!!!!! Equations (5) and (7) can be used to approximate the IV characteristic if V T is replaced with V T + V T.! 31
32 Channel Length Modulation! V G V D > V D SAT N+ V D 2 V D1 N+ P In the saturation region, as V D é, the depletion region near drain expands, the pinchoff point of the channel moves back towards source. The effective channel becomes shorter, I D é because it is proportional to µ/l eff. The depletion region expands as V D assuming a step junction. Provided the device has a channel length >> ΔX D then the change in channel length is approximated by difference in the depletion width of a step junction. Δ L 2 ε s q N a V D V DSAT ( ) (11) 32
33 The decrease in L is responsible for an increase in I D in the saturation region.!! Ι D Therefore, a finite output impedance results. For most applications, this is modeled as! ( ) 2 ( 1+ λv D )! I DSAT =! W!!!!!!!! 2L µ n C ox " V G V T (12) where λ = channel length modulation parameter! V D 33
34 Circuit Models! The MOS transistor may be modeled in the following manner, by inspection of its physical structure. V V V 34
35 Of the elements in the model, only the gate to channel capacitance is essential; the rest are parasitic elements which degrade performance. Technology improvements are generally designed to reduce these parasitics. In many cases, the equivalent circuit can be reduced to the following for small signals: G C GD D C GS g V m G r ds C DB S Note that many of the parameters in the model are voltage sensitive. Accurate large signal model usually requires computer techniques. 35
36 Transconductance, g m! Defined from the I D V D characteristics in both the linear and saturation regions I D = W L µ ε ox n [ V t G V T ]V D ox I DSAT W 2 L µ n ε ox ( V t G V T ) 2 ox The transconductance or gain of the device is defined as: g m = I D V G V D = const 36
37 g m = I D V G V D = const W L µ n ε ox t ox V D W L µ n ε ox t ox for V D < V DSAT, linear region ( V G V T ) for V D >V DSAT, saturation region (13) B. Gate Capacitances, C GS and C GD The gate capacitances vary as the device moves from the linear to saturation region, C GS = 1/2 C ox to 2/3 C ox from linear to saturation (14) C GD = 1/2 C ox to 1/3 C ox from linear to saturation (15) 37
38 Output Impedance, r ds! The output impedance or resistance of the device is defined as: r ds = V D I D & W ( L µ n ' V G = const ε ox t ox 1 ( ) V G V T ) + * for V D < V DSAT, linear region 1 λi D for V D > V DSAT, saturation region (16) Note: Small signal model applicable to analog applications is NOT APPLICABLE to digital applications. 38
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