EE105 - Fall 2006 Microelectronic Devices and Circuits

Transcription

1 EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor

2 Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM 1 next week Th will cover everything up to and including MOSCAP Otherwise very normal week 2

3 Overview Last lecture MOS Capacitor This lecture MOS Transistor 3

4 MOS-CAP : Fields and Charge at Equilibrium + V ox + V B X d 0 Body (p-type substrate) E ox At equilibrium there is an electric field from the gate to the body. The charges on the gate are positive. The negative charges in the body come from a depletion region Built-in Voltage: Approx 970 mv 4

5 Good Place to Sleep: Flat Band V FB < 0 + Q ( V = V ) = 0 G GB FB Body (p-type substrate) If we apply a bias, we can compensate for this built-in potential V = ( φ φ ) FB In this case the charge on the gate goes to zero and the depletion region disappears In solid-state physics lingo, the energy bands are flat under this condition n + p 5

6 Accumulation Q = C ( V V ) G ox GB FB V GB < V FB Q B = Q G Body (p-type substrate) If we further decrease the potential beyond the flatband condition, we essentially have a parallel plate capacitor Plenty of holes and electrons are available to charge up the plates Negative bias attracts holes under gate 6

7 Depletion V GB > V FB Body (p-type substrate) Q ( V ) = Q G GB B Q = qn X ( V ) B a d GB Similar to equilibrium, the potential in the gate is higher than the body Body charge is made up of the depletion region ions Potential drop across the body and depletion region 7

8 Inversion V GB = V T φ s Body (p-type substrate) As we further increase the gate voltage, eventually the surface potential increases to a point where the electron density at the surface equals the background ion density qφs kt s i a n = ne = N φs = φp At this point, the depletion region stops growing and the extra charge is provided by the inversion charge at surface 8

9 Threshold Voltage The threshold voltage is defined as the gate-body voltage that causes the surface to change from p-type to n-type For this condition, the surface potential has to equal the negative of the p-type potential We ll derive that this voltage is equal to: 1 VTn = VFB 2φ p + 2 qε sna( 2 φp) C ox 9

10 Q-V Curve for MOS Capacitor Q G depletion inversion Q B,max Q ( V ) N GB accumulation V FB V ( ) GB V In accumulation, the charge is simply proportional to the applies gate-body bias In inversion, the same is true In depletion, the charge grows slower since the voltage is applied over a depletion region V Tn 10

11 MOS CV Curve Q G Cox C Cox Q ( V ) N GB Q B,max V FB V Tn V ( ) GB V V FB V Tn V GB Small-signal capacitance is slope of Q-V curve Capacitance is linear in accumulation and inversion Capacitance in depletion region is smallest Capacitance is non-linear in depletion 11

12 C-V Curve Equivalent Circuits Cox C ox C dep Cox ε s CdepCox C Cdep = ox Cox Ctot = = = xdep Cdep + C Cdep ε s t ox ox C ε ox x ox dep In accumulation mode the capacitance is just due to the voltage drop across t ox In inversion the incremental charge comes from the inversion layer (depletion region stops growing). In depletion region, the voltage drop is across the oxide and the depletion region 12

13 The MOSFET Transistor NMOS PMOS The symbols with the arrows are typically used in analog applications The body contact is often not shown The source/drain can switch depending on how the device is biased (the device has inherent symmetry) 13

14 Observed Behavior: I D -V GS I DS I DS V DS V GS Current zero for negative gate voltage Current in transistor is very low until the gate voltage crosses the threshold voltage of device (same threshold voltage as MOS capacitor) Current increases rapidly at first and then it finally reaches a point where it simply increases linearly V T V GS 14

15 Observed Behavior: I D -V DS IDS / k VGS = 4V non-linear resistor region constant current I DS V DS resistor region VGS = 3V V GS VGS = 2V For low values of drain voltage, the device is like a resistor As the voltage is increases, the resistance behaves non-linearly and the rate of increase of current slows Eventually the current stops growing and remains essentially constant (current source) V DS 15

16 MOSFET Cross Section gate body source drain diffusion regions p+ n+ L n+ p-type substrate Add two junctions around MOS capacitor The regions forms PN junctions with substrate MOSFET is a four terminal device The body is usually grounded (or at a DC potential) For ICs, the body contact is at surface 16

17 MOSFET Layout B S G D contact B S G D poly gate p+ n+ n+ L x j W p-type substrate L Planar process: complete structure can be specified by a 2D layout Design engineer can control the transistor width W and L Process engineer controls t ox, N a, x j, etc. 17

18 PMOS & NMOS B S G D B S G D p+ n+ n+ L x j n+ p+ p+ L x j p-type substrate n-type substrate PMOS A MOSFET by any other name is still a MOSFET: NMOS, PMOS, nmos, pmos NFET, PFET IGFET Other flavors: JFET, MESFET CMOS technology: The ability to fabricated NMOS and PMOS devices simultaneously 18

19 CMOS B S G D B S G D p+ n+ n+ L x j n+ p+ p+ L x j p-type substrate n-type substrate PMOS p-type substrate Complementary MOS: Both P and N type devices Create a n-type body in a p-type substrate through compensation. This new region is called a well. To isolate the PMOS from the NMOS, the well must be reverse biased (pn junction) 19

20 Linear Region Current V GS p+ NMOS > V Tn S n+ n+ p-type G Inversion layer channel 100mV If the gate is biased above threshold, the surface is inverted This inverted region forms a channel that connects the drain and gate If a drain voltage is applied positive, electrons will flow from source to drain D VDS x y 20

21 MOSFET Linear Region The current in this channel is given by I = Wv Q DS y N The charge proportional to the voltage applied across the oxide over threshold Q = C ( V V ) N ox GS Tn I = Wv C ( V V ) DS y ox GS Tn If the channel is uniform density, only drift current flows v V y = μne DS y Ey = W I = DS ncox( VGS VTn) VDS VGS > VTn L μ V 100mV DS L 21

22 MOSFET: Variable Resistor Notice that in the linear region, the current is proportional to the voltage I = W C ( V V ) V L μ DS n ox GS Tn DS Can define a voltage-dependent resistor R eq VDS 1 L L = = = R ( VGS ) I μ C ( V V ) W W DS n ox GS Tn This is a nice variable resistor, electronically tunable! 22

23 Finding I D = f (V GS, V DS ) Approximate inversion charge Q N (y): drain is higher than the source less charge at drain end of channel 23

24 Inversion Charge at Source/Drain Q Q ( y = 0) + Q ( y = L) /2 ( ) N N N Q N ( y Tn = 0) = Cox ( VGS V ) Q N ( y = L) = C V V ) ox ( GD Tn V GD = V GS V DS 24

25 Average Inversion Charge Source End Drain End Cox( VGS VT) + Cox( VGD VT) QN ( y) 2 Cox ( VGS VT ) + Cox ( VGS VDS VT ) QN ( y) 2 Cox(2VGS 2 VT ) CoxVSD VDS QN( y) = Cox( VGS VT ) 2 2 Charge at drain end is lower since field is lower Simple approximation: In reality we should integrate the total charge minus the bulk depletion charge across the channel 25

26 Drift Velocity and Drain Current Long-channel assumption: use mobility to find v Substituting: μnvds vy ( ) = μney ( ) μn( ΔV/ Δ y) = L VDS VDS ID = WvQN Wμ Cox( VGS VT ) L 2 W VDS I C ( V V ) V L μ 2 D ox GS T DS Inverted Parabolas 26

27 Square-Law Characteristics TRIODE REGION Boundary: what is I D,SAT? SATURATION REGION 27

28 The Saturation Region When V DS > V GS V Tn, there isn t any inversion charge at the drain according to our simplistic model Why do curves flatten out? 28

29 Square-Law Current in Saturation Current stays at maximum (where V DS = V GS V Tn = V DS,SAT ) W VDS I = C ( V V ) V L μ 2 D ox GS T DS W VGS VT I DS, sat Cox( VGS VT )( VGS VT ) L μ = 2 W μcox 2 IDS, sat = ( VGS VT ) L 2 Measurement: I D increases slightly with increasing V DS model with linear fudge factor W μc I V V V L 2 ox 2 DS, sat= ( GS T)(1 +λ DS) 29

30 Pinching the MOS Transistors V GS > V Tn S G D V DS Depletion Region p+ n+ n+ VGS VTn p-type NMOS Pinch-Off Point When V DS > V DS,sat, the channel is pinched off at drain end (hence the name pinch-off region ) Drain mobile charge goes to zero (region is depleted), the remaining electric field is dropped across this high-field depletion region As the drain voltage is increases further, the pinch off point moves back towards source Channel Length Modulation: The effective channel length is thus reduced higher I DS 30

31 Short-Channel MOSFET Model Channel (inversion) charge: neglect reduction at drain Velocity saturation defines V DS,SAT =E sat L = constant Drain current: -v sat / μ n I = WvQ = W ( v )[ C ( V V D, SAT N sat ox GS Tn E sat = 10 4 V/cm, L = 0.12 μm V DS,SAT = 0.12 V! )], I = v WC ( V V )(1 + λ V D, SAT sat ox GS Tn n DS ) 31

32 Linear I-V Characteristics: short-channel MOSFET 32

33 I D versus V DS 6 x Resistive VGS= 2.5 V Saturation VGS= 2.0 V 2.5 x VGS= 2.5 V VGS= 2.0 V I D (A) 3 2 V DS = V GS -V T VGS= 1.5 V I D (A) 1 VGS= 1.5 V 1 VGS= 1.0 V 0.5 VGS= 1.0 V V DS (V) Long Channel V DS (V) Short Channel 33