The Devices. Jan M. Rabaey

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1 The Devices Jan M. Rabaey

2 Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models for SPICE simulation Analysis of secondary and deep-sub-micron effects Future trends

3 The Diode B A Al SiO2 p n Cross-section of pn-junction in an IC process A Al A p n B B One-dimensional representation Digital Integrated Circuits diode symbol Devices

4 Depletion Region hole diffusion electron diffusion p n (a) Current flow. hole drift electron drift Charge Density - ρ + x Distance (b) Charge density. Electrical Field ξ x (c) Electric field. Potential V ψ 0 -W 1 W 2 x (d) Electrostatic potential.

5 Diode Current

6 Forward Bias p n (W 2 ) p n0 L p n p0 p-region -W 1 0 W 2 n-region x diffusion

7 Reverse Bias p n0 n p0 p-region -W 1 0 W 2 n-region x diffusion

8 Diode Types p n0 p n (x) x Short-base Diode (standard in semiconductor devices) W n p n (x) Long-base Diode p n0 W n x

9 Models for Manual Analysis V D + I D = I S (e V D/φ T 1) V D + + I D V Don (a) Ideal diode model (b) First-order diode model

10 Junction Capacitance

11 Diffusion Capacitance

12 Diode Switching Time R src V D V 1 V src I D V 2 t = 0 t = T Excess charge Space charge V D ON OFF ON Time

13 Secondary Effects 0.1 I D (A) V D (V) Avalanche Breakdown

14 Diode Model R S + V D - I D C D

15 SPICE Parameters

16 The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor

17 Cross-Section of CMOS Technology

18 MOS transistors Types and Symbols D D G G S NMOS Enhancement D NMOS S Depletion D G G B PMOS S Enhancement S NMOS with Bulk Contact

19 Threshold Voltage: Concept S - V GS + G D n+ n+ n-channel p-substrate Depletion Region B

20 The Threshold Voltage

21 Current-Voltage Relations S V GS G V DS D I D n + V(x) + n + L x p-substrate B MOS transistor and its bias conditions

22 Current-Voltage Relations

23 Transistor in Saturation V GS G V DS > V GS - V T S D n+ - V GS - V T + n+

24 I-V Relation V DS = V GS -V T V GS = 5V I D (ma) 2 1 Triode Saturation V GS = 4V V GS = 3V Square Dependence I D Subthreshold Current V GS = 2V V GS = 1V V DS (V) (a) I D as a function of V DS 0.0 V T V GS (V) (b) I D as a function of V GS (for V DS = 5V). NMOS Enhancement Transistor: W = 100 µm, L = 20 µm

25 A model for manual analysis

26 Dynamic Behavior of MOS Transistor G C GS C GD S D C SB C GB C DB B

27 The Gate Capacitance

28 Average Gate Capacitance Different distributions of gate capacitance for varying operating conditions Most important regions in digital design: saturation and cut-off

29 Diffusion Capacitance

30 Junction Capacitance

31 Linearizing the Junction Capacitance Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest

32 The Sub-Micron MOS Transistor Threshold Variations Parasitic Resistances Velocity Sauturation and Mobility Degradation Subthreshold Conduction Latchup

33 Threshold Variations V T Long-channel threshold Low V DS threshold L Threshold as a function of the length (for low V DS ) Drain-induced barrier lowering (for low L)

34 Parasitic Resistances G Polysilicon gate L D Drain contact V GS,eff S D W R S R D Drain

35 Velocity Saturation (1) υn (cm/sec) υ sat = 10 7 constant velocity Constant mobility (slope = µ) µn (cm 2 /Vs) µ n0 E sat = 1.5 E (V/µm) 0 E t (V/µm) 100 (a) Velocity saturation (b) Mobility degradation

36 Velocity Saturation (2) V GS = 5 I D (ma) V GS = 4 V GS = 3 V GS = 2 Linea r Dependence I D (ma) V GS = V DS (V) (a) I D as a function of V DS V GS (V) (b) I D as a function of V GS (for V DS = 5 V). Linear Dependence on V GS

37 Sub-Threshold Conduction Linear region ln(i D ) (A) Subthreshold exponential region V T V GS (V)

38 Latchup V DD V DD p + n + n + p + p + n + R nwell p-source n-well R nwell R psubs p-substrate n-source R psubs (a) Origin of latchup (b) Equivalent circuit

39 SPICE MODELS Level 1: Long Channel Equations - Very Simple Level 2: Physical Model - Includes Velocity Saturation and Threshold Variations Level 3: Semi-Emperical - Based on curve fitting to measured devices Level 4 (BSIM): Emperical - Simple and Popular

40 MAIN MOS SPICE PARAMETERS

41 SPICE Parameters for Parasitics

42 SPICE Transistors Parameters

43 Fitting level-1 model for manual analysis I D Short-channel I-V curve Region of matching V GS = 5 V Long-channel approximation V DS = 5 V V DS Select k and λ such that best matching is V gs = V ds = V DD

44 Technology Evolution

45 Bipolar Transistor E B C p + isolation n + p + p n-epitaxy n + p + n + buried layer p-substrate (a) Cross-sectional view. B E n + p n C (b) Idealized transistor structure.

46 Schematic Symbols and Sign Conventions I B + B + V BC V BE C E + I C V CE I E I B + B + V BC V BE C E + I C V CE I E (a) npn (b) pnp

47 Operations Modes

48 Forward Active Operation Carrier Concentration Depletion Regions E B C n b (0) p c0 p e0 n b0 x 0 W W B

49 Current Components E B C I E 1 I C 2 3 x I B electrons holes

50 Reverse Active Carrier Concentration E B C n b (W) p e0 n b (0) n b0 0 W p c0 x W B

51 Saturation Mode Carrier Concentration n b (0) E B C Q A n b (W) p e0 Q S n b0 0 W p c0 x W B

52 Cutoff Carrier Concentration E B C p e0 n b (0) n b0 n b (W) 0 W p c0 x W B

53 Bipolar Transistor Operation IC (ma) I B =25 µa I B =50 µa I B =75 µa I B =100 µa Reverse Operation IC(mA) Forward Operation Active I B =100 µa I B =75 µa I B =50 µa I B =25 µa V CE (V) Saturation V CE (V)

54 A Model for Manual Analysis B I B + V BE βfi B C B V BE(on) I B + βfi B C I B = I S (e V BE/φT 1) E E (a) Forward-active (b) Forward-active (simplified) B I B V BE(sat) + C + V CE(sat) E (c) Forward-saturation I C < β F I B

55 Capacitive Model for Bipolar Transistor C B Q R C bc C cs collector-substrate junction capacitance Q F C be S base charge E base-emitter base-collector junction capacitances

56 Junction Capacitances

57 Base Charge - Diffusion Capacitance

58 Bipolar Transistors - Secondary Effects Early Voltage Parasitic Resistances Beta Variations

59 Early Voltage I C Saturation Forward Active VBE3 V BE2 V BE1 V A V CE

60 Parasitic Resistance E B C p + r E n + p + p n + isolation n-epitaxy r B r C1 p + r C3 n + buried layer r C2 p-substrate

61 Beta Variations ln (I) I KF I C High Level Injection β F Recombination I B V BE (linear)

62 SPICE models for Bipolar

63 Main Bipolar Transistor SPICE Models

64 Spice Parameters for Parasitics

65 SPICE Transistor Parameters

66 Process Variations Devices parameters vary between runs and even on the same die! Variations in the process parameters, such as impurity concentration densities, oxide thicknesses, and diffusion depths. These are caused by nonuniform conditions during the deposition and/or the diffusion of the impurities. This introduces variations in the sheet resistances and transistor parameters such as the threshold voltage. Variations in the dimensions of the devices, mainly resulting from the limited resolution of the photolithographic process. This causes (W/L) variations in MOS transistors and mismatches in the emitter areas of bipolar devices.

67 Impact of Device Variations Delay (nsec) Delay (nsec) L eff (in mm) V Tp (V) Delay of Adder circuit as a function of variations in L and V T

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