Section 12: Intro to Devices

Transcription

1 Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals

2 Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon crystal in a two-dimensional representation. Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si When an electron breaks loose and becomes a conduction electron, a hole is also created.

3 Semiconductors, Insulators, and Conductors E c E g1.1 ev E c Ev E g 9 ev E v Top of conduction band empty filled E c Si, Semiconductor SiO 2, insulator Conductor Totally filled bands and totally empty bands do not allow current flow. (Just as there is no motion of liquid in a totally filled or totally empty bottle.) Metal conduction band is half-filled. Semiconductors have lower E G s than insulators and can be doped

4 electron - Bottom of conduction band Intrinsic Carriers Energy gap 1.12 ev hole + Top of valence band n (electron conc) p (hole conc) n i

5 Dopants in Silicon Si Si Si Si Si Si Si As Si Si B Si Si Si Si Si Si Si As, a Group V element, introduces conduction electrons and creates N-type silicon, and is called a donor. B, a Group III element, introduces holes and creates P-type silicon, and is called an acceptor.

6 Types of charges in semiconductors Hole Electron Mobile Charge Carriers they contribute to current flow with electric field is applied. Ionized Donor Ionized Acceptor Immobile Charges they DO NOT contribute to current flow with electric field is applied. However, they affect the local electric field

7 Fermi Function The Probability of an Energy State Being Occupied by an Electron f ( E) ( E E ) / kt E 1+ e 1 f E f is called the Fermi energy or the Fermi level. Boltzmann approximation: f ( E E ) kt f ( E) e E E f >> kt E f E f E f + 3kT + 2kT E f + kt ( E E f ) kt f ( E) e f ( E ) kt E ( E) 1 e f E E f << kt E f E f kt E f 2kT E f 3kT ( E f E ) kt f ( E) 1 e f(e)

8 Electron and Hole Concentrations n N c e ( E E F C ) / kt N c is called the effective density of states. p N v e ( E E V F ) / kt N v is called the effective density of states of the valence band. Remember: the closer E f moves up to E c, the larger n is; the closer E f moves down to E v, the larger p is. For Si, N c cm -3 and N v cm -3.

9 Shifting the Fermi Level

10 Quantitative Relationships n: electron concentration (cm -3 ) p : hole concentration (cm -3 ) N D : donor concentration (cm -3 ) N A : acceptor concentration (cm -3 ) Assume completely ionized to form N D + and N A - 1) Charge neutrality condition: N D + p N A + n 2) Law of Mass Action : n p n i 2 What happens when one doping species dominates?

11 General Effects of Doping on n and p I. N N >> n (i.e., N-type) d a i n N d N a p n 2 i n If N d >> N a, n Nd and p 2 n i N d II. N N >> a d n i (i.e., P-type) p n N a N n 2 i p d If N >>, a N d p Na and n 2 n i N a

12 When an electric field is applied to a semiconductor, mobile carriers will be accelerated by the electrostatic force. This force superimposes on the random thermal motion of carriers: E.g. Electrons drift in the direction opposite to the E-field Current flows E 0 Average drift velocity v μ E 5 1 electron Carrier Drift Carrier mobility 2 E 1 electron

13 Carrier Mobility Mobile carriers are always in random thermal motion. If no electric field is applied, the average current in any direction is zero. Mobility is reduced by 1) collisions with the vibrating atoms phonon scattering 2) deflection by ionized impurity atoms Coulombic scattering - B- - As+ - - Si

14 Total Mobility 1600 Mobility (cm 2 V -1 s -1 ) Electrons Holes 1 τ 1 μ τ 1 + phonon 1 μ phonon + τ 1 impurity 1 μ impurity E14 1E15 1E16 1E17 1E18 1E19 1E20 Total Impurity N Concenration (atoms cm -3 a + N d (cm -3 ) )

15 Conductivity and Resistivity J p,drift qpv qpμ p J n,drift qnv qnμ n J drift J n,drift + J p,drift σ (qnμ n +qpμ p ) conductivity of a semiconductor is σ qnμ n + qpμ p Resistivity, ρ 1/ σ

16 Relationship between Resistivity and Dopant Density DOPANT DENSITY cm -3 N-type P-type RESISTIVITY (Ω cm) ρ 1/σ

17 W I + L V Material with resistivity ρ _ R s Sheet Resistance L t R ρ Wt R s is the resistance when W L ρ t R s value for a given conductive layer (e.g. doped Si, metals) in IC or MEMS technology is used for design and layout of resistors for estimating values of parasitic resistance in a device or circuit R s L W (in ohms/square) if ρ is independent of depth x

18 Diffusion Current Particles diffuse from higher concentration to lower concentration locations.

19 J n, diffusion qd Diffusion Current n dn dx J p, diffusion qd p dp dx D is called the diffusion constant. Signs explained: n p x x

20 Generation/Recombination Processes Recombination continues until excess carriers 0. Time constant of decay is called recombination lifetime

21 Continuity Equations Combining all the carrier actions: n n n n t t + drift t + + diff t thermalr G Now, by the definition of current, we know: n t others n n J J Nx Ny J Nz t + 1 drift t 1 diff q ( x + y + z ) q J Since a change in carrier concentration must occur from a net current Therefore, we can compactly write the continuity equation as: N n t p t 1 q J 1 q N J + P n t thermalr G + + p t thermalr G n t other p t other +

22 PN Junctions Donors N-type P-type I V + I V N P Reverse bias Forward bias diode symbol A PN junction is present in almost every semiconductor device.

23 Energy Band Diagram and Depletion Layer N-region P-region (a) E f E c (b) E c E f E v (c) E v E c E f E v n 0 and p 0 in the depletion layer (d) Neutral N-region Depletion layer Neutral P-region E c E f E v φ bi kt q ln N d 2 i n N a

24 Qualitative Electrostatics Band diagram Built in-potential From ε-dv/dx

25 Depletion-Layer Model Neutral Region N Depletion Layer Neutral Region P On the P-side of the depletion layer, ρ qn a x 0 n x p ρ d dx qn a ε s x n qn d qn a x p x qna qna ( x) x + C 1 ( x p x) ε ε s s E On the N-side, ρ qn d x x n 0 p x qnd ( x ) ( x + xn ) ε s

26 Effect of Bias on Electrostatics

27 Current Flow - Qualitative

28 PN Diode IV Characteristics I qv kt I0( e 1) I 0 Aqn 2 i L D p p N d + Dn L N n a I I + r 0 A qnw i τ dep dep

29 MOS Capacitors MOS: Metal-Oxide-Semiconductor V g metal gate V g gate SiO 2 N + SiO 2 N + Si body P-body MOS capacitor MOS transistor

30 MOS Band Diagram

31 Flat-band Condition and Flat-band Voltage χ SiO ev E c E 0 qψ M 3.1 ev 3.1 ev χ Si qψ s χ Si + (E c E f ) 4.05eV E c, E f E c V fb E v N + -poly-si 9 ev P-body E f E v E 0 : Vacuum level E 0 E f : Work function E 0 E c : Electron affinity Si/SiO 2 energy barrier E v 4.8 ev Vfb ψ ψ M s SiO 2

32 Biasing Conditions

33 Biasing Conditions (2)

34 E c, E f E v qv g Depletion and the Depletion Width qv ox qφ s W de p depletion region M O S E c E fev The charge within the depletion region is: ρ qn A Poisson s equation reduces to: dε ρ qn A K0 x W dx ε ε Si Integrating twice gives: φ S qn 2ε A Si Si W 2 (b) Or: W 2ε Si qn φ A S

35 Surface Depletion V V g > V fb gate depletion layer charge, Q dep P-Si body SiO 2 E c, E f E v qv g qv ox qφ s W de p depletion region E c E fev V ox Q C V g s ox V Q (a) C fb + φ + V s dep ox ox qn a C ox V W fb dep + φ + s qn a C qn M O S 2ε φ ox a s C 2ε φ ox s s s (b)

36 Threshold Condition and Threshold Voltage threshold of inversion E c φ st threshold : n s N a A C qφ Β E i (E c E f ) surface (E f E v ) bulk qv g qv t D B E f E v AB, and C D E c, E f φ st 2φ B kt 2 ln q N n i a E v M O S qφ B E 2 g ( E f E v ) bulk kt q ln N n i v kt q ln N N v a kt q ln N n i a

37 V V + V + V g fb s Threshold Voltage ox V t V fb + 2 φ + B qn a 2ε 2φ C ox s B Summarizing both polarities: V φ ± 2 t st φ B V fb +φ ± st qn sub C 2ε φ ox s st + : N-type device, : P-type device

38 Strong Inversion Beyond Threshold Past V T, the depletion width no longer grows W dep W dmax 2ε sφst qn a E c E f E v All additional voltage results in inversion layer charge E c, E f E v qv g Q inv C ox ( Vg Vt ) M O S (b)

39 Review : Basic MOS Capacitor Theory φ s 2φ B V fb V t V g accumulation depletion inversion W dep W dmax (φ s ) 1/2 W dmax (2ε s 2φ Β /qν a ) 1/2 V fb V t V g accumulation depletion inversion

40 Review : Basic MOS Capacitor Theory Q dep qn a W dep (a) V fb accumulation depletion inversion 0 qn a W dep V t qn a W dmax V g total substrate charge, Q s Q Q + Q + Q s acc dep inv Q inv Q s (b) V fb accumulation depletion inversion V t V g accumulation regime depletion regime inversion regime slope C ox V fb 0 V t V g Q acc Q inv (c) slope C ox slope C ox V fb V t V g accumulation depletion inversion

41 Quasi-Static CV Characteristics C ox C V fb V t accumulation depletion inversion V g 1 C 1 C C ox C dep 1 C 2 ox 2( Vg V + qn ε a s fb )

42 Qualitative MOSFET Operation Depletion Layer

43 Channel Length Modulation

44 MOSFET I-V Characteristics A 1 st attempt The Square Law Theory Current in the channel should be mainly drift-driven dφ J N qμnnε qμnn dy The current is: I D qz J Z μ Q dφ μn dy n N Ny dx dz x c dφ dy ( y) 0 n( x, y) dx

45 MOSFET I-V Characteristics A 1 st attempt But, current is constant through the channel: We know the inversion layer charge: Accounting for the non-uniformity: D D V N n D V N n D L D d Q L Z I d Q Z L I dy I φ μ φ μ ) ( T G ox inv V V C Q ) ( ) ( φ T G ox inv V V C y Q ( ) T G Dsat D D D T G ox n D V V V V V V V V C L Z I K μ

46 MOSFET I-V Characteristics A 1 st attempt Past pinch-off, the drain current is constant I D, V D So: > V I D, V V Dsat Dsat Dsat Now, in the pinched-off region: I D Q V I D inv Dsat ( y) V Z L G D μ C n ox V Z μnc 2L T ox G C ( V V V ) 0 ox I 2 V ( V ) Dsat G VT VDsat T [ V V ] 2 G T Dsat 2

47 N-channel MOSFET Layout (Top View) 4 lithography steps are required: 1. active area 2. gate electrode 3. contacts 4. metal interconnects

48 Simple NMOS Process Flow 1) Thermal oxidation (~10 nm pad oxide ) 2) Silicon-nitride (Si 3 N 4 ) deposition by CVD (~40nm) 3) Active-area definition (lithography & etch) 4) Boron ion implantation ( channel stop implant)

49 5) Thermal oxidation to grow oxide in field regions 6) Si 3 N 4 & pad oxide removal 7) Thermal oxidation ( gate oxide ) 8) Poly-Si deposition by CVD 9) Poly-Si gate-electrode patterning (litho. & etch) Simple NMOS Process Flow 10) P or As ion implantation to form n+ source and drain regions Top view of masks

50 Simple NMOS Process Flow 11) SiO 2 CVD Top view of masks 12) Contact definition (litho. & etch) 13) Al deposition by sputtering 14) Al patterning by litho. & etch to form interconnects