Lecture 7 PN Junction and MOS Electrostatics(IV) Metal Oxide Semiconductor Structure (contd.)

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1 Lecture 7 PN Junction and MOS Electrostatics(IV) Metal Oxide Semiconductor Structure (contd.) Outline 1. Overview of MOS electrostatics under bias 2. Depletion regime 3. Flatband 4. Accumulation regime 5. Threshold 6. Inversion regime Reading Assignment: Howe and Sodini, Chapter 3, Sections Spring 2009 Lecture 7 1

2 1. Overview of MOS electrostatics under bias Application of bias: Built-in potential across MOS structure increases from φ B to φ B + V GB Oxide forbids current flow J=0 everywhere in semiconductor Need drift = diffusion in SCR Must maintain boundary condition at Si/SiO 2 interface E ox / E s 3 How can this be accommodated simultaneously? quasi equilibrium situation with potential build-up across MOS equal to φ B + V GB Spring 2009 Lecture 7 2

3 Important consequence of quasi equilibrium: Boltzmann relations apply in semiconductor [they were derived starting from J n = J p =0] and qφ(x) kt n(x) = n i e qφ(x) kt p(x) = n i e 2 np = n i at every x Spring 2009 Lecture 7 3

4 2. Depletion regime For V GB >0, metal attracts electrons and repels holes Depletion region widens For V GB <0, metal repels electrons and attracts holes Depletion region shrinks Spring 2009 Lecture 7 4

5 In depletion regime, all results obtained for thermal equilibrium apply if φ B φ B +V GB. For example: Depletion region thickness: ε x s d (V GB ) = C ox 2C 2 (φ B + V GB ) ox 1+ 1 ε s qn a Potential drop across semiconductor SCR: Surface potential qn x 2 V B (V GB ) = a d 2ε s φ(0) = φ p + V B (V GB ) Potential drop across oxide: V ox (V GB ) = qn a x d t ox ε ox Spring 2009 Lecture 7 5

6 3. Flatband At a certain negative V GB, depletion region is wiped out Flatband Flatband Voltage: V GB = V FB = φ B = (φ N + φ p ) Spring 2009 Lecture 7 6

7 4. Accumulation regime If V GB < V FB accumulation of holes at Si/SiO 2 interface Spring 2009 Lecture 7 7

8 5. Threshold Back to V GB >0. For sufficiently large V GB >0, electrostatics change when n(0)=n a threshold. Beyond threshold, we cannot neglect contributions of electrons towards electrostatics. Let s compute the gate voltage (threshold voltage) that leads to n(0)=n. Key assumption: use electrostatics of depletion (neglect electron concentration at threshold) Spring 2009 Lecture 7 8

9 Computation of threshold voltage. Three step process: First, compute potential drop in semiconductor at threshold. Start from: qφ(0) kt n(0) = n i e Solve for φ(0) at V GB = V T : kt n (0) kt N φ(0 ) = ln = ln a V = φ GB =V T q n p i q n V GB = V T i Hence: V B (V T ) = 2φ p Spring 2009 Lecture 7 9

10 Computation of threshold voltage (contd.) Second, compute potential drop in oxide at threshold. Obtain x d (V T ) using relationship between V B and x d in depletion: 2 VT Solve for x d at V GB = V T : Then: V B (V GB = V T ) = qn ax d 2ε s x d (V T ) = x d max = ( ) V ox (V T ) = E ox (V T )t ox = qn a x d (V T ) ε ox t ox = = 2φ p 2ε s ( 2φ p ) qn a 1 C ox 2ε s qn a ( 2φ p ) Spring 2009 Lecture 7 10

11 Computation of threshold voltage. (contd..) Finally, sum potential drops across structure. V T + φ B = V B (V T ) + V ox (V T ) = 2φ P + Solve for V T : 1 C ox 2ε s qn a ( 2φ p ) V GB = V T = V FB 2φ P + 1 C ox 2ε s qn a ( 2φ p ) Key dependencies: If N a V T. The higher the doping, the more voltage required to produce n(0) = N a If C ox (t ox ) V T. The thinner the oxide, the less voltage dropped across the oxide Spring 2009 Lecture 7 11

12 6. Inversion What happens for V GB > V T? More electrons at Si/SiO 2 interface than acceptors inversion. Electron concentration at Si/SiO 2 interface modulated by V GB V GB n(0) Q N : Field effect control of mobile charge density! [essence of MOSFET] Want to compute Q N vs. V GB [charge control relation] Make sheet charge approximation: electron layer at Si/SiO 2 is much thinner than any other dimension in problem (t ox, x d ) Spring 2009 Lecture 7 12

13 Charge Control Relation To derive the charge control relation, let s look at the overall electrostatics: Spring 2009 Lecture 7 13

14 Charge Control Relation (contd.) Key realization: n(0) e qφ(0) kt qn a x d φ(0) Hence, as V GB and φ(0), n(0) will change a lot, but Q d will change very little. Several consequences: x d does not increase much beyond threshold: 2ε s ( 2φ p ) x d (inv.) x d (V T ) = = x qn d,max a V B does not increase much beyond V B (V T ) =-2φ P (a thin sheet of electrons does not contribute much to V B.): V B (inv.) V B (V T ) = 2φ P Spring 2009 Lecture 7 14

15 Charge Control Relation (contd..) All extra voltage beyond V T used to increase inversion charge Q n. Think of it as capacitor: Top plate: metal gate Bottom plate: inversion layer Q = CV Q N = C ox (V GB V T ) for V GB > V T Coul/cm 2 Existence of Q N and control over Q N by V GB key to MOS electronics Spring 2009 Lecture 7 15

16 What did we learn today? Summary of Key Concepts In inversion: Q N = C ox (V GB V T ) for V GB > V T Spring 2009 Lecture 7 16

17 MIT OpenCourseWare Microelectronic Devices and Circuits Spring 2009 For information about citing these materials or our Terms of Use, visit:

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