Metal-oxide-semiconductor field effect transistors (2 lectures)
|
|
- Kerry Brown
- 5 years ago
- Views:
Transcription
1 Metal-ide-semiconductor field effect transistors ( lectures) MOS physics (brief in book) Current-voltage characteristics - pinch-off / channel length modulation - weak inversion - velocity saturation - metrics extraction Capacitances Small-signal model Reading: (4-5 th edition) 1.5 (not 1.5.4) 1.6 (not 1.6.6, 1.6.8) 1.7 (not 1.7., 1.7.3): not in detail 1
2 n-type MOSFET layout Gate ( ) Source (grounded) SiO rain ( S ) n ++ p-type Si n ++ Body ( SB )
3 Energy bands 1 flat band semiconductor y L Metal E C E i x E F E ide ρ Gate ide has large band gap no current. E F constant in semiconductor x 3
4 Energy bands - depletion L E C Φ = surface potential + E i + ρ n p <<p p <<N A p p =N A E F E Charge per area: N q -N A x Q s 0 q N A Q C A 4
5 Energy bands 3 intrinsic surface L Φ E C + E i E F + ρ n p =p p =n i << N A -N A E x Q s 0 q N N A Q C q A 5
6 Energy bands 4 weak inversion L Φ E C E i + E F + ρ n n p p -N A p p N A E x Q s 0 q N N A Q C q A 6
7 Energy bands 5 onset of strong inversion ( = t ) L Φ E C + S E i Φ f Φ=* Φ f E F + ρ Φ f n n p p N -N A p A p E Many free electrons at surface x Q s 0 q N N A Q C q A 7
8 Strong inversion > t Φ E C Φ Φ f E i E F E Φ f np N A np N A ρ ρ Conducting channel at surface! -N A x -N A x 8
9 Q (surface charge) Charge vs surface potential depletion / weak inversion only acceptors contribute -> slow increase in Q (increase ) ρ Q const * -N A strong inversion mainly electrons contribute -> exponential increase in Q ρ Q const * exp( ) -N A Φ (surface potential) Threshold for channel formation 9
10 Surface potential variation with gate voltage Φ () Φ = Q C falls over both ide and semiconductor Φ=*Φ f Φ falls only over ide (parallel-plate capacitor) t () 10
11 C gs (F m - ) MOS physics: capacitance max(c gs )=C ρ depletion inversion ρ C dq d -N A -N A SiO Low frequency (10 Hz) p-type semiconductor Minority carriers don t have time to be generated high frequency (>1 MHz) min(c gs ) related to can get N A () 11
12 min exercise metal work function variation Metal and semiconductor work functions usually not the same (as we assumed before). 1. Sketch band diagram for metal with higher work function in MOS.. How does the higher work function impact t (threshold voltage needed for strong inversion)? semiconductor + =??? Metal ΔΦ ms 1
13 nversion layers creates channel in MOSFET Gate = Source SiO rain N ++ N ++ S > 0 P-type semiconductor 13
14 Geometry for drain current calculation S =0 Z Oxide Gate S Oxide S Source channel rain Q (y)=c ( -(y)- t ) y channel x L y W S Q (y) = electrons per unit area at position y (y) = voltage at y ε(y) = electric field at y 14
15 () Current and channel shape linear (triode) region 5 rainström (ma) S = - t 0 nc W L < t t S S > t S < - t rainspänning S () () Q ( y) C ( y) t 15
16 () Current and channel shape saturation region (pinch-off) rainström (ma) S = - t, sat nc W L Pinch-off: independent of S t 0 Q S < - t C rainspänning () S () (y) t Q S = - t 0 C t S > - t Q C t (y) Q L 0 Q L 0 16
17 Pinch-off band structure and electron velocity High field region High velocity -> low Q Pinch-off point: Electrons swept into drain by E-field 17
18 Channel length modulation d Q C t (y), sat C W L n t 1 S Slope=1/r 0 - A non-inverted region is formed beyond pinch-off i.e. the channel length is reduced with S - Gives output resistance r d d 0 S Output conductance g d =1/r 0 - λ
19 Example: MOSFET with channel length modulation t = 1.0 C = 3 mf/m µ n = m /s L = 5 µm W = 50 µm λ = Calculate for 1) S =0.5, 1, & 3 if = 0 ) S =0.5, 1, & 3 if =.5 Linear region S t nc W L t S S saturation S t, sat C W L n t 1 S 19
20 min exercise source/drain resistance n modern MOSFETs, resistance in the source/drain can not always be neglected. How does the output characteristics change if a significant source/drain resistance is added? SiO n ++ n p-type Si ++ p-type Si n ++ SiO n ++??? S 0
21 Subthreshold current (weak inversion) (don t read 1.8) - For < t (but high enough for weak inversion): channel charge << inversion charge - rift current is small, mainly diffusion current (as NPN BJT) - Exponentially increasing injection over barrier with. exp n T t 1 exp S T S exponential increase t ρ n ++ SiO p-type Si n ++ = t, Φ=* Φ f < t -N A Forward biased np-junction 1
22 elocity saturation in short-channel MOSFETs (1.7.1) - Short channel length, high S -> high electric field - At critical field ε c (1.5*10 6 ) electron velocity saturates due to optical phonon emission v d µ n 1 / c c c v v d d µ µ n n c v scl lim E C 0 = WC t v scl Without velocity sat. ( ) With velocity sat. ( ) S t
23 etrimental effects Junction breakdown For large S (long channel) the drainsubstrate pn-junction is reversed biased enough to cause avalanche breakdown. Punchthrough For large S (short channel) the drain depletion region can tough the source depletion region. Slower current increase than junction breakdown Hot carriers high electric fields give electrons enough energy to be injected into gate ide. Can give higher gate current and/or shift the threshold voltage. Oxide breakdown For high (6*10 6 /cm) vertical electric fields (from gate) the gate ide may break. 3
24 Summary MOSFET C characteristics Linear (triode) S < t + nc W L T S S Saturation (active, pinch-off) S > t + included channel length modulation, sat C W L n t 1 S elocity saturation lim E C 0 = WC t v scl 4
25 Parameter extraction from output characteristics 5
26 Parameter extraction from transfer characteristics Long channel Short channel (velocity saturation) 6
27 Parameter extraction from transfer characteristics (log) 7
28 1 min excercise MOSCAP vs MOSFET How can a MOSFET operate at GHz when MOSCAP only responds at frequencies < 1 MHz in inversion? >GHz < MHz SiO SiO N ++ N ++ P-type semiconductor P-type semiconductor 8
29 Small-signal model G d (t)= +i d (t) + v gs (t) = gs (t) gs (t) S t S + i d (t) = d (t) gs (t)= +v gs (t) t rainström (ma) () rainspänning () S () 1 st order Taylor expansion - linearization f ( x x) f ( x ) df ( x) dx 0 0 xx d v v gs d d 9 d 0 x S vds S vds S vds S gs g m 1 r 0... v gs
30 Capacitances v i C gs SiO C gd N ++ P-type semiconductor N ++ Linear region Saturation region C gs 1 Cgd WLC (C [F/µm ]) C gs WLC 3 C gd 0 (pinched off channel derived on page 51) 30
31 (simple) Small-signal model - saturation G C G AC g m v gs r 0 C g m v gs r 0 S S - Transconductance controls the current source - Output resistance channel length modulation with increasing S - gate-source capacitance g m µ n C 1 ro S C WLC 3 W L - nput resistance infinite due to gate ide 31
32 Small-signal model more advanced Add more elements: - drain-body / source-body capacitances (C db /C sb ) reversed biased pn-junctions - gate overlap capacitances (C ol ) - gate-body capacitance - outside active device area - body transconductance acting as nd gate - source/drain resistances (not included here) body effects 3
33 Summary - MOSFETs n-type (p-doped substrate) or p-type (n-doped substrate) ncreasing voltage beyond t gives inversion layer (channel) under gate Linear (triode): depends on both and S Saturation (active): depends only on due to pinch-off of channel at drain Channel length modulation: ncreasing S beyond pinch-off shortens channel increasing with S. Small signal model: nfinite input resistance due to gate ide. Output resistance (r 0 ) due to channel length modulation. Gate-source capacitance (C ) dominates Can add more capacitances and resistances to get more accurate (and complicated) model. 33
34 BJTs vs MOSFETs BJT MOSFET Terminals Emitter, base, collector Source, gate, drain, (base) Symmetric no (more doping in emitter) yes Transport mechanism iffusion rift (diffusion below t ) Current formula (active region) C BE CE T S 1 e nc W 1 A, sat L t S Transconductance g m C T g m µ n C W L nput resistance (r 0 ) Finite due to base current nfinite due to insulating gate ide 34
35 Si MOSFET development (for digital logic) 35
36 Modern transistors MOSFET Strain enhance mobility High-k gate dielectric gives higher C without leakage current Tri-gate enables channel length reduction due to better electrostatic control (less short-channel effects) (- semiconductors would give higher mobility) L = 3 nm High electron mobility transistor (HEMT) - semiconductors to get high mobility Move doping away from channel to avoid scattering Heterojunction bipolar transistor (HBT) Combine (-) semiconductors with different E g (HBT). alence band barrier gives less backinjection from base to emitter. ncrease base doping with same gain. 36
37 Modern MOSFET ngaas channel Highly doped regrown contact gives self-aligned gate No pn-junctions, fully depleted channel on =.0 ma/μm g m = 1.9 ms/μm f t = 44 GHz 37
Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes
Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and cross-sectional area 100µm 2
More informationLecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationMOS Transistor I-V Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationSpring Semester 2012 Final Exam
Spring Semester 2012 Final Exam Note: Show your work, underline results, and always show units. Official exam time: 2.0 hours; an extension of at least 1.0 hour will be granted to anyone. Materials parameters
More informationLong Channel MOS Transistors
Long Channel MOS Transistors The theory developed for MOS capacitor (HO #2) can be directly extended to Metal-Oxide-Semiconductor Field-Effect transistors (MOSFET) by considering the following structure:
More informationThe Devices. Jan M. Rabaey
The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models
More informationMOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA
MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing
More informationFundamentals of the Metal Oxide Semiconductor Field-Effect Transistor
Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the
More informationOperation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS
Operation and Modeling of The MOS Transistor Second Edition Yannis Tsividis Columbia University New York Oxford OXFORD UNIVERSITY PRESS CONTENTS Chapter 1 l.l 1.2 1.3 1.4 1.5 1.6 1.7 Chapter 2 2.1 2.2
More informationElectronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices
Electronic Circuits 1 Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Three-terminal device whose voltage-current relationship is controlled by a third voltage
More informationLecture 3: Transistor as an thermonic switch
Lecture 3: Transistor as an thermonic switch 2016-01-21 Lecture 3, High Speed Devices 2016 1 Lecture 3: Transistors as an thermionic switch Reading Guide: 54-57 in Jena Transistor metrics Reservoir equilibrium
More informationThe Devices: MOS Transistors
The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor
More informationChapter 4 Field-Effect Transistors
Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationELEC 3908, Physical Electronics, Lecture 26. MOSFET Small Signal Modelling
ELEC 3908, Physical Electronics, Lecture 26 MOSFET Small Signal Modelling Lecture Outline MOSFET small signal behavior will be considered in the same way as for the diode and BJT Capacitances will be considered
More informationCurrent mechanisms Exam January 27, 2012
Current mechanisms Exam January 27, 2012 There are four mechanisms that typically cause currents to flow: thermionic emission, diffusion, drift, and tunneling. Explain briefly which kind of current mechanisms
More informationLecture 5: CMOS Transistor Theory
Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics
More informationLecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
More informationELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model
ELEC 3908, Physical Electronics, Lecture 23 The MOSFET Square Law Model Lecture Outline As with the diode and bipolar, have looked at basic structure of the MOSFET and now turn to derivation of a current
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated
More informationEE5311- Digital IC Design
EE5311- Digital IC Design Module 1 - The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!
More informationTransistors - a primer
ransistors - a primer What is a transistor? Solid-state triode - three-terminal device, with voltage (or current) at third terminal used to control current between other two terminals. wo types: bipolar
More informationIntroduction and Background
Analog CMOS Integrated Circuit Design Introduction and Background Dr. Jawdat Abu-Taha Department of Electrical and Computer Engineering Islamic University of Gaza jtaha@iugaza.edu.ps 1 Marking Assignments
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationLecture 12: MOSFET Devices
Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationFIELD-EFFECT TRANSISTORS
FIEL-EFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancement-type N-MOS transistor 3 I-V characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation
More informationMOS CAPACITOR AND MOSFET
EE336 Semiconductor Devices 1 MOS CAPACITOR AND MOSFET Dr. Mohammed M. Farag Ideal MOS Capacitor Semiconductor Devices Physics and Technology Chapter 5 EE336 Semiconductor Devices 2 MOS Capacitor Structure
More informationECE 497 JS Lecture - 12 Device Technologies
ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density
More informationMOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
More information6.012 Electronic Devices and Circuits Spring 2005
6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):
More informationClass 05: Device Physics II
Topics: 1. Introduction 2. NFET Model and Cross Section with Parasitics 3. NFET as a Capacitor 4. Capacitance vs. Voltage Curves 5. NFET as a Capacitor - Band Diagrams at V=0 6. NFET as a Capacitor - Accumulation
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. EECS 130 Professor Ali Javey Fall 2006
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 130 Professor Ali Javey Fall 2006 Midterm 2 Name: SID: Closed book. Two sheets of notes are
More informationSemiconductor Physics fall 2012 problems
Semiconductor Physics fall 2012 problems 1. An n-type sample of silicon has a uniform density N D = 10 16 atoms cm -3 of arsenic, and a p-type silicon sample has N A = 10 15 atoms cm -3 of boron. For each
More informationDigital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationChapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 2 CMOS Transistor Theory Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor Jin-Fu Li, EE,
More informationErik Lind
High-Speed Devices, 2011 Erik Lind (Erik.Lind@ftf.lth.se) Course consists of: 30 h Lectures (H322, and Fys B check schedule) 8h Excercises 2x2h+4h Lab Excercises (2 Computer simulations, 4 RF measurment
More informationSECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University
NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula
More informationEE105 - Fall 2006 Microelectronic Devices and Circuits
EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM
More informationMOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor
MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET Calculation of t and Important 2 nd Order Effects SmallSignal Signal MOSFET Model Summary Material from: CMOS LSI Design By Weste
More informationMOSFET. Id-Vd curve. I DS Transfer curve V G. Lec. 8. Vd=1V. Saturation region. V Th
MOSFET Id-Vd curve Saturation region I DS Transfer curve Vd=1V V Th V G 1 0 < V GS < V T V GS > V T V Gs >V T & Small V D > 0 I DS WQ inv WC v WC i V V VDS V V G i T G n T L n I D g V D (g conductance
More informationLecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor
Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics t ti Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE105 Fall 2007
More informationCMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More informationLecture 12: MOS Capacitors, transistors. Context
Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those
More information6.012 Electronic Devices and Circuits
Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless
More informationStudent Number: CARLETON UNIVERSITY SELECTED FINAL EXAMINATION QUESTIONS
Name: CARLETON UNIVERSITY SELECTE FINAL EXAMINATION QUESTIONS URATION: 6 HOURS epartment Name & Course Number: ELEC 3908 Course Instructors: S. P. McGarry Authorized Memoranda: Non-programmable calculators
More informationMOS Capacitors ECE 2204
MOS apacitors EE 2204 Some lasses of Field Effect Transistors Metal-Oxide-Semiconductor Field Effect Transistor MOSFET, which will be the type that we will study in this course. Metal-Semiconductor Field
More informationLecture #27. The Short Channel Effect (SCE)
Lecture #27 ANNOUNCEMENTS Design Project: Your BJT design should meet the performance specifications to within 10% at both 300K and 360K. ( β dc > 45, f T > 18 GHz, V A > 9 V and V punchthrough > 9 V )
More informationLecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor
Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE15 Spring 28 Lecture
More informationEEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring
More informationThe Devices. Devices
The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Cross-Section of CMOS Technology MOS transistors
More informationGEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering
NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 First Exam Closed Book and Notes Fall 2002 September 27, 2002 General Instructions: 1. Write on one side of
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationMOS Capacitor MOSFET Devices. MOSFET s. INEL Solid State Electronics. Manuel Toledo Quiñones. ECE Dept. UPRM.
INEL 6055 - Solid State Electronics ECE Dept. UPRM 20th March 2006 Definitions MOS Capacitor Isolated Metal, SiO 2, Si Threshold Voltage qφ m metal d vacuum level SiO qχ 2 E g /2 qφ F E C E i E F E v qφ
More information! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!
More informationEE105 - Fall 2005 Microelectronic Devices and Circuits
EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 29, 2019 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2019 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationCMOS Devices. PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors
CMOS Devices PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors PN Junctions Diffusion causes depletion region D.R. is insulator and establishes barrier
More informationInstitute of Solid State Physics. Technische Universität Graz. Exam. Feb 2, 10:00-11:00 P2
Technische Universität Graz nstitute of Solid State Physics Exam Feb 2, 10:00-11:00 P2 Exam Four questions, two from the online list. Calculator is ok. No notes. Explain some concept: (tunnel contact,
More informationSemiconductor Physics Problems 2015
Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and M-K Lee 1. The purest semiconductor crystals it is possible
More informationVLSI Design The MOS Transistor
VLSI Design The MOS Transistor Frank Sill Torres Universidade Federal de Minas Gerais (UFMG), Brazil VLSI Design: CMOS Technology 1 Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V
More informationECE-305: Fall 2017 MOS Capacitors and Transistors
ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue
More informationEE 3329 Electronic Devices Syllabus ( Extended Play )
EE 3329 - Electronic Devices Syllabus EE 3329 Electronic Devices Syllabus ( Extended Play ) The University of Texas at El Paso The following concepts can be part of the syllabus for the Electronic Devices
More informationESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. Refinement. Last Time. No Field. Body Contact
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 10: September 6, 01 MOS Transistor Basics Today MOS Transistor Topology Threshold Operating Regions Resistive Saturation
More informationR. Ludwig and G. Bogdanov RF Circuit Design: Theory and Applications 2 nd edition. Figures for Chapter 6
R. Ludwig and G. Bogdanov RF Circuit Design: Theory and Applications 2 nd edition Figures for Chapter 6 Free electron Conduction band Hole W g W C Forbidden Band or Bandgap W V Electron energy Hole Valence
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationMicroelectronic Devices and Circuits Lecture 9 - MOS Capacitors I - Outline Announcements Problem set 5 -
6.012 - Microelectronic Devices and Circuits Lecture 9 - MOS Capacitors I - Outline Announcements Problem set 5 - Posted on Stellar. Due net Wednesday. Qualitative description - MOS in thermal equilibrium
More informationLecture 11: MOS Transistor
Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Cross-section and layout
More information6.012 Electronic Devices and Circuits
Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to
More informationLecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 29-1 Lecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007 Contents: 1. Non-ideal and second-order
More information13. Bipolar transistors
Technische Universität Graz Institute of Solid State Physics 13. Bipolar transistors Jan. 16, 2019 Technische Universität Graz Institute of Solid State Physics bipolar transistors npn transistor collector
More informationLECTURE 3 MOSFETS II. MOS SCALING What is Scaling?
LECTURE 3 MOSFETS II Lecture 3 Goals* * Understand constant field and constant voltage scaling and their effects. Understand small geometry effects for MOS transistors and their implications modeling and
More informationLecture 04 Review of MOSFET
ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D
More informationGaN based transistors
GaN based transistors S FP FP dielectric G SiO 2 Al x Ga 1-x N barrier i-gan Buffer i-sic D Transistors "The Transistor was probably the most important invention of the 20th Century The American Institute
More informationReview of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model
Content- MOS Devices and Switching Circuits Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model A Cantoni 2009-2013 Digital Switching 1 Content- MOS
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More information! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 9, 019 MOS Transistor Theory, MOS Model Lecture Outline CMOS Process Enhancements Semiconductor Physics Band gaps Field Effects
More informationLecture 17 - The Bipolar Junction Transistor (I) Forward Active Regime. April 10, 2003
6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 17-1 Lecture 17 - The Bipolar Junction Transistor (I) Contents: Forward Active Regime April 10, 2003 1. BJT: structure and basic operation
More informationELECTRONICS IA 2017 SCHEME
ELECTRONICS IA 2017 SCHEME CONTENTS 1 [ 5 marks ]...4 2...5 a. [ 2 marks ]...5 b. [ 2 marks ]...5 c. [ 5 marks ]...5 d. [ 2 marks ]...5 3...6 a. [ 3 marks ]...6 b. [ 3 marks ]...6 4 [ 7 marks ]...7 5...8
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More information! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February, 07 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance Model!
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 10/02/2007 MS Junctions, Lecture 2 MOS Cap, Lecture 1 Reading: finish chapter14, start chapter16 Announcements Professor Javey will hold his OH at
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOS Capacitor with External Bias
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 5: Januar 6, 17 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation! Level
More informationAppendix 1: List of symbols
Appendix 1: List of symbols Symbol Description MKS Units a Acceleration m/s 2 a 0 Bohr radius m A Area m 2 A* Richardson constant m/s A C Collector area m 2 A E Emitter area m 2 b Bimolecular recombination
More informationMicroelectronics Part 1: Main CMOS circuits design rules
GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! med-amine.miled@polymtl.ca!
More informationConduction in Semiconductors -Review
Conduction in Semiconductors Review Intrinsic (undoped) Semiconductors intrinsic carrier concentration n i =.45x0 0 cm 3, at room temp. n = p = n i, in intrinsic (undoped) material n number of electrons,
More informationECE315 / ECE515 Lecture-2 Date:
Lecture-2 Date: 04.08.2016 NMOS I/V Characteristics Discussion on I/V Characteristics MOSFET Second Order Effect NMOS I-V Characteristics ECE315 / ECE515 Gradual Channel Approximation: Cut-off Linear/Triode
More informationIntroduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline
Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and
More informationScaling Issues in Planar FET: Dual Gate FET and FinFETs
Scaling Issues in Planar FET: Dual Gate FET and FinFETs Lecture 12 Dr. Amr Bayoumi Fall 2014 Advanced Devices (EC760) Arab Academy for Science and Technology - Cairo 1 Outline Scaling Issues for Planar
More informationan introduction to Semiconductor Devices
an introduction to Semiconductor Devices Donald A. Neamen Chapter 6 Fundamentals of the Metal-Oxide-Semiconductor Field-Effect Transistor Introduction: Chapter 6 1. MOSFET Structure 2. MOS Capacitor -
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type
More informationMSE 310/ECE 340: Electrical Properties of Materials Fall 2014 Department of Materials Science and Engineering Boise State University
MSE 310/ECE 340: Electrical Properties of Materials Fall 2014 Department of Materials Science and Engineering Boise State University Practice Final Exam 1 Read the questions carefully Label all figures
More informationECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University
NAME: PUID: : ECE 305 Exam 5 SOLUTIONS: April 17, 2015 Mark Lundstrom Purdue University This is a closed book exam. You may use a calculator and the formula sheet at the end of this exam. Following the
More informationMOSFET Capacitance Model
MOSFET Capacitance Model So far we discussed the MOSFET DC models. In real circuit operation, the device operates under time varying terminal voltages and the device operation can be described by: 1 small
More information