ELECTRONICS IA 2017 SCHEME

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1 ELECTRONICS IA 2017 SCHEME

2 CONTENTS 1 [ 5 marks ] a. [ 2 marks ]...5 b. [ 2 marks ]...5 c. [ 5 marks ]...5 d. [ 2 marks ] a. [ 3 marks ]...6 b. [ 3 marks ] [ 7 marks ] a. [ 4 marks ]...8 b. [ 2 marks ]...9 c. 9 i. [ 2 MARKS ]...9 ii. [ 2 MARKS ]...9 iii. [ 2 MARKS ] [ 8 marks ] a. 11 i. [ 2 MARKS ] Half-wave rectifier ii. [ 2 MARKS ] Full-wave rectifier iii. [ 2 MARKS ] Bridge rectifier b. [ 2 marks ] c. [ 2 marks ] a. [ 2 marks ] b. [ 2 marks ] c. [ 2 marks] d. [ 2 marks ] [ 6 marks ]... 14

3 10 [ 8 marks ] [ 12 marks ] [ 7 marks] a. [ 7 marks ] b. [ 9 marks ] a. [ 6 marks ] b. [ 3 marks ] c. [ 10 marks]... 23

4 1 [ 5 MARKS ] Microphone coupled to earpiece of stethoscope S/H DSP Signal Acquisition Sampling Quantization Encoding Processing and Storage Network transmission After the signal is acquired by a suitable transducer, in this case a microphone, it is fed to an Analog to Digital Convertor (ADC). The ADC samples the signal at regular intervals of time such that the sampling frequency, f s, is at least twice the maximum frequency, f max, in the captured signal. The samples are then quantized to a fixed number of levels. The resulting discretized signal is then encoded into bits and bytes. The digital signal processor (DSP) then reencodes/compresses the raw bytes to the format specified by mp3. This results in a smaller file which can then be transmitted over a network.

5 2 a. [ 2 MARKS ] Nyquist s criterion states that for a continuous time signal to be recovered exactly from the samples, the sampling rate must be more than twice the bandlimit of the original continuous time signal. f s 2f max b. [ 2 MARKS ] ADCs usually contain capacitors that must be recharged to some correct voltage prior to the acquisition of each sample. Thus, they are connected at the time of sampling. Therefore, there is an inrush of current as they charge and this constitutes a disruption of the input signal. c. [ 5 MARKS ] 4 bits implies 2 4 = 16 possible values/states per sample. In a range of 0-10V, the step size would be = 5 V/level V/level 8 d. [ 2 MARKS ] By increasing the number of levels.

6 3 a. [ 3 MARKS ] Fiber optic communication refers to exchange of information via light impulses along a fiber optic cable. The fiber optic cable essentially comprises a glass or plastic core and a reflective coating. A bunch of these are put together and protected by a jacket. Due to the high speeds and reliability of fiber optic communication, it is used to network/link computers servers and networking equipment. Thus through our usage of the internet and mobile phones, we use fiber optic communication in one way or another. b. [ 3 MARKS ] 1. It has greater capacity which implies higher speeds. 2. It has lower attenuation and can therefore take data over longer distances. 3. It is immune to external interference from electromagnetic fields. 4. The cables are small and light.

7 4 [ 7 MARKS ] V A GND By KCL i a + 3 = i b + i c In Nodal analysis this translates to 50 V A = V A 10 + V A V A = 4V A + V A V A = 40V Therefore, I a = 50 V A 5 = 2A I b = V A 10 = 4A I c = V A 40 = 1A

8 5 a. [ 4 MARKS ] When the P-type and N-type semiconductor materials are brought together, at the junction, the negative charges from the N side diffuse across the junction to the P side while positive charges diffuse from the P side across the junction to the P side. This constitutes a current termed diffusion current. They move over to recombine with the atoms there and hence a neutral region is created around the junction. This region is called the depletion region. Owing to the resulting electric field, thermally generated minority carriers i.e. negative charges in the P-type and positive charges in the N-type are swept across, drift across, the depletion region. This constitutes the drift current and it moves opposite to the diffusion current. Equilibrium is maintained by a built-in voltage known as the barrier potential.

9 b. [ 2 MARKS ] c. i. [ 2 MARKS ] When the diode is forward biased, granted a voltage high enough to overcome the barrier potential, the biasing voltage causes a significant quantity of current to flow through the diode. ii. [ 2 MARKS ] When the diode is reverse biased the depletion layer rather widens and therefore no current flow is expected. Due to the presence of minority carriers however, there is still a small leakage current that flows. iii. [ 2 MARKS ] As the reverse bias is increased, beyond a certain voltage, the diode breaks down and there is rather a large current flow as a result of the rise in the thermally generated minority carriers.

10 6 [ 8 MARKS ] Assuming the diode is forward biased and hence conducting ia ib By KCL, Using nodal analysis, 12 V x 1k i a = i b + i x = V x k + V x 4k 48 4V x = 2V x V x V x = 16 7 V V Since V x is positive and the other terminal of the diode is connected through a resistor to ground, the terminal connected to V x must be at a higher potential than that connected to the 4 kω resistor. Thus the diode is indeed forward biased. i x = i x = V x 4k = 1 ma ma 1750

11 7 a. i. [ 2 MARKS ] Half-wave rectifier ii. [ 2 MARKS ] Full-wave rectifier iii. [ 2 MARKS ] Bridge rectifier

12 b. [ 2 MARKS ] Constant voltages are required to maintain a bias state of a transistor. Thus feeding the transistor with the unsmoothed version would make it unstable. c. [ 2 MARKS ] Bridge rectifier with smoothing capacitor.

13 8 a. [ 2 MARKS ] For a half wave rectifier circuit I rms = I max 2 But I rms = V rms /R L I max = 2 V rms = R L 2M I max = 230 μa b. [ 2 MARKS ] c. [ 2 MARKS] I dc = I max π = 230μ π I dc = μa I rms = V rms = 230 R L 2M I rms = 115μA d. [ 2 MARKS ] P = I rms V rms = 115μA 230 P = mw

14 9 [ 6 MARKS ] The bipolar junction transistor is essentially like two PN junction diodes connected back to back. The voltage V BE applied across the base-emitter junction forward biases the junction and hence urges the negative charges from the N-type emitter to the P-type base. The base is made very thin and lightly doped and the collector rather large. For that matter, though the application of the V CB reverse biases the collector-base junction, most of the electrons injected into the base (from the emitter) are urged on through the collector. Thus, only a small current goes to the base terminal. Since V CB reverse biases the collector-base junction, increasing it does not narrow the depletion region and hence does not cause any significant increment in the current flow. Hence the collector current is almost unaffected by the collector potential.

15 10 [ 8 MARKS ] I C V 0 I B 30k Q1 20k 20k i0 1V IE 10V GND In the left loop Using nodal analysis for the right two loops 1 = 30k I B + V BE = 30k I B I B = 10μA I C = βi B = 80 10μA I C = 800μA I c + V k + V 0 20k = 0 800μ 20k + 2V 0 10 = 0 V 0 = 3V i 0 = V 0 20k = 3 20k i 0 = 150 μa Thus, the current i 0 moves in the direction opposite to the direction indicated in the diagram.

16 11 [ 12 MARKS ] V BB From the input (left side) DC self-bias circuit represented in Thevenin Equivalent circuit form V BB = R 2 R 1 + R 2 V CC and R B = R 1 R 2 V BB = I B R B + V BE + I E R E Assuming forward active, V BE = 0.7, and I E = (β + 1)I B From the output (right side) k 15 = I B ( ) 3k I B I B = μa I E = ma I C = ma V CC = I C R C + V CE + I E R E 15 = m 5k + V CE m 3k V CE = V Since I B > 0 and V CE > 0.2 V, the transistor is indeed in the forward active mode. V E = I E R E = m 3k V E = V V B = V BE + V E = V B = V

17 V C = V CE + V E = V C = V

18 12 [ 7 MARKS] g m = I C = 1m = 0.04 Ω 1 V T 25m r π = β 0 = 100 = 2.5 kω g m 0.04 r 0 = V A = 20 = 20 kω I C 1m

19 13 a. [ 7 MARKS ] Thevenin Voltage and Resistance: Assuming forward active, V BE = 0.7 V From the left side, From the right side, 8.6 V BB = 24 = V R B = k = kω I B = V BB V BE = = μa R B k I C = βi B = μa = ma V CC = I C R C + V CE V CE = 24 5k m V CE = V

20 Since I B > 0 and V CE > 0.2 the transistor is indeed in the forward active mode. b. [ 9 MARKS ] The input resistance The output resistance g m = I C = m = Ω 1 V T 25m r π = 750 Ω r 0 = V A 75 = = kω I C m R in = R B r π = Ω R out = r 0 R C = kω Therefore, the small signal equivalent circuit above can be reduced to By the voltage divider method,

21 R in V in = V S R S + R in V S = V in R S + R in R in Using the current divider, R out V out = g m V in R R out + R L L The voltage gain A v = V out V s = A v = R out g m V in R out + R R L L V in R S + R in R in g m R out R in R L (R out + R L )(R S + R in ) A v =

22 14 a. [ 6 MARKS ] The n-channel MOSFET is constructed from doped semiconductor materials as shown above. The two n-type regions have metal terminals connected directly to them: one being the drain terminal and the other being the source terminal. A third terminal is insulated from the middle P-type region; this is the gate terminal. The substrate is connected internally to the source. When a positive voltage is applied to the gate terminal, it repels the positive charges away from the upper region thereby creating a more negatively charged region. Thus, an n-channel is created and it links the two n-type regions. When a positive voltage is applied to the drain terminal, the negative charges are drawn all the way from the source through the channel to the drain. As this voltage is increased, the attraction felt by the negative charges around the drain region is stronger than at the source region. Hence the channel narrows as it gets to the source. Beyond a point, no increase in the V DS causes further narrowing and this is termed pinching off. b. [ 3 MARKS ] 1. Cutoff mode I D = 0

23 2. Triode mode 3. Saturation mode I D = K p W L (V GS V TH 1 2 V DS) V DS I D = 1 2 K p W L (V GS V TH ) 2 c. [ 10 MARKS] The Thevenin voltage and resistance are V GG = R G2 V R G + R DD = G V GG = 5 V R G = R G1 R G2 R G = 5 MΩ For a MOSFET, since the gate terminal is insulated, the gate current, I G = 0 From the right-hand loop, For a MOSFET I D = I S V G = V GG = 5V V DD = I D R D + V DS + I S R S V DD = I D (R D + R S ) + V DS

24 I D = V DD V DS R D + R S I D = 10 V DS 12k Assuming the MOSFET is in saturation and λ = 0 (1) I D = 1 2 K p W L (V GS V TH ) 2 I D = 1m 2 (V GS 1) 2 (2) From the left-hand loop V DD = V GS + I D R S I D = V GG V GS R S From (2) and (3) I D = 5 V GS 6k (3) 5 V GS 6k = 1m 2 (V GS 1) 2 5 V GS = 3(V GS 2V GS + 1) 3V 2 GS 5V GS 2 = 0 V GS = 2V or 1 3 V Since (V GS = 2) is greater than (V TH = 1), V GS = 2V is consistent with the assumption of saturation. Now from (1) I D = 5 2 6k = 0.5 ma 0.5m = 10 V DS 12k V DS = 4V Since V DS > V GS V TH i.e. (4 > 2 1). The MOSFET is indeed in saturation and all calculated values are valid. V GS = V G V S V S = V G V GS V S = 5 2

25 V S = 3V V DS = V D V S V D = V DS + V S V D = V D = 7V V G = 5 V, V S = 3V, V D = 7V

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