At point G V = = = = = = RB B B. IN RB f


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1 Common Emitter
2
3
4 At point G CE RC I C RC 116. R 1k C 116. ma I IC 116. ma β 100 F 116µ A I R ( 116µ A)( 20kΩ) 2. 3 R IN R f
5 Gain in Constant Current Region I I I C F β ( IN F ) R I R OUT CC C C R OUT CC C β ( ) R F IN F d d OUT IN R R C β F
6 FET Inverter (Common Source  CS)
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9 At Point C DS 55. RTH i D RTH 2. 0 R 500 TH 4 ma i k( ) D GS TR 2 GS id + k TR 4 ma + 2 1mA /
10 Output Gain in Constant Current Region I k( ) D IN TR 2 R I OUT TH TH D R k( ) 2 TH TH IN TR d d OUT IN 2R k( ) TH IN TR
11 Emitter Follower Input and output loops share load element x IN OUT x OUT Feedback
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13 Emitter Follower I X R F X IN OUT I R ( I + I ) R ( 1+ β ) I R OUT E E C E F E Assuming Constant Current Operation I R IN OUT F I ( 1+ β ) I R R IN F E F [ R + ( 1+ β ) I R ] I F E IN F
14 I R IN F + ( 1+ β ) R F E R OUT ( )( 1+ β ) R R + ( 1+ β ) R << ( 1+ β ) R F E IN F F E F E IN CE > F > SAT OUT IN F Current Gain of Emitter Follower I I + I LOAD C I + β I F ( 1+ β ) I F I I IN
15 I I LOAD IN ( 1+ β ) F "Current Gain" R IN IN I R IN IN F + ( 1+ β ) R F E R IN IN R R IN F [ + ( 1+ β ) ] F E
16 FET Follower OUT I S R S I D R S GS IN  OUT IN  I D R S GS changes with I D (feedback) can use iterative graphical approach to solve
17 R DD IN TR S 15 8 k 05. ma / 2 1kΩ 2
18 Common ase (C) (Tracking Configuration)
19 I I I + I IN E C ( 1+ β ) I F I IIN ( 1+ β ) F β F IC β F I I ( 1+ β ) F IN I R OUT CC C L β F CC RL I ( 1 + β ) F IN
20 Common ase Transfer Function
21 Cascode Configuration
22 iasing Allows nonlinear elements to be treated as linear elements (under certain conditions) Different techniques for Discrete and Integrated designs Avoid nonlinearities of I characteristics by choosing a portion of the curve over which the device will operate
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33 For JT of Fig R 1kΩ R 100 kω β CC C F F with A 0 ias levels I β I β C F F ( F ) ( ) R 100 kω 5mA I R 10 ( 5mA)(1k Ω) 5 CE CC C C Nonlinear Regions egin at 10 I 0 CE CC C (Cutoff) CE SAT CE SAT 0. 2 IC ma (Saturation) R C
34 Minimum A A MIN A MIN A MIN Maximum I A MAX IC ( SAT ) 9. 8 ma β ma + A MAX F R I MAX I R + A MAX MAX R F A MAX A MAX ( ma)(100 k)
35 Fixed oltages and Current iasing A simple way of eliminating a separate biasing source is to replace it with one of the power supply buses ias values are adjusted by selecting proper resistors in the input loop
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37 10 R 1kΩ β 100 CC C F Find R that will result in bias value C 5 I R C CC C C I I C 5mA IC β F 0. 05mA I CC R F R CC I F kω
38 GS R A R + R DD 0. 5MΩ MΩ
39 Assume transistor in constant current region ( ) I k( ) 1mA / 4 2 D GS TR 4 ma I R DS DD D D 16 ( 4 ma)(2 kω) 8 i.e. > ( ) DS GS TR Constant Current Note: No current through gate of transistor
40 Parameter Independent iasing Previous biasing techniques are sensitive to device parameters such as β F, k and TR which are in turn sensitive to temperature and fabrication variances. One configuration called feedback biasing is virtually independent of device parameters
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43 I R ( I + I ) R E I I + I I R ( I + I ) R 2 CC 2 C 2 1 E Input loop and output loop share the voltage drop (I 2 + I 1 )R E. This feedback mechanism is responsible for stabilizing bias levels against device parameters. Difficult to use graphical analysis to analyze circuit Example: Given 2, k 0.5 ma /, R 1MΩ, R 2 MΩ, R 1kΩ, R TR A D E 5kΩ 2 (A) Find I, () Find I if k is changed to 1 ma / 2 D D
44
45 Solution: R A R + R DD 2 MΩ MΩ + 2 MΩ ( ) Assume FET operates in the constant current region (must confirm later). I k( ) 2 D GS TR I k( I R ) 2 D D E TR
46 I D RE I D + 2RE ( TR ) TR 0 k + ( ) I 2 2 D ( 5kΩ) 25I 2 D 1 I D + 2( 5kΩ)( 8 2 ) mA / 62 I D + ( 8 2) 0 2 Applying quadratic formula I D 0. 93A I 155. ma D
47 First value gives 3.36, second value gives GS GS 0.24 (not valid cutoff) I ( R + R ) DS CC D D E Note: mA ( 1kΩ + 5kΩ) > DS GS TR Therefore constant current region 2 If k 10. ma / then 3, I 10. ma GS 100% change in k results in only a 7.5% change in I D D
48 JT Feedback ias
49 Problem: Find the vlaue of I C if βf varies from 50 to 200. F 0.7 CC R2 R + R kω kω + 20 kω 4 R R R kω
50 β F 50: I C 50( ) 6.67 kω + 51( 1kΩ) ma β F 200: I C 200( ) 6.67 kω + 201( 1kΩ) 318. ma β Changes by a factor of 4 I Changes by 11 % C
51 Same problem without R E 4 R kω I R F I R F kω ma
52 β 50: I β I 50( ma) 24. 5mA F C β 200: I β I 200( ma) 98 ma F C β Changes by a factor of 4 I Changes by a factor of 4 C Note: Current gain without R is greater (i.e. Sacrifice some gain for stability) E
53 iasing with ipolar Supplies The use of bipolar supplies can improve bias designs Facilitates DC  coupled input signals Allows outputs to be set to a bias level of zero In some cases can reduce the number of resistors in the bias circuit A bipolar supply bus is formed by positive and negative DC voltage sources each connected to a common ground
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55 For a periodic AC waveform with no DC component the transistor input looks like a DC ground Applying KL F + I E RE + EE 0 For large βf I E ( EE F IC ) R E I R R C CC C C CC + ( EE + F ) R C E E F
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