MOS Transistor Theory


 Ferdinand Carter
 2 years ago
 Views:
Transcription
1 CHAPTER 3 MOS Transistor Theory
2 Outline 2 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models
3 MOS Transistor symbols Introduction 3 nmos symbols pmos symbols
4 MOS Structure 4 Accumulation Mode Depletion Mode Inversion Mode
5 Cutoff nmos Operation Regions 5 V gs < V t : no channel Linear V gs > V t, V gd > V t : linear resistor Saturation V gs > V t, V gd < V t : channel pinchoff
6 Outline 6 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models
7 MOS Channel Charge Q C V V C V V V channel g gc t g gs ds t C WL t C WL g ox ox ox Qchannel L E, E Vds / L, Ids, tchannel t channel
8 Q C WL V V V 1 channel gs 2 ds t ds ox E, E V / L, 2 L L L E V I Q t channel channel, t ds ds channel Ideal IV Equations 8 L Ideal IV equation I ds Q t channel channel Qchannel L/ W Vds C V V V L 2 Vds Vgs Vt Vds 2 ox gs t ds Ids V V V 2 V 2 0 V 2 gs Vt gs t ds ds V gs V t V V V V ds dsat gs t V V V V ds dsat gs t cutoff linear saturation
9 Ideal IV Characteristics 9 nmos IV pmos IV
10 Outline Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models
11 Nonideal IV Effects 11 Velocity saturation: at high V ds, the carrier velocity is not proportional to lateral field. I ds decrease. Mobility degradation: at high V gs, the carrier scatter more and mobility decrease. I ds decrease. Channel length modulation effect: at high V ds, depletion of S/D, effective L. I ds increase. Subthreshold conduction: V gs < V t, I ds is exponentially dropoff instead of abruptly becoming zero. Drain/Source leakage: reverse diode junction leakage. Nonzero gate current I g : carriers tunneling effect. Body effect: threshold voltage V t is influence by V bs (bodytosource voltage).
12 Velocity Saturation 12 Carrier velocity : nonlinearly proportional to lateral electrical field before velocity saturation E 1E E lat lat sat : carrier velocity : mobility E V L : lateral electrical field E lat sat ds sat I ds will saturate due to velocity saturation, it depends on channel length L and applied V ds. Qchannel Qchannel I C W V V t L/ ds ox gs t sat channel sat
13 Ids I dsat 0 V V I dsat ds dsat αpower Law Model 13 αpower Law Model: piecelinear model to illustrate MOSs IV characteristic with velocity saturation. V V V gs ds ds Idsat Pc Vgs V t 2 V t V V dsat dsat cutoff linear saturation, V /2 dsat P Vgs V t Empirical parameters: Pc, P, Because of μ p < μ n, pmos experience less velocity saturation than nmos, therefore α p > α n Mobility degradation is modeled by a μ eff < μ, and the it can be included in the parameter α
14 Channel Length Modulation 14 Effective channel length: is reduced due the wider depletion region at high V ds L L L eff d The IV equation at saturation region with channel length modulation effect. λ is the empirical parameter 2 Vgs Vt Ids 1 Vds, / L 2 With shorter L, λ, result in output resistance, then MOSFET s intrinsic gain
15 Body Effect 15 The threshold voltage V t is increased by positive V sb. V sb < 0, V t, OFF leakage Design tradeoff N A Vt Vt 0 [ 2 s Vsb 2 s ], s 2T ln n V t0 : the threshold voltage for V sb = 0 φ f : fabricationprocess parameter i t ox ox 2qN A si 2qN C ox A si γ : Bodyeffect parameter (fabricationprocess parameter) N A : Doping concentration of ptype substrate ε s : permittivity of silicon=11.7 ε 0
16 Subthreshold Conduction 16 Leakage current at subthreshold region V gs < V t : weak inversion Ids I e e V V V nt T ds0 1 gs t ds I ds0 e T Leakage current = 0, when V ds = 0. It increase exponentially with V gs. DrainInduced Barrier Lowering (DIBL) : the V t will be reduced by a positive V ds. It will worse the leakage at subthreshold. It acts like channel length modulation effect at active mode. VtV t Vds
17 Junction Leakage 17 S/D junction leakage from a reversebiased diode VD T ID IS e 1 Junction leakage used to be the storage time limitation. In modern transistor with shorter length, subthreshold leakage far exceed junction leakage.
18 Tunneling 18 Gate leakage: from carriers' tunneling through gate oxide. It is exponentially reverse proportional to gate oxide. HiK (dielectric constant) gate insulator is used to reduce it.
19 Temperature Dependence 19 T μ : T T T r Tr k T V t : V T V T k T T t t r t r T I OFF I ON T I dsat T The circuit performance is improved: subthreshold leakage, saturation velocity, mobility, junction capacitance. But breakdown voltage.
20 Geometry Dependence 20 Effective channel length and width L L X 2L eff drawn L D X L, X : Poly overetch W W W X 2W eff drawn W D L, W :Sourcedrian lateral diffusion Use identical and same orientation MOSFET to get a good matching. ex. Current mirror D D
21 Outline Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models
22 CV Characteristics 22 Gate capacitance: with advance technology, t ox, L, C permicron keeps constant. C C WL C W g ox permicron ox Cpermicron CoxL L tox Parasitic capacitance: C db and C sb are from reverse pn junction and proportional to S/D area.
23 MOS Gate Capacitance Model 23 Gate capacitance: it varies with channel behavior at different operation region C C WL 0 ox S/D overlap capacitance: C gs(overlap) & C gd(overlap) are from S/D lateral diffusion, don t confused with C gs & C gd C C W gs( overlap ) gd ( overlap ) gsol C C W gdol
24 C gc vs. V gs & V ds 24 C gc vs. V gs C gc vs. V ds
25 Gate Capacitance vs. V ds 25 Long channel device: C gd will becomes near 0 at saturation Short channel device: more C gd(overlap) and C gs(overlap) factor
26 DataDependent Gate Capacitance 26
27 Outline Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models
28 CMOS Inverter DC Characteristic I 28
29 CMOS Inverter DC Characteristic II 29 I ds vs. V ds (nmos & pmos) For pmos, I d, V gs, V ds, V th <0 pmos IV as loadline of nmos input device.
30 CMOS Inverter DC Characteristic III 30 V in V out DC transfer curve Railtorail operation V in I DD DC transfer curve Dynamic power dissipation
31 DC Response 31 DC Response: V out vs. V in for a gate Ex: Inverter When V in = 0 > V out = V DD When V in = V DD > V out = 0 In between, V out depends on transistor size and current By KCL, must settle such that I dsn = I dsp We could solve equations V in But graphical solution gives more insight V DD I dsp I dsn V out
32 Transistor Operation 32 Current depends on region of transistor behavior For what V in and V out are nmos and pmos in Cutoff? Linear? Saturation?
33 nmos Operation 33 Cutoff Linear Saturated V gsn < V gsn > V gsn > V dsn < V dsn > V DD V in I dsp I dsn V out
34 nmos Operation 34 Cutoff Linear Saturated V gsn < V tn V gsn > V tn V gsn > V tn V dsn < V gsn V tn V dsn > V gsn V tn V DD V in I dsp I dsn V out
35 nmos Operation 35 Cutoff Linear Saturated V gsn < V tn V gsn > V tn V gsn > V tn V dsn < V gsn V tn V dsn > V gsn V tn V DD V gsn = V in V dsn = V out V in I dsp I dsn V out
36 nmos Operation 33 Cutoff Linear Saturated V gsn < V tn V in < V tn V gsn > V tn V in > V tn V dsn < V gsn V tn V out < V in  V tn V gsn > V tn V in > V tn V dsn > V gsn V tn V out > V in  V tn V DD V gsn = V in V dsn = V out V in I dsp I dsn V out
37 pmos Operation 37 Cutoff Linear Saturated V gsp > V gsp < V gsp < V dsp > V dsp < V DD V in I dsp I dsn V out
38 pmos Operation 38 Cutoff Linear Saturated V gsp > V tp V gsp < V tp V gsp < V tp V dsp > V gsp V tp V dsp < V gsp V tp V DD V in I dsp I dsn V out
39 pmos Operation 39 Cutoff Linear Saturated V gsp > V tp V gsp < V tp V gsp < V tp V dsp > V gsp V tp V dsp < V gsp V tp V DD V gsp = V in  V DD V dsp = V out  V DD V tp < 0 V in I dsp I dsn V out
40 pmos Operation 40 Cutoff Linear Saturated V gsp > V tp V in > V DD + V tp V gsp < V tp V in < V DD + V tp V dsp > V gsp V tp V out > V in  V tp V gsp < V tp V in < V DD + V tp V dsp < V gsp V tp V out < V in  V tp V DD V gsp = V in  V DD V dsp = V out  V DD V tp < 0 V in I dsp I dsn V out
41 IV Characteristics 41 Make pmos is wider than nmos such that n = p V gsn5 I dsn V gsn4 V gsn3 V dsp V gsp1 V gsp2 V DD 0 V DD V gsn2 V gsn1 V gsp3 V dsn V gsp4 I dsp V gsp5
42 Current vs. V out, V in 42 V in0 V in5 I dsn, I dsp V in1 V in4 V in2 V in3 V in3 V in4 V in2 V in1 V out V DD
43 Load Line Analysis 43 For a given V in : Plot I dsn, I dsp vs. V out V out must be where currents are equal in V in0 V in5 I dsn, I dsp V in1 V in4 V in2 V in3 V DD I dsp V in3 V in4 V in2 V in1 V in I dsn V out V out V DD
44 Load Line Analysis 44 V in = 0 V in0 I dsn, I dsp V in0 V out V DD
45 Load Line Analysis 45 V in = 0.2V DD I dsn, I dsp V in1 V in1 V out V DD
46 Load Line Analysis 46 V in = 0.4V DD I dsn, I dsp V in2 V in2 V out V DD
47 Load Line Analysis 47 V in = 0.6V DD I dsn, I dsp V in3 V in3 V out V DD
48 Load Line Analysis 48 V in = 0.8V DD I dsn, I dsp V in4 V in4 V out V DD
49 Load Line Analysis 49 V in = V DD V in0 V in5 I dsn, I dsp V in1 V in2 V in3 V in4 V out V DD
50 Load Line Summary 50 V in0 V in5 I dsn, I dsp V in1 V in4 V in2 V in3 V in3 V in4 V in2 V in1 V out V DD
51 DC Transfer Curve 51 Transcribe points onto V in vs. V out plot V DD A B V in0 V in5 V in1 V in4 V out C V in2 V in3 V in3 V in4 V in2 V in1 0 D E V tn V DD /2 V DD +V tp V out V DD V in V DD
52 Operating Regions 52 Revisit transistor operating regions Region nmos pmos A B C D E V out V DD A B 0 C D E V tn V DD /2 V DD +V tp V in V DD
53 Operating Regions 53 Revisit transistor operating regions Region nmos pmos A Cutoff Linear B Saturation Linear C Saturation Saturation D Linear Saturation E Linear Cutoff V out V DD A B 0 C D E V tn V DD /2 V DD +V tp V in V DD
54 CMOS Inverter Operation 54
55 Beta Ratio Effect 55 β parameters and ratio C p p ox p C W L W L n n ox n ratio p n β ratio = 1: largest noise margin μ n > μ p, choose (W/L) p > (W/L) n to make β ratio = 1 β ratio > 1: HIskewed inverter, switching threshold > 0.5V DD β ratio < 1: LOskewed inverter, switching threshold < 0.5V DD
56 Noise Margin I 56 Noise margin definition The allowable noise voltage on the input that the output wont be corrupted. V V V V IH IL OH OL NM V V L IL OL NM V V H OH IH minimum HIGH input voltage maximum LOW input voltage minimum HIGH output voltage maximum LOW output voltage
57 Indeterminate region (forbidden zone) Noise Margin II 57 V V V : output unknown logic level IL in IH
58 β ratio > 1 β Ratio and Noise Margin 58 Switching threshold > 0.5V DD V IH NM H V IL NM L β ratio < 1 Switching threshold < 0.5V DD V IH NM H V IL NM L Noise is scaled with V DD VDD, smaller NM is acceptable.
59 Ratioed Inverter Transfer Function I 59 nmos inverters with resistive of constant current load Transfer function depends on the ratio of pulldown to the pullup transistor (static load).
60 Ratioed Inverter Transfer Function II 60 PseudonMOS inverters with turnon pmos as load TurnON pmos is made by a depletion mode nmos in pure nmos process. Dissipating static power when V o = LOW Poor NM but smaller area & input capacitance loading
61 Pass Transistor DC Characteristic 61 Threshold drop nmos : can NOT pass 1 pmos : can NOT pass 0 Need to consider BODY EFFECT. ON resistance depends on V in Need to BOOST gate voltage with small V DD
62 Inverter + transmission gate Tristate Inverter 62 For the same size n and p devices, it is approximately half the speed of complementary CMOS inverter. The structure in (d) is suffered from A s toggle in tristate. Need to consider BODY EFFECT.
63 Outline Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models
64 Effective Resistance R 64 R: effective resistance of unit nmos (minimum W & L) An pmos has resistance 2R(or 3R) because of smaller mobility In linear region, it is inverse proportional to W/L and V gs 1 I ds 1 1 L 1 R Vds C W Vgs V t ox Vgs Vt C: gate capacitance of unit transistor (nmos & pmos) It is proportional to gate area W*L C: junction capacitance of S/D of unit transistor It is proportional to gate width W nmos of k times unit width has resistance R/k, gate capacitance kc and S/D capacitance kc.
65 RC Circuit Model 65 pmos of k times unit width has resistance 2R/k, gate capacitance kc and S/D capacitance kc nmos parasitic capacitors are referred to GND (pbody) and pmos parasitic capacitors are referred to VDD (nwell)
66 Inverter Propagation Delay 66 Fanoutof1 Inverter Choose pmos width size to be x2~x3 of that of nmos t R 6C 6RC pd
67 R of Transmission Gate 67 Effective resistance of transmission gate is the parallel combination of nmos and pmos It depends on the signal to be pass pmos pass 0 weakly with larger resistance 4R nmos pass 1 weakly with larger resistance 2R Usually choose same size of nmos/pmos in transmission gate Increase MOS size R C : need to check the tradeoff
MOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationDC and Transient Responses (i.e. delay) (some comments on power too!)
DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02  CMOS Transistor Theory & the Effects of Scaling
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationMOS Transistor IV Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor IV Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded
More informationLecture 6: DC & Transient Response
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins
More informationLecture 5: CMOS Transistor Theory
Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos IV Characteristics
More informationEE5780 Advanced VLSI CAD
EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay
More informationVLSI Design The MOS Transistor
VLSI Design The MOS Transistor Frank Sill Torres Universidade Federal de Minas Gerais (UFMG), Brazil VLSI Design: CMOS Technology 1 Outline Introduction MOS Capacitor nmos IV Characteristics pmos IV
More informationDC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575604 yrpeng@uark.edu Pass Transistors We have assumed source is
More informationLecture 4: DC & Transient Response
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide
More informationDC & Transient Responses
ECEN454 Digital Integrated Circuit Design DC & Transient Responses ECEN 454 DC Response DC Response: vs. for a gate Ex: Inverter When = > = When = > = In between, depends on transistor size and current
More informationEEE 421 VLSI Circuits
EEE 421 CMOS Properties Full railtorail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationLecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos IV Characteristics pmos IV Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More information5. CMOS Gate Characteristics CS755
5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NORgate C = NOT (A or B)
1 Introduction to TransistorLevel Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationIntroduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline
Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
More informationChapter 2 CMOS Transistor Theory. JinFu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 2 CMOS Transistor Theory JinFu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor JinFu Li, EE,
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
More informationChapter 2 MOS Transistor theory
Chapter MOS Transistor theory.1 Introduction An MOS transistor is a majoritycarrier device, which the current a conductg channel between the source and the dra is modulated by a voltage applied to the
More informationMOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA
MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the FieldEffect Transistor! Julius Lilienfeld filed a patent describing
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationNanoscale CMOS Design Issues
Nanoscale CMOS Design Issues Jaydeep P. Kulkarni Assistant Professor, ECE Department The University of Texas at Austin jaydeep@austin.utexas.edu Fall, 2017, VLSI1 Class Transistor IV Review Agenda Nonideal
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationEEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins,
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V
More informationLecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationChapter 4 FieldEffect Transistors
Chapter 4 FieldEffect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 41 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More informationCMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationTopic 4. The CMOS Inverter
Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ Email: p.cheung@ic.ac.uk Topic 41 Noise in Digital Integrated
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ualwell TrenchIsolated
More informationECE 497 JS Lecture  12 Device Technologies
ECE 497 JS Lecture  12 Device Technologies Spring 2004 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density
More informationEEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring
More informationEE5311 Digital IC Design
EE5311 Digital IC Design Module 1  The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM
More informationToday s lecture. EE141 Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
 Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
More informationMOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor
MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET Calculation of t and Important 2 nd Order Effects SmallSignal Signal MOSFET Model Summary Material from: CMOS LSI Design By Weste
More informationCS/EE Ntype Transistor
CS/EE 6710 MOS Transistor Models Electrical Effects Propagation Delay Ntype Transistor D + G Vds i electrons +Vgs S  1 Another Cutaway View Thanks to National Central University for Some images Vgs Forms
More informationDigital Microelectronic Circuits ( ) The CMOS Inverter. Lecture 4: Presented by: Adam Teman
Digital Microelectronic Circuits (3611301 ) Presented by: Adam Teman Lecture 4: The CMOS Inverter 1 Last Lectures Moore s Law Terminology» Static Properties» Dynamic Properties» Power The MOSFET Transistor»
More informationThe Devices: MOS Transistors
The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, AddisonWesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor
More informationLecture 12 Circuits numériques (II)
Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationUniversity of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA
University of Pennsylvania Department of Electrical Engineering ESE 570 Midterm Exam March 4, 03 FORMULAS AND DATA. PHYSICAL CONSTANTS: n i = intrinsic concentration undoped) silicon =.45 x 0 0 cm 3 @
More informationL ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling
L13 04202017 ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling Scaling laws: Generalized scaling (GS) p. 610 Design steps p.613 Nanotransistor issues (page 626) Degradation
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationCMOS Technology for Computer Architects
CMOS Technology for Computer Architects Recap Technology Trends Lecture 2: Transistor Inverter Iakovos Mavroidis Giorgos Passas Manolis Katevenis FORTHICS (University of Crete) 1 2 Recap Threshold Voltage
More informationEE105  Fall 2005 Microelectronic Devices and Circuits
EE105  Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture
More informationand V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
More informationReview of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model
Content MOS Devices and Switching Circuits Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model A Cantoni 20092013 Digital Switching 1 Content MOS
More informationP. R. Nelson 1 ECE418  VLSI. Midterm Exam. Solutions
P. R. Nelson 1 ECE418  VLSI Midterm Exam Solutions 1. (8 points) Draw the crosssection view for AA. The crosssection view is as shown below.. ( points) Can you tell which of the metal1 regions is the
More informationAnnouncements. EE141 Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power
 Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 123pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 111:3 Thursday, October 6, 6:38:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationDigital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationECE 342 Solid State Devices & Circuits 4. CMOS
ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationDigital Integrated Circuits
Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Shortcircuit current The CMOS inverter :
More information2007 Fall: Electronic Circuits 2 CHAPTER 10. DeogKyoon Jeong School of Electrical Engineering
007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits DeogKyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full railtorail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationLecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:308:00pm in 105 Northgate
EE4Fall 2008 Digital Integrated Circuits Lecture VTCs and Delay Lecture # Announcements No lab today, Mon., Tues. Labs restart next week Midterm # Tues. Oct. 7 th, 6:308:00pm in 05 Northgate Exam is
More information5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1
5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design
More informationChapter 5. The Inverter. V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov Inverter
Chapter 5 The Inverter V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov.12 03 Objective of This Chapter Use Inverter to know basic CMOS Circuits Operations Watch for performance Index such as Speed (Delay calculation)
More informationEE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing
EE115C Winter 2017 Digital Electronic Circuits Lecture 3: MOS RC Model, CMOS Manufacturing Agenda MOS Transistor: RC Model (pp. 104113) S R on D CMOS Manufacturing Process (pp. 3646) S S C GS G G C GD
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationECEN474/704: (Analog) VLSI Circuit Design Spring 2018
ECEN474/704: (Analog) SI Circuit Design Spring 2018 ecture 2: MOS ransistor Modeling Sam Palermo Analog & MixedSignal Center exas A&M University Announcements If you haven t already, turn in your 0.18um
More informationLow Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur
Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture No. # 08 MOS Inverters  III Hello, and welcome to today
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 10/30/2007 MOSFETs Lecture 4 Reading: Chapter 17, 19 Announcements The next HW set is due on Thursday. Midterm 2 is next week!!!! Threshold and Subthreshold
More informationLecture 11: MOS Transistor
Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Crosssection and layout
More informationPractice 3: Semiconductors
Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given
More informationMiscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]
Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an NSwitch, the
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!
More informationLECTURE 3 MOSFETS II. MOS SCALING What is Scaling?
LECTURE 3 MOSFETS II Lecture 3 Goals* * Understand constant field and constant voltage scaling and their effects. Understand small geometry effects for MOS transistors and their implications modeling and
More informationQuantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current.
Quantitative MOSFET Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. V DS _ n source polysilicon gate y = y * 0 x metal interconnect to
More informationMOSFET and CMOS Gate. Copy Right by Wentai Liu
MOSFET and CMOS Gate CMOS Inverter DC Analysis  Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max
More informationThe Devices. Jan M. Rabaey
The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models
More informationLecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I curve (SquareLaw Model)
More informationScaling Issues in Planar FET: Dual Gate FET and FinFETs
Scaling Issues in Planar FET: Dual Gate FET and FinFETs Lecture 12 Dr. Amr Bayoumi Fall 2014 Advanced Devices (EC760) Arab Academy for Science and Technology  Cairo 1 Outline Scaling Issues for Planar
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationThe Devices. Devices
The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ FieldOxyde (SiO 2 ) psubstrate p+ stopper Bulk Contact CROSSSECTION of NMOS Transistor CrossSection of CMOS Technology MOS transistors
More information! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February, 07 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance Model!
More informationLecture 12: MOSFET Devices
Lecture 12: MOSFET Devices GuYeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
More informationLecture 14  Digital Circuits (III) CMOS. April 1, 2003
6.12  Microelectronic Devices and Circuits  Spring 23 Lecture 141 Lecture 14  Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:
More informationMidterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February 4, 2016 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance
More informationCheck course home page periodically for announcements. Homework 2 is due TODAY by 5pm In 240 Cory
EE141 Fall 005 Lecture 6 MOS Capacitances, Propagation elay Important! Check course home page periodically for announcements Homework is due TOAY by 5pm In 40 Cory Homework 3 will be posted TOAY ue Thursday
More information4.10 The CMOS Digital Logic Inverter
11/11/2004 section 4_10 The CMOS Digital Inverter blank.doc 1/1 4.10 The CMOS Digital Logic Inverter Reading Assignment: pp. 336346 Complementary MOSFET (CMOS) is the predominant technology for constructing
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler
More informationCHAPTER 5 MOS FIELDEFFECT TRANSISTORS
CHAPTER 5 MOS FIELDEFFECT TRANSISTORS 5.1 The MOS capacitor 5.2 The enhancementtype NMOS transistor 5.3 IV characteristics of enhancement mode MOSFETS 5.4 The PMOS transistor and CMOS technology 5.5
More informationMicroelectronics Part 1: Main CMOS circuits design rules
GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! medamine.miled@polymtl.ca!
More informationCMOS Logic Gates. University of Connecticut 181
CMOS Logic Gates University of Connecticut 181 Basic CMOS Inverter Operation V IN P O N O pchannel enhancementtype MOSFET; V T < 0 nchannel enhancementtype MOSFET; V T > 0 If V IN 0, N O is cut off and
More informationVLSI Design and Simulation
VLSI Design and Simulation CMOS Inverters Topics Inverter VTC Noise Margin Static Load Inverters CMOS Inverter FirstOrder DC Analysis R p V OL = 0 V OH = R n =0 = CMOS Inverter: Transient Response R p
More informationNon Ideal Transistor Behavior
Non Ideal Transistor Behavior Slides adapted from: N. Weste, D. Harris, CMOS VLSI Design, Addison Wesley, 3/e, 2004 1 Nonideal Transistor IV effects Non ideal transistor Behavior Channel Length ModulaJon
More information