DEPARTMENT OF ECE UNIT VII BIASING & STABILIZATION AMPLIFIER:


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1 UNIT VII IASING & STAILIZATION AMPLIFIE:  A circuit that increases the amplitude of given signal is an amplifier  Small ac signal applied to an amplifier is obtained as large a.c. signal of same frequency at output. iasing a Transistor Amplifier.  Input signal is applied between base and emitter  Output is taken out between Collector and emitter. I CC 3.5mA Icmax 3mA AC load line 1.5mA DC load line 12V D VCE max 24V. DC LOAD LINE:  V CC V CE + I C L  24V V CE + 0. VCE Max V CE 24V  For Ic max, transistor is in saturation. V CE drop is 0.2V, Ideally V CE 0 V CC V CE + I CC V CC 0 + I C C VCC or I cmax 24/8k 3mA C V CE 1
2 Optimum operating point point is called Quiescent point V 12Volts 2 IC max mA 2 θ CE max 24 VCEQ 2 I CQ VCE max 24 VCE Q 12volts 2 2 Ic max 3 ICQ 1.5mA 2 2 Ac load ac C L kΩ Max V CE V CE Q + IcQ ac (Point D) x 103 x 6 x volts Max collector current VCE φ 12V IcQ + 15mA 3.5 ma. ac 6k I C max 3.5mA (Point C) Line joining C & D is called ac load line. 1Q) Determine the quiescent current and collector to emitter voltage for germanium transistor with β 50 in selfbiasing arrangement draw the circuit with given component value V CC 20V, C 2K, E 100Ω, 2 5K (Also find out stability factor). (May 2005) Solution:  +20V For drawing DC load line we must know a) V CE max when Ic 0 b) Ic max when V CE 0 V CE max VC C 20V Quiescent V CE Q Quiescent I C Q V CE VCC 20 IC IE IC max 9.52mA max 20 10V 2 2 Ic max mA 2 2 C E 5K 2
3 I C φ 4.76 Quiescent I Q mA β 50 Quiescent I E Q I C Q + I Q 4.855mA. Q2) For transistor amplifier shown in the fig. L 1.5kΩ and V E 0.7V Solution: i) Draw DC load line ii) Determine operating point iii) Draw AC load line i) DC load line DC load line V CC V CE + I C ( C + E ) (I C I E ) V CEmax + V CC 12V VCC 12 Ic max 6mA K C E ( ) ii) iii) Operating Point Voltage across 2, 4K 2 V 2, VCC 12 4volts ( 8 + 4) K V2 V V 2 V E + I E E or C IE 3 E 1 10 I E V CC I C ( C + E ) x 103 (2 x 10 3 ) 5.4 volts Therefore operating point or quiescent point Q (5.4 V1 3.3mA) AC load line We should V CE max & I C max. C L AC load resistance ac C L 0.6kΩ C + L 2.5 V CE max V CE Q + IcQ. ac x 103 x 0.6 x Volts (Point C) VCE Q Ic max IcQ mA ac (Point D) 3
4 THEMAL UN AWAY:  Collector current I C βi + (β+1) I CO  β, I, I CO all increase with temperature  I CO doubles for every 10 C rise in temperature  Collector current causes junction temperature to rise, which in term rises  I CO rise in Ic.  This cumulative process leads to collector current to increase further and transistor may be destroyed.  This phenomenon is called thermal un away.  emedy:  1) To reduce base current with rise in temperature using NTC components  2) Making collector larger in size and using heat sink to dissipate heat.  STAILITY FACTO (S)  The extent to which the collector current I C is stabilized with varying Ico is measured by stability factor S.  It is defined as the rate of change of collector current to the change in Ico, keeping I and as constant.  IC dic S, β & I Constant Or S ICO dico  Collector current Ic βi + (β+1) I CO  (1) Differencing eqn. (1) with repeat to Ic. dic dβ I d( β + 1) Ico dic dic dic di DICO 1 β + ( β + 1) dic dic di β β dic S β + 1 Or S di 1 β dic  S should be as small as possible to have better stability Stability Factor S and S. dic Ic S ', Ico & β constant dve VE dic Ic S ", Ico & VE dβ β constant Methods of Transistor iasing:  Types of iasing:  a) Fixed ias or base resistor ias b) Collector to ase bias or biasing with feet back resistor 4
5 c) Selfbias or emitter bias or potential divides ias. a) Fixed ias: y DC analysis V I + V  (1) CC. E V V CC E I  (2) 1+ β Stability Factor S di 1 β dic Since I is not depending on Ic as per equation (2). 1+ β S 1+ β  (3) 1 β (0) Since β is a large quality and varies from device to device. This is very poor circuit for stability for bias. Advantages of fixed ias:  a) Simple circuit b) Small number of components c) If V CC is very large, compared to V E then (as per equation 2) I is independent of V E. COLLECTO TO ASE IAS:  I  V CE I + V E VCE  V E 5
6  If the collector current increases due to increase in temperature or the transistor is replaced by one with higher β, the voltage drop across C increases.  So, less V CE and less I, to compensate increase in Ic i.e., greater stability ( ) V I + I + I + V  (1) CC C C E IC + ICC + I + VE I + + I + V ( ) C C C E V V I C + di C d + CC E C C Or I IC C Stability Factor: 1+ β S di 1 β dic Putting the value of di / di C from equation (3) 1+ β 1+ β S C C 1 β 1+ β C + C +  (2)  (3) Note:  1) Value of S is less than that of fixed bias (which is S 1+β) 1) S can be made small and stability improved by making small or C large.  If c is small S 1 + β, i.e., stability is port This collector to base bias is not satisfactory for transformer coupled amplifier.  6
7 Self bias or Potential Divider ias:   equired base bias is obtained from the power supply through potential divider 1 & 2.  In this circuit voltage across everse biases base emitter junction. Whenever there is increase in this collector circuit voltage across E increases causing base current to diverse which compensate the increase in collector current.  This circuit can be used with low collector resistance. 2Vcc V y applying thevenins theorem, the cut can be replaced and Equivalent Circuit:  Writing loop equation for the basic loop shown I C E I + V E + E (I +I C ) I + V E + I E + I C E I ( + E ) + V E + I C E Or I ( + E ) V V E  I C E Or di E di + c E Differencing wrt. Ic, di dv dve di + E di di di di ( ) C E C C C C di Or ( + ) 0 0 di  (1) c E E Stability Factor 7
8 1+ β S di 1 β dic DI Putting the value of from equation (1) DIC 1+ β 1+ β 1+ β S E E + + β 1 β 1+ β + E + E + E E E Dividing N & D by E + E ( 1+ β ) 1+ E E S (1 + β ) (2) + E + β E 1+ β + If E E β 0, S (1 + β ) β ( β ) β + If, S ( 1+ β ) ( 1+ β ) E E (3) So, (a) for smaller value of stability is better, but large power will be wasted in 1 & 2. S is independent of. (b) For fixed /E, S increases with β (see eqn. 2) i.e., stability decreases with increase in β. ias compensation a) Diode bias compensation I I D + I (I D is reverse saturation Current increases with temp.) When temperature increases, I C increases at the time, I D also increases, making I to educe and controlling I C. 8
9 b) Thermistor ias compensation:   T is having negative temp. Coefficient i.e., temperature T.T  When temperature increases T decreases thereby reducing base bias voltage & base current and hence collect to current. c) Sensistor ias compensation.  s is sensistor (resistance) having positive temperature coefficient.  When temp. s. V 2 iasing of FET Source selfias circuit: ase bias voltage ase current. Collector current controlled. This configuration can be used to bias JFET pr depletion mode MOS FET.  Voltage across S is used to reverse bias the gate as voltage across E is used for selfbias of C E amplifier.  elation of drain current, V GS, Vp is given by I DS I DSS (1 V GS /V P ) 2.  Since gate current in negligible, source resistance can be VGS found as S I D  9
10 iasing against device variation:  V GS V GG I DS. (Gate current is very small & V G is small)  V GS is always negative  There may be a change in the drain current I d, when even a device is changed  If a device change results in increase in I d, it leads to more voltage drop across S and V GS increases. So, I d will be reduced.  In this way the circuit takes care of device variations. FET as a voltage variable esistor:  ID  When V DS < V P V GS 0V Id α V DS, when V GS is constant. V GS 1V i.e., FET acts as a resistance. V GS 2V  In this region FET is used as a V GS 3V Voltage controlled resistor. Or Voltage variable resistor. Or Voltage dependant resistor. 0 V P V DS Application:  There many applications. Automatic gain control of F amplifier of a receiver is one of the applications. 10
11  FET is biased in such a way that when transistors conducts more, then the resistance offered by FET is more.  The causes more reverse bias to emitter base junction of transistor and it conducts less.  In this way Automatic gain control (AGS) is achieved. Q) Find out stability factor of the circuit given below: (May 2005) Stability factor of selfbiased Circuit given by: E E S ( 1+ β ) 1+ β + E k k Ω S ( ) Q2) For the circuit shown, determine the value of Ic and VCE. Assume VE 0.7V and β 100 (Sep.06) V V. 10 5k k 15 cc 2 in 1 2 ( ) th k k 3.33 k volts V th I + V E + I E E I + V E + (β+1)i E V th V E I ( +(β + 1) E ) V Or th VE I + β + 1 ( ) E 11
12 K I µ A I β. I 4888 µ A. C I I + I µ A E C Part (b) V CE? V CC I C C + V CE + I E E Or V CE V CC I C C I E E x 106 x x 106 x volts I C 4.89 ma V CE 2.64 Volts Q3) For the JFET shown in the circuit with the voltage divides bias as shown below. Calculate V G, V S, V D and V DS if V GS 2V. (Sep. 2006) Solution: VG V. 15 4k k 4 DD ( ) 3.75V Since gate circuit is negligible Voltage drop across G 0 V GS V G I d s.  2 V I d S I d S V Vs. Id 5.75/1k 5.75mA. Voltage drop across L I D x 103 x V V DS V DD I D 2 I D S volts V D V DD I D L V. 3Q) For the circuit shown, calculate V E, I E, Ic and Vc. Assume V E 0.7V. (Sep. 2006) Solution: V V E + V E or V E V V E V VE 3.3 I E 1mA 3.3k E 12
13 Since β is not given, assume Ic I E 1mA. V C V CC I C L 10 1 x 103 x 4.7 x volts 4 Q) In the circuit shown, if I C 2mA and V CE 3V, calculate 1 & 3 Solution: Ic 2mA I 0.02mA β 100 I I + I mA E C V I 2.02mA volts E E E V 2 VE + VE volts V I 0.161mA 2 10k V 1 V CC V volts V kΩ I + I ma ( ) V 3 V CC V E V CE ; V CE 3V V volts V k I 2mA Ω C (Sep. 2006) 5Q) Design a selfbias circuit for the following specifications. VCC 12V, VCE 2V, I C 4mA, h fc 80. (Sep. 2006) Solution: C I I 4mA / mA β I E I C + I ma Let V 4V. 2 4k and 1 8K k k 2667Ω V I + V E + V E Or V E V I V E x 103 x volts VE E 7.82 I E 4.05mA Ω V CC V C + V CE + V E (O) V C V CC V CE  V E volts 13
14 VC c I C ma 1708Ω. 1 8k, 2 4k, c 1708Ω and c 782. ut resistor of 1708Ω and 782Ω are not available commercially. We have to choose commercially available resistors, which are nearest to these values. Numerical of Unit III Question ank 1 Q) A volts (rms) ideal transformer is used with a FW with diodes having fwd drop of 1 volt. The load resistance in 100Ω and capacitor of 10,000 µf is used on filter. Calculate the Dc load current and voltage. (JNTU 2005) Solution:  I DC VDC Vm where f is power line frequency. C in farads. 4 fc Vrms 15V, Assume voltage drop (rms) across diode as 1V. Vrms across load 14V Idc 4170 Idc V dc V m C 10, I ; 19.8 (or) I ; Amp dc dc V 19.8 Volts. dc Vm Vrms volts. 2 Q) A FW is used to supply power to a 2000Ω load, choke of 20H and capacitor of 16µf are available. Compute ripple factor using filter 1 (i) one inductor (ii) one capacitor (iii) single L type. Solution: L 2000Ω; C 16µf; L 20H. i) One Inductor Filter L r L (ii) One capacitor filter: r CL (iii) Single LC Type Filter 14
15 r LC (iv) π Selection r CC1L1 L Filter in the Order of Merit: a) Capacitor Filter (b) Inductor Filter c) L Section (d) π Section. 3 Q) Design a full wave rectifier with an LC filter to provide 9V DC at 100mA with a max ripple of 2%. Given line frequency f 60Hz. (JNTU 2000) Solution:  Given V DC 9V, f 60Hz. I L 100mA, r 2% 0.02 To find: L, C. r 0.83 when f 60 Hz. (1) (1) Else r wc 2 wl. Where L C L / Or 0.83 LC 41.5 (2) 0.02 Critical Inductance (value of Inductance for which diode conducts continuously) L VDC 9 L C.; L I DC 100mA Lc (2) 41.5 C µ f Transformer rating Vrms? Diode ratings Piv Vm current rating load current L 796mH C 521µf 4 Q) A FW operating at 50 Hz i.e., to provide DC current of 50mA at 30V with a 80µf, C type filter. Calculate (i) V m the peak secondary voltage of the transformer (ii) atio of surge to mean currents of diode (iii) The ripple factor of the output. (JNTU 2002) 15
16 Solution:  Given f 50 Hz, C 80µf I DC 50mA To find V m? ratio of surge to mean current V DC 30V. Part (i) V m? V DC V m. Or V m V DC / / volts. Part ii atio of surge to mean current X X Surge Current It is the current flowing through the diode, when the power supply is just switched on i.e., at time t 0+. At time t 0+. Voltage across capacitor will be zero X X X V V S C Current through the diode at any time d + S VS max Vm When Vc 0, Id will be max d + S d + S This is called surge current. VS Vdc Mean diode current Id + d V ( d + m s ) atio of surge current to mean current ( ) V m V m V DC S + V V d s m dc Note: Designer must cater for 3 times the required average current. Part III : 2410 ipple factor r CL f 60 Hz. Or 1 ipple factor r 4 3 fcl Vdc 300V 2 L 30V Idc 50mA r
17 5 Q) For a FW circuit AC voltage input to transformer primary is 115V. Transformer secondary voltage is 50V, L 25Ω. Determine i) Peak DC component, MS and AC component of load voltage ii) Peak DC component, MS and AC component of load current. (June 2002) Solution: Given Vrms 50V, to find V m, V r, I m, I r. V L 25Ω Vm Vdc r 2 Part (i) Vm Vms orvm 2; Vms 2, Volts V V r 2 r, r of FW (without filter) 0.48 Vdc V dc V m 0.637x volts Vr γ, Vdc 0.48 x volts Peak DC component VDC + ipple voltage volts γ peak 66.6 V rms 47 Volts 2 2 Part II Vm 70.7 Im Amps. 25 L Vr 21.6 Ir Amps. L 25 Peak DC current component 66.6/ Amps. uns DC current component 47/ Amps. 6 Q) Calculate ripple factor of capacitor filter with peak rectified voltage of 20V and C 50 µf and I DC 50mA. (June 2004) Solution:  Vm 20V, Idc 50mA, C 50µf. V DC Vm 20V V DC Idc Vm 4 fc Suppose f 50Hz, Then V DC V r
18 volts 200 VDC L 300Ω Idc 50mA r 4 3 fc L Photo Transistor: Phototransistor is a JT for which no base bias is given. When light falls on the junction base current flows and transistor conducts. Ic(mA) Symbol ase 3.0 current H 1.25 mw/cm 2 I µa Vcc(V)  Collector current does not vary much with Vcc  Collector current increases with light intensity. adiation flux Density H(mw/in 2 ) Advantages of photo diode.  Will produce I C much higher (β times) I C (by photo diode) Applications: Capt. isolators are used to isolate input source and load i.e., high isolation logic gates etc., 18
19 Numerical of Question ank Unit IV 1 Q) In a C connection current amplification factor is 0.9. If emitter current is 1mA, determine the value of base current. Given α 0.9 I? I E 1 ma. Solution: α Ic/IE or IC α. I E 0.9 x 1 0.9mA I I E Ic ma. 2 Q) For a transistor collector current is 20mA and current gain factor is 50. Determine emitter current. (May 2000) Given Ic 20mA IE? β 50 Solution: Ic Ic 20 β Or I ma 0.4 ma. I β 50 IE I C + I ma. 3 Q) In a transistor collector current is 0.98 ma and base current is 20µA. Determine the value of i) Emitter current (ii) Current amplification factor iii) Current gain factor (May 2000) Given I C 0.98mA To find: I E? I 20µA β? α? Solution:  I E Ic + I 0.98 ma + 20µA 980µA + 20µA 1000µA Ic 980 β µ A 49 I 20 Ic 980 α µ A 0.98 IE Q) A JT has I 10µA, α 0.99 and I co 1µA. What is the collector current. Solution: Ic βi + (β + 1) Ico; α β 99 1 α Ic (99 x x 1)µA µA 1.09 ma. 19
20 5 Q) The readings obtained from a JFET are as follows:  Drain to source voltage (volts) Gate to source voltage (volts) Drain current Id (ma) Determine (i) AC drain resistance (ii) Trans. Conductance (iii) Amplification Factor SOLUTION: (i) VDS Ac Drain esistance d / VGS constant V GS constant ID 12 5( Volts) ( ma) kΩ (ii) Trans conductance Id gm VGS VDS constant mA 70 m 0 ( 0.25) m (iii) Amplification factor µ g m. d 2.8 x 103 x Q) An SC is used as a switch to supply an inductive load of L 20H and negligible resistance from a DC source of 100V. If the latching current of SC is 100mA, find the min. pulse width of trigger pulse. i Solution: V VSC + VL + V VSC 0 + VL + 0 di V L VL 20 dt. L dt di 100V V Integrating both sides V 0Ω L 20 3 t. i sec. V 100 Minimum pulse width required is 0.02 sec. 20
21 NUMEICAL OF QUESTION ANK. 1 Q) An NPN transistor used in selfbias CE amplifier has a value of β 49 at temperature of 25 c. The circuit has 1 90kΩ. Vcc and c are adjusted to establish Ic 2mA. Calculate stability factor. (JNTU 2001) Solution: Stability factor S E 1+ β + E ( β ) β & E are given: k; k E 1k 1 2 ( )( ) ( + + ) S Q) In the selfbiased CE amplifier c 4kΩ, 1 90kΩ, 2 10kΩ, 45 and VE 0.6V. Compute stability factor for E (i)1kω (ii) 1.5KΩ (iii) 1.8kΩ. (Dec. 2003) Solution:  ( 1+ β ) 1+ E Stability factor of selfbias circuit S 1+ β + E Given, β 45, E k Case (i) Case (ii) Case (iii) 1 2 ( + )( + ) E 1KΩ S E 1 K 9k ( 1+ 45)( 1+ 6) E 1.5 k, 6 S 6.19 KE 1.5 k k ( 1+ 45)( 1+ 5) E 1.8 k, 5 S 5.41 E 1.8 k
22 IAS CONPENSATION: 1 Q) Explain ias compensation using sensistors. Ic (β + 1) ICO + βi. For correct operation of transistor as an amplifier collector current should be independent of temperature variations. ut when temperature increases ICO increases. So to keep the collector current Ic constant, we must reduce current I to compensate increase in ICO. The technique used is called ias compensation. +VCE 1. Sensistor compensation 1 s E As shown in the diagram s can be Connected across s (or it can be Connected across E). 2 E Sensistor (s) in a positive temperature Coefficient resistance i.e., value of s increases with rise in temperature. So, when temperature increases resistance offered by s (sensistor) increases. So, parallel combination of s and 1 with also offer more resistance. More voltage will be dropped across than and less voltage is applied to base. This reduces the base emitter bias voltage resulting in reduction of base current. In this way sensistor reduces the base current to compensate increase in ICO due to rise in temperature. 1 b) In the circuit shown, if Ic 2mA and VCE 3V, calculate 1 and 3. (May 07, Aug. 06, 07) + Vcc 15V Solution: 1 3 I+I Ic I 2 10kΩ 4 500Ω 22
23 3 Ic 2 10 I 0.02mA β 100 IE Ic + I mA VE IC E 2.02mA x volts V2 VE + VE volts V I ma 10k 2 V1 VCC V volts V K I + I ma ( ) V3 VCC VE VCE volts V k Ic 2mA Ω 1 c) Compare JT, JFET and MOS FET in all respects. (Aug 06, 07) S.No. JT JFET MOS FET 1 Types NPN, PNP, ipolar Nch JET, Pch Enhancement & JFET, Unipolar depletion type, Unipolar 2 Current oth majority Only majority Only majority charge &minority charge charge carriers are carriers are used. carriers are used used 3 Input impedance Low (kω) High (100 MΩ) Very high (10 15 Ω) 4 Control Current controlled Voltage controlled Voltage controlled device input current device. Input device. controls output voltage controls current output current 5 Fabrication Difficult Easy Easy 6 Handling Easy No, preached Easy Difficult, special required precautions to be taken 7 Power High Low Very low Dissipation 8 Lifetime Less More Less 9 Switching speed Less High High 4 Q) Explain in detail about Thermal runaway and Thermal resistance. (May 07) Thermal un away: 23
24 Ic βi + (β+1) Ico. Leakage current Ico increases with temperature and β also increases with rise in temperature. Ico doubles with every 10 c rise in temperature. Therefore collector current also increases with temperature. More collectors current in turn will give rise to more temperature at the junction. This problem of selfheating is called Thermal run away and may result in damaging the transistor. Thermal esistance (P 288 MMH) The steady state temperature rise at the collector junction is proportional to the power dissipated at the junction. T T J T A k P D Where T rise in temperature T J Temperature at junction T A Ambient temperature P D Power dissipated K Proportionality constant, called Thermal resistance. The value of Thermal resistance depends on size of transistor, on convection or radiation to the surroundings, on forced air cooling and on Thermal connection of the device to metallic chassis or heat sink. The value of Thermal resistance varies from 0.2 c/w for a high power transistor with efficient heat sink to 1000 c / w for a low power transistor in free air. 4 b) Q) For the circuit shown in figure, determine I E, V C and V CE. Assume VE 0.7V. (May 2007) V EE  8V Si c 1.8kΩ V CC 10V β
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