MOS Transistor Theory


 Spencer Hutchinson
 2 years ago
 Views:
Transcription
1 MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors as ideal switches An ON transistor passes a finite amount of current Depends on terminal voltages Derive currentvoltage (IV) relationships Transistor gate, source, drain all have capacitance I = C (ΔV/Δt) > Δt = (C/I) ΔV Capacitance and current determine speed Also explore what a degraded level really means EE 261 Krish Chakrabarty 2 1
2 MOS Transistor Theory Study conducting channel between source and drain Modulated by voltage applied to the gate (voltagecontrolled device) nmos transistor: majority carriers are electrons (greater mobility), psubstrate doped (positively doped) pmos transistor: majority carriers are holes (less mobility), nsubstrate (negatively doped) EE 261 Krish Chakrabarty 3 Terminal Voltages Mode of operation depends on V g, V d, V s + + V gs = V g V V gs s  V gd = V g V d V V ds = V d V s = V gs V s  gd V + ds Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence V ds 0 nmos body is grounded. First assume source is 0 too. Three regions of operation Cutoff Linear Saturation V g V gd  V d EE 261 Krish Chakrabarty 4 2
3 Source Gate Biasing Gate SiO 2 Drain n + Channel n E psubstrate V gs =0: no current flows from source to drain (insulated by two reverse biased pn junctions V gs >0: electric field created across substrate V SS (Gnd) Electrons accumulate under gate: region changes from ptype to ntype Conduction path between source and drain EE 261 Krish Chakrabarty 5 psubstrate nmos Device Behavior Polysilicon gate Oxide insulator Inversion Region (ntype) Depletion region Depletion region V gs << V t Accumulation mode V gs = V t Depletion mode V gs > V t Inversion mode Enhancementmode transistor: Conducts when gate bias V gs > V t Depletionmode transistor: Conducts when gate bias is zero EE 261 Krish Chakrabarty 6 3
4 nmos Cutoff No channel I ds = 0 V gs = g +  V gd s n+ n+ ptype body b d EE 261 Krish Chakrabarty 7 nmos Linear Channel forms Current flows from d to s e  from s to d I ds increases with V ds Similar to linear resistor V gs > V t +  s g +  V gd = V gs n+ n+ V ds = 0 ptype body b d V gs > V t +  s g +  V gs > V gd > V t d I ds n+ n+ 0 < V ds < V gs V t ptype body b EE 261 Krish Chakrabarty 8 4
5 nmos Saturation Channel pinches off I ds independent of V ds We say current saturates Similar to current source V gs > V t +  g +  V gd < V t s d I ds n+ n+ V ds > V gs V t ptype body b EE 261 Krish Chakrabarty 9 IV Characteristics In linear region, I ds depends on How much charge is in the channel? How fast is the charge moving? EE 261 Krish Chakrabarty 10 5
6 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = gate t ox polysilicon gate n+ L n+ ptype body W SiO2 gate oxide (good insulator, ε ox = 3.9) V g + + source V gs C g V gd drain   channel n+  + n+ V s V ds ptype body V d EE 261 Krish Chakrabarty 11 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = CV C = t ox polysilicon gate n+ L n+ ptype body W SiO2 gate oxide (good insulator, ε ox = 3.9) V gs gate + V g + source C g V gd drain   channel n+  + n+ V s V ds ptype body V d EE 261 Krish Chakrabarty 12 6
7 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = CV C = C g = ε ox WL/t ox = C ox WL V = t ox polysilicon gate n+ L n+ ptype body W SiO2 gate oxide (good insulator, ε ox = 3.9) V gs gate + V g + source C g V gd drain   channel n+  + n+ V s C ox = ε ox / t ox V ds ptype body V d EE 261 Krish Chakrabarty 13 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate oxide channel Q channel = CV C = C g = ε ox WL/t ox = C ox WL C V = V gc V t = (V gs V ds /2) V ox = ε ox / t ox t gate t ox polysilicon gate n+ L n+ ptype body W SiO2 gate oxide (good insulator, ε ox = 3.9) V g + + source V gs C g V gd drain   channel n+  + n+ V s V ds ptype body V d EE 261 Krish Chakrabarty 14 7
8 Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral Efield between source and drain v = EE 261 Krish Chakrabarty 15 Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral Efield between source and drain v = μe μ called mobility E = EE 261 Krish Chakrabarty 16 8
9 Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral Efield between source and drain v = μe μ called mobility E = V ds /L Time for carrier to cross channel: t = EE 261 Krish Chakrabarty 17 Carrier velocity Charge is carried by e Carrier velocity v proportional to lateral Efield between source and drain v = μe μ called mobility E = V ds /L Time for carrier to cross channel: t = L / v EE 261 Krish Chakrabarty 18 9
10 nmos Linear IV Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross I = ds EE 261 Krish Chakrabarty 19 nmos Linear IV Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross Qchannel Ids = t = EE 261 Krish Chakrabarty 20 10
11 nmos Linear IV Now we know I ds How much charge Q channel is in the channel How much time t each carrier takes to cross Qchannel = t W V = μc V V V L V = β V ds gs V t V 2 ds ds ox gs t 2 ds W β = μcox L EE 261 Krish Chakrabarty 21 nmos Saturation IV If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t Now drain voltage no longer increases current I ds = EE 261 Krish Chakrabarty 22 11
12 nmos Saturation IV If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t Now drain voltage no longer increases current V I dsat ds = β Vgs Vt V 2 dsat EE 261 Krish Chakrabarty 23 nmos Saturation IV If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t Now drain voltage no longer increases current V I dsat ds = β Vgs V t V 2 dsat β = ( V ) 2 gs Vt 2 EE 261 Krish Chakrabarty 24 12
13 nmos IV Summary Shockley 1 st order transistor models 0 Vgs < Vt V I = β V V ds V V V 2 < β ( V V ) 2 V > V 2 ds gs t ds ds dsat gs t ds dsat cutoff linear saturation EE 261 Krish Chakrabarty 25 CurrentVoltage Relations EE 261 Krish Chakrabarty 26 13
14 CurrentVoltage Relations k n : transconductance of transistor W : widthtolength ratio L As W increases, more carriers available to conduct current As L increases, V ds diminishes in effect (more voltage drop). Takes longer to push carriers across the transistor, reducing current flow EE 261 Krish Chakrabarty 27 For a 0.6 μm process From AMI Semiconductor t ox = 100 Å μ = 350 cm 2 /V*s V t = 0.7 V Plot I ds vs. V ds V gs = 0, 1, 2, 3, 4, 5 Use W/L = 4/2 λ Example A/ V L L L 14 W W W ox 8 β = μc = ( ) = μ I ds (ma) V gs = 2 V 0 gs = V ds V gs = 5 V gs = 4 V gs = 3 EE 261 Krish Chakrabarty 28 14
15 pmos IV All dopings and voltages are inverted for pmos Mobility μ p is determined by holes Typically 23x lower than that of electrons μ n 120 cm 2 /V*s in AMI 0.6 μm process Thus pmos must be wider to provide same current In this class, assume μ n / μ p = 2 to 3 EE 261 Krish Chakrabarty 29 Capacitance Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important Creates channel charge necessary for operation Source and drain have capacitance to body Across reversebiased diodes Called diffusion capacitance because it is associated with source/drain diffusion EE 261 Krish Chakrabarty 30 15
16 Gate Capacitance Approximate channel as connected to source C gs = ε ox WL/t ox = C ox WL = C permicron W C permicron is typically about 2 ff/μm polysilicon gate W t ox n+ L n+ ptype body SiO2 gate oxide (good insulator, ε ox = 3.9ε 0 ) EE 261 Krish Chakrabarty 31 The Gate Capacitance EE 261 Krish Chakrabarty 32 16
17 Diffusion Capacitance C sb, C db Undesirable, called parasitic capacitance Capacitance depends on area and perimeter Use small diffusion nodes Comparable to C g for contacted diff ½C g for uncontacted Varies with process EE 261 Krish Chakrabarty 33 Diffusion Capacitance EE 261 Krish Chakrabarty 34 17
18 G Parasitic Resistances Polysilicon gate L D Drain contact V GS,eff S R S R D D W Drain R S = (L S /W)R + R C R D = (L D /W)R + R C R C : contact resistance R : sheet resistance per square of drainsource diffusion EE 261 Krish Chakrabarty 35 Body Effect Many MOS devices on a common substrate Substrate voltage of all devices are normally equal But several devices may be connected in series Increase in sourcetosubstrate voltage as we proceed vertically along the chain V 12 g2 g1 V11 d2 s2 d1 s1 V sb2 = 0 V sb1 = 0 Net effect: slight increase in threshold voltage V t, V t2 >V t1 EE 261 Krish Chakrabarty 36 18
19 Pass Transistors We have assumed source is grounded What if source > 0? e.g. pass transistor passing EE 261 Krish Chakrabarty 37 Pass Transistors We have assumed source is grounded What if source > 0? e.g. pass transistor passing V g = If V s > V t, V gs < V t Hence transistor would turn itself off nmos pass transistors pull no higher than V tn Called a degraded 1 Approach degraded value slowly (low I ds ) pmos pass transistors pull no lower than V tp EE 261 Krish Chakrabarty 38 19
20 Pass Transistor Ckts V SS EE 261 Krish Chakrabarty 39 Pass Transistor Ckts Vs = V tn V DD Vtn VDDVtn V tn V s = V tp V tn 2V tn V SS EE 261 Krish Chakrabarty 40 20
21 Effective Resistance Shockley models have limited value Not accurate enough for modern transistors Too complicated for much hand analysis Simplification: treat transistor as resistor Replace I ds (V ds, V gs ) with effective resistance R I ds = V ds /R R averaged across switching of digital gate Too inaccurate to predict current at any given time But good enough to predict RC delay EE 261 Krish Chakrabarty 41 RC Delay Model Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nmos has resistance R, capacitance C Unit pmos has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width g d k s g d R/k kc s kc kc g d k s g s kc 2R/k kc kc d EE 261 Krish Chakrabarty 42 21
22 RC Values Capacitance C = C g = C s = C d = 2 ff/μm of gate width Values similar across many processes Resistance R 6 KΩ in 0.6um process Improves with shorter channel lengths Unit transistors May refer to minimum contacted device (4/2 λ) Or maybe 1 μm wide device Doesn t matter as long as you are consistent EE 261 Krish Chakrabarty 43 Activity 1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change EE 261 Krish Chakrabarty 44 22
23 Activity 1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change EE 261 Krish Chakrabarty 45 DC Response DC Response: vs. for a gate Ex: Inverter When = 0 > = When = > = 0 In between, depends on transistor size and current By KCL, must settle such that I dsn = I dsp We could solve equations But graphical solution gives more insight I dsp I dsn EE 261 Krish Chakrabarty 46 23
24 Transistor Operation Current depends on region of transistor behavior For what and are nmos and pmos in Cutoff? Linear? Saturation? EE 261 Krish Chakrabarty 47 Cutoff V gsn < nmos Operation Linear Saturated V gsn > V gsn > V dsn < V dsn > I dsp I dsn EE 261 Krish Chakrabarty 48 24
25 Cutoff nmos Operation Linear Saturated V gsn < V tn V gsn > V tn V gsn > V tn V dsn < V gsn V tn V dsn > V gsn V tn I dsp I dsn EE 261 Krish Chakrabarty 49 Cutoff nmos Operation Linear Saturated V gsn < V tn V gsn > V tn V gsn > V tn V dsn < V gsn V tn V dsn > V gsn V tn V gsn = I dsp V dsn = I dsn EE 261 Krish Chakrabarty 50 25
26 Cutoff nmos Operation Linear Saturated V gsn < V tn < V tn V gsn > V tn > V tn V dsn < V gsn V tn < V tn V gsn > V tn > V tn V dsn > V gsn V tn > V tn V gsn = I dsp V dsn = I dsn EE 261 Krish Chakrabarty 51 Cutoff V gsp > pmos Operation Linear Saturated V gsp < V gsp < V dsp > V dsp < I dsp I dsn EE 261 Krish Chakrabarty 52 26
27 Cutoff pmos Operation Linear Saturated V gsp > V tp V gsp < V tp V gsp < V tp V dsp > V gsp V tp V dsp < V gsp V tp I dsp I dsn EE 261 Krish Chakrabarty 53 Cutoff pmos Operation Linear Saturated V gsp > V tp V gsp < V tp V gsp < V tp V dsp > V gsp V tp V dsp < V gsp V tp V gsp =  V tp < 0 V dsp =  I dsp I dsn EE 261 Krish Chakrabarty 54 27
28 Cutoff pmos Operation Linear Saturated V gsp > V tp > + V tp V gsp < V tp < + V tp V dsp > V gsp V tp > V tp V gsp < V tp < + V tp V dsp < V gsp V tp < V tp V gsp =  V tp < 0 V dsp =  I dsp I dsn EE 261 Krish Chakrabarty 55 IV Characteristics Make pmos wider than nmos such that β n = β p V gsn5 I dsn V gsn4 V gsn3 V dsp V gsp1 V gsp20 V gsn2 V gsn1 V gsp3 V dsn V gsp4 I dsp V gsp5 EE 261 Krish Chakrabarty 56 28
29 A B DC Transfer Curve Transcribe points onto vs. plot C 0 D E V tn /2 +V tp EE 261 Krish Chakrabarty 57 Operating Regions Revisit transistor operating regions Region A B C D E nmos pmos A B 0 C D E V tn /2 +V tp EE 261 Krish Chakrabarty 58 29
30 Operating Regions Revisit transistor operating regions Region A B C D E nmos Cutoff Saturation Saturation Linear Linear pmos Linear Linear Saturation Saturation Cutoff A B 0 C D E V tn /2 +V tp EE 261 Krish Chakrabarty 59 Beta Ratio If β p / β n 1, switching point will move from /2 Called skewed gate Other gates: collapse into equivalent inverter β p 0.1 β = n β p 10 β = n EE 261 Krish Chakrabarty 60 30
31 Noise Margins How much noise can a gate input see before it does not recognize the input? Logical High Output Range Output Characteristics V OH NM H V IH V IL Input Characteristics Indeterminate Region Logical High Input Range Logical Low Output Range V OL NM L GND Logical Low Input Range EE 261 Krish Chakrabarty 61 Logic Levels To maximize noise margins, select logic levels at β p /β n > 1 0 EE 261 Krish Chakrabarty 62 31
32 Logic Levels To maximize noise margins, select logic levels at unity gain point of DC transfer characteristic Unity Gain Points Slope = 1 V OH β p /β n > 1 V OL 0 V tn V IL V IH  V tp EE 261 Krish Chakrabarty 63 32
Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline
Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and
More informationMOS Transistor IV Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor IV Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationLecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos IV Characteristics pmos IV Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded
More informationEE5780 Advanced VLSI CAD
EE5780 Advanced VLSI CAD Lecture 4 DC and Transient Responses, Circuit Delays Zhuo Feng 4.1 Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal IV Characteristics 3. Nonideal IV Effects 4. CV Characteristics 5. DC Transfer Characteristics 6. Switchlevel RC Delay Models MOS
More informationDC and Transient. Courtesy of Dr. Daehyun Dr. Dr. Shmuel and Dr.
DC and Transient Courtesy of Dr. Daehyun Lim@WSU, Dr. Harris@HMC, Dr. Shmuel Wimer@BIU and Dr. Choi@PSU http://csce.uark.edu +1 (479) 575604 yrpeng@uark.edu Pass Transistors We have assumed source is
More informationLecture 6: DC & Transient Response
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins
More informationDC and Transient Responses (i.e. delay) (some comments on power too!)
DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02  CMOS Transistor Theory & the Effects of Scaling
More informationLecture 5: CMOS Transistor Theory
Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos IV Characteristics
More informationDC & Transient Responses
ECEN454 Digital Integrated Circuit Design DC & Transient Responses ECEN 454 DC Response DC Response: vs. for a gate Ex: Inverter When = > = When = > = In between, depends on transistor size and current
More informationChapter 2 CMOS Transistor Theory. JinFu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 2 CMOS Transistor Theory JinFu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor JinFu Li, EE,
More informationLecture 4: DC & Transient Response
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide
More informationVLSI Design The MOS Transistor
VLSI Design The MOS Transistor Frank Sill Torres Universidade Federal de Minas Gerais (UFMG), Brazil VLSI Design: CMOS Technology 1 Outline Introduction MOS Capacitor nmos IV Characteristics pmos IV
More informationMOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor
MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET Calculation of t and Important 2 nd Order Effects SmallSignal Signal MOSFET Model Summary Material from: CMOS LSI Design By Weste
More information5. CMOS Gate Characteristics CS755
5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More informationLecture 12 CMOS Delay & Transient Response
EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology
More informationEEE 421 VLSI Circuits
EEE 421 CMOS Properties Full railtorail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady
More informationENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor NChannel MOSFET Built on ptype
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationCS/EE Ntype Transistor
CS/EE 6710 MOS Transistor Models Electrical Effects Propagation Delay Ntype Transistor D + G Vds i electrons +Vgs S  1 Another Cutaway View Thanks to National Central University for Some images Vgs Forms
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NORgate C = NOT (A or B)
1 Introduction to TransistorLevel Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationPractice 3: Semiconductors
Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given
More informationChapter 4 FieldEffect Transistors
Chapter 4 FieldEffect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 41 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationVLSI Design and Simulation
VLSI Design and Simulation Performance Characterization Topics Performance Characterization Resistance Estimation Capacitance Estimation Inductance Estimation Performance Characterization Inverter Voltage
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationEE105  Fall 2006 Microelectronic Devices and Circuits
EE105  Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM
More informationEE105  Fall 2005 Microelectronic Devices and Circuits
EE105  Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture
More informationChapter 2 MOS Transistor theory
Chapter MOS Transistor theory.1 Introduction An MOS transistor is a majoritycarrier device, which the current a conductg channel between the source and the dra is modulated by a voltage applied to the
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationMOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA
MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the FieldEffect Transistor! Julius Lilienfeld filed a patent describing
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
More informationLecture 12: MOS Capacitors, transistors. Context
Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V
More informationLecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I curve (SquareLaw Model)
More informationECE 497 JS Lecture  12 Device Technologies
ECE 497 JS Lecture  12 Device Technologies Spring 2004 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More informationToday s lecture. EE141 Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
 Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
More informationDigital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationMOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
More informationThe Devices. Jan M. Rabaey
The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models
More informationEE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing
EE115C Winter 2017 Digital Electronic Circuits Lecture 3: MOS RC Model, CMOS Manufacturing Agenda MOS Transistor: RC Model (pp. 104113) S R on D CMOS Manufacturing Process (pp. 3646) S S C GS G G C GD
More informationEEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationCMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More informationLecture 11: MOS Transistor
Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Crosssection and layout
More informationThe Devices: MOS Transistors
The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, AddisonWesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationEEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins,
More informationThe Devices. Devices
The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ FieldOxyde (SiO 2 ) psubstrate p+ stopper Bulk Contact CROSSSECTION of NMOS Transistor CrossSection of CMOS Technology MOS transistors
More informationStep 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since
Step 1. Finding V M Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since V DSn = V M  0 > V M  V Tn V SDp = V DD  V M = (V DD  V M ) V Tp Equate drain
More informationENEE 359a Digital VLSI Design
SLIDE 1 ENEE 359a Digital VLSI Design & Logical Effort Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay
More informationLecture 11 VTCs and Delay. No lab today, Mon., Tues. Labs restart next week. Midterm #1 Tues. Oct. 7 th, 6:308:00pm in 105 Northgate
EE4Fall 2008 Digital Integrated Circuits Lecture VTCs and Delay Lecture # Announcements No lab today, Mon., Tues. Labs restart next week Midterm # Tues. Oct. 7 th, 6:308:00pm in 05 Northgate Exam is
More informationand V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
More informationLecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pullup The inverter NMOS inverter with currentsource pullup Complementary MOS (CMOS) inverter Static analysis
More informationTopic 4. The CMOS Inverter
Topic 4 The CMOS Inverter Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ Email: p.cheung@ic.ac.uk Topic 41 Noise in Digital Integrated
More informationSECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University
NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula
More informationECE 342 Solid State Devices & Circuits 4. CMOS
ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. SchuttAine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ualwell TrenchIsolated
More informationDigital Integrated Circuits
Chapter 6 The CMOS Inverter 1 Contents Introduction (MOST models) 0, 1 st, 2 nd order The CMOS inverter : The static behavior: o DC transfer characteristics, o Shortcircuit current The CMOS inverter :
More informationMOSFET and CMOS Gate. Copy Right by Wentai Liu
MOSFET and CMOS Gate CMOS Inverter DC Analysis  Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max
More informationFIELDEFFECT TRANSISTORS
FIELEFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancementtype NMOS transistor 3 IV characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation
More informationEE 330 Lecture 17. MOSFET Modeling CMOS Process Flow
EE 330 Lecture 17 MOSFET Modeling CMOS Process Flow Review from Last Lecture Limitations of Existing Models V DD V OUT V OUT V DD?? V IN V OUT V IN V IN V DD SwitchLevel Models V DD Simple squarelaw
More informationEE 560 MOS TRANSISTOR THEORY
1 EE 560 MOS TRANSISTOR THEORY PART 1 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE ptype doped Si (N A = 10 15 to 10 16 cm 3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM:
More informationHW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7
HW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7 2 What do digital IC designers need to know? 5 EE4 EECS4 6 3 0< V GS  V T < V DS Pinchoff 7 For (V GS V T )
More informationFundamentals of the Metal Oxide Semiconductor FieldEffect Transistor
Triode Working FET Fundamentals of the Metal Oxide Semiconductor FieldEffect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the
More informationNanoscale CMOS Design Issues
Nanoscale CMOS Design Issues Jaydeep P. Kulkarni Assistant Professor, ECE Department The University of Texas at Austin jaydeep@austin.utexas.edu Fall, 2017, VLSI1 Class Transistor IV Review Agenda Nonideal
More informationEE5311 Digital IC Design
EE5311 Digital IC Design Module 1  The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM
More information4.10 The CMOS Digital Logic Inverter
11/11/2004 section 4_10 The CMOS Digital Inverter blank.doc 1/1 4.10 The CMOS Digital Logic Inverter Reading Assignment: pp. 336346 Complementary MOSFET (CMOS) is the predominant technology for constructing
More informationMOSFET Physics: The Long Channel Approximation
MOSFET Physics: The ong Channel Approximation A basic nchannel MOSFET (Figure 1) consists of two heavilydoped ntype regions, the Source and Drain, that comprise the main terminals of the device. The
More informationMicroelectronics Part 1: Main CMOS circuits design rules
GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! medamine.miled@polymtl.ca!
More informationECE321 Electronics I
ECE31 Electronics Lecture 1: CMOS nverter: Noise Margin & Delay Model Payman ZarkeshHa Office: ECE Bldg. 30B Office hours: Tuesday :003:00PM or by appointment Email: payman@ece.unm.edu Slide: 1 CMOS
More informationLecture 23: Negative Resistance Osc, Differential Osc, and VCOs
EECS 142 Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California,
More informationEE 330 Lecture 16. MOSFET Modeling CMOS Process Flow
EE 330 Lecture 16 MOSFET Modeling CMOS Process Flow Model Extensions 300 Id 250 200 150 100 50 300 0 0 1 2 3 4 5 Vds Existing Model 250 200 Id 150 100 50 Slope is not 0 0 0 1 2 3 4 Actual Device Vds Model
More informationReview of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model
Content MOS Devices and Switching Circuits Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model A Cantoni 20092013 Digital Switching 1 Content MOS
More informationCHAPTER 5 MOS FIELDEFFECT TRANSISTORS
CHAPTER 5 MOS FIELDEFFECT TRANSISTORS 5.1 The MOS capacitor 5.2 The enhancementtype NMOS transistor 5.3 IV characteristics of enhancement mode MOSFETS 5.4 The PMOS transistor and CMOS technology 5.5
More informationVLSI Design and Simulation
VLSI Design and Simulation CMOS Inverters Topics Inverter VTC Noise Margin Static Load Inverters CMOS Inverter FirstOrder DC Analysis R p V OL = 0 V OH = R n =0 = CMOS Inverter: Transient Response R p
More informationLecture 12: MOSFET Devices
Lecture 12: MOSFET Devices GuYeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br
More informationUniversity of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA
University of Pennsylvania Department of Electrical Engineering ESE 570 Midterm Exam March 4, 03 FORMULAS AND DATA. PHYSICAL CONSTANTS: n i = intrinsic concentration undoped) silicon =.45 x 0 0 cm 3 @
More informationLecture 13 MOSFET as an amplifier with an introduction to MOSFET smallsignal model and smallsignal schematics. Lena Peterson
Lecture 13 MOSFET as an amplifier with an introduction to MOSFET smallsignal model and smallsignal schematics Lena Peterson 20151013 Outline (1) Why is the CMOS inverter gain not infinite? Largesignal
More informationECEN474/704: (Analog) VLSI Circuit Design Spring 2018
ECEN474/704: (Analog) SI Circuit Design Spring 2018 ecture 2: MOS ransistor Modeling Sam Palermo Analog & MixedSignal Center exas A&M University Announcements If you haven t already, turn in your 0.18um
More informationCMOS Technology for Computer Architects
CMOS Technology for Computer Architects Recap Technology Trends Lecture 2: Transistor Inverter Iakovos Mavroidis Giorgos Passas Manolis Katevenis FORTHICS (University of Crete) 1 2 Recap Threshold Voltage
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar
More informationEE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors
EE 330 Lecture 16 Devices in Semiconductor Processes MOS Transistors Review from Last Time Model Summary I D I V DS V S I B V BS = 0 0 VS VT W VDS ID = μcox VS VT VDS VS V VDS VS VT L T < W μc ( V V )
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full railtorail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power
More information! PN Junction. ! MOS Transistor Topology. ! Threshold. ! Operating Regions. " Resistive. " Saturation. " Subthreshold (next class)
ESE370: ircuitlevel Modeling, Design, and Optimization for Digital Systems Lec 7: September 20, 2017 MOS Transistor Operating Regions Part 1 Today! PN Junction! MOS Transistor Topology! Threshold! Operating
More informationUsing MOS Models. C.K. Ken Yang UCLA Courtesy of MAH EE 215B
Using MOS Models C.K. Ken Yang UCLA yangck@ucla.edu Courtesy of MAH 1 Overview Reading Rabaey 5.4 W&H 4.2 Background In the past two lectures we have reviewed the iv and CV curves for MOS devices, both
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!
More informationVLSI Design I; A. Milenkovic 1
Course Administration CPE/EE 47, CPE 57 SI Design I 0: IC Manufacturing & MOS Transistor Theory Department of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic
More informationLecture 04 Review of MOSFET
ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D
More information