Vidyalankar S.E. Sem. III [EXTC] Analog Electronics - I Prelim Question Paper Solution

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1 . (a) S.E. Sem. [EXTC] Analog Electronics - Prelim Question Paper Solution Comparison between BJT and JFET BJT JFET ) BJT is a bipolar device, both majority JFET is an unipolar device, electron and minority carriers take place in electrical conduction. current in Nchannel and hole current in Pchannel. ) BJT is current operated device, it is a current controlled current source. JFET is voltage operated device, it is a voltage controlled current source. 3) BJT has high g m and hence provides JFET has low g m and hence large gain provides low gain. 4) BJT has low input resistance ( k) JFET has high input resistance (M) input junction is forward biased. input junction is reverse biased. 5) Thermal runaway is possible in BJT. Thermal runaway is not possible in C increases when temperature increases. JFET. D decreases when temperature increases. 6) BJT can be operated with low values JFET requires large supply voltage of supply voltage (3 ) (> ) 7) BJT is noisy in operation. JFET is less noisy in operation. 8) Requires large area while fabrication Requires less area while fabrication of C's. of C's. 9) Less susceptible to damage while handling. More susceptible to damage while handling. ) ery complex biasing circuits required to provide stability. Biasing circuits are less complex when compared to that of BJT. ) Cannot be used as a voltage variable resistance t can be used as a voltage variable resistance. (b) Thermal Runaway in Transistor The junction temperature of a transistor can increase due to the increase in ambient temperature or due to self heating. The transistor collector current is given by C B + ( + ) CBO CBO is temperature dependent, CBO doubles for C rise in temperature in Si transistor. Hence if the collector junction temperature (T j ) increases, the minority leakage current CBO increases, this increases C, hence the power dissipation in transistor (P D ) increases. Since power is dissipated in the form of heat, the junction temperature further increases, further increasing C. T j CBO C P D 3/Engg/SE/Pre Pap/3/EXTC/AE_

2 : S.E. AE - Thus due to thermal regeneration, C increases to a very high value causing damage to the transistor (burn out). This phenomenon is by which C increases with temperature is called as thermal regeneration. The process by which transistor undergoes damage is called thermal runaway. f the rate at which power dissipated in transistor is equal to the rate at which power radiated outside, then junction temperature remains constant. This is achieved by using Heat Sink. Note : Thermal bias stability is very important in the case of BJT.. (c) in s + s in s A A in A. s + A. ( A.) A. s f A s.a A. or 36 f Barkhausein s criteria. f A in s if A <, then f A. in becomes less than in due to this amplitude of oscillation die out after some time. if A > then f A. in will be greater than in due to which signal keeps on building up as shown below of A then sustained oscillations are obtained as shown below : t t t 3/Engg/SE/Pre Pap/3/EXTC/AE_

3 Prelim Question Paper Solution However, initially oscillator should design with A > when power supply is turned on the output voltage keeps on building up (A > ). After output reaches at desired output level then A should reduce to by decreasing either A or. Hence stable oscillation will be obtained.. (d). (a) Comparison between LC and RC Oscillator LC RC ) LC oscillators are used to generate An RC oscillator is used for low high frequency. The frequency of frequency oscillator oscillations is f o f o ; fo RC LC LC ) Range of operating frequency is low. By varying the frequency determining Usually above MHz frequency. components a wide range of frequency is obtained. Used upto MHz frequency. 3) Frequency stability of LC oscillators Frequency stability of RC oscillators is poor because the values of is relatively better. frequency determining components change with temperature, ageing etc. Also the capacitor value becomes comparable to junction capacitors at high frequency. 4) LC oscillators are used for high RC oscillators can not be used at frequency applications because in high frequencies because the value the low frequency range the values of capacitor required is of the order of L and C should be very large. of junction capacitors. Hence the Large values of L and C makes the junction capacitors can change the circuit bulky and costly. frequency of oscillations. Hence frequency stability is not better at high frequencies. Hence, it is used at low frequencies. The DC equivalent circuit is as shown DD 4 7M G R D 4.7k M R S.5k 3/Engg/SE/Pre Pap/3/EXTC/AE_ 3

4 : S.E. AE -. (b) M 4M Here G [M 7M] 3 R G (7MM M) 875 k Now GS G s R s 3.5 s ( s in ma) GS GS 3.5 Now D DSS s 8 P 4 8 (7.5 D ) s 6 D D D D D D D D D ma or ma D ma or 3.9 ma For D 3.9 ma For D ma GS 6.8 GS But P 4 GS 6.8 GS D ma Now g mo DSS 8mA P 4 4 ms g m GS gmo P 4mS 4 ms ms g m Now neglecting the value of r d A v g m R D 4.7 A v 9.4 R i R 875 k C R R D 4.7k A v 9.4 R i 875 k R 4.7 k (i) BJT has a positive temperature coefficient i.e., with the increase in temperature, value of C increases and hence power dissipation P D increase and the temperature increases. Thus due to thermal regeneration C increases to a very high value causing damage to transistor. This is thermal runaway. 4 3/Engg/SE/Pre Pap/3/EXTC/AE_

5 Prelim Question Paper Solution FET on the other hand have negative temperature coefficient since the mobility decreases with increasing temperature. Since majority carrier current decreases with temperature, thermal runaway is not encountered in FET. 3. (a) (ii) Transfer characteristics of JFET A graph drawn with D, D. GS for a constant value of DS is as shown. The graph is parabolic in nature. The graph can be represented mathematically by the equation D DS GS p The above equation shows that JFET is a square law device. (Refer Class Notes). JFET Parameters ) DSS : Drain source saturation current : DSS is defined as the maximum value of drain current when GS. t is a constant for a JFET. For JFET BFW, DSS typical 7 ma. ) GS-OFF : Pinch off voltage : t is defined as the maximum value of GS at which the drain current becomes zero. t is also called as pinch off voltage. For a JFET, GS-OFF is a constant. For JFET BFW, GS-OFF typical.5. D (ma) 3) g m : Transconductance : t is defined as the ratio of the change in drain current to the change in the gate source voltage for a constant value of GS. DSS D g m DS constant GS slope of transfer characteristics D D D GS () GS OFF ( p ) GS D (ma) DSS GS p k 3/Engg/SE/Pre Pap/3/EXTC/AE_ 5

6 : S.E. AE - The given circuit is of twoway series clipper. Assuming the diodes to be ideal. During positive half cycle of the input, we observe that D gets forward biased and D gets reverse biased. D acts as a short circuit whereas D act as a open circuit. The equivalent circuit is as shown. + As out can be observed from the above figure the output voltage as long as i ; it reverse biases the diode more than the input voltage. When i > the output becomes a function of i/p voltage. 8 k D 8 ma D k 6 6 The output voltage can be drawn as shown. 8 6 i Similarly, during ve half cycle of input, D gets forward biased and D gets reverse biased. The circuit diagram is as shown. + i + k.5 k However, the.5 bias keep the diode reverse biased unless i.5. Hence. When i <.5, the output voltage voltage becomes a function of input voltage i. Maximum output voltage i 6 3/Engg/SE/Pre Pap/3/EXTC/AE_

7 Prelim Question Paper Solution 3. (b) The waveform can be drawn as shown D off D off i 5.5 D OFF D ON The transfer characteristics are as shown. 8.5 DODE ON (D ) D D off + m 6 DODE OFF D & D m 5.5 Emitter Follower / Common Collector (CC) Amplifier + (a) Circuit diagram CC C C D ON D OFF R B DODE ON (D ) i Q R E C C t t i 3/Engg/SE/Pre Pap/3/EXTC/AE_ 7

8 : S.E. AE - Since output is taken from emitter, emitter voltage follows the base voltage and hence the name emitter follower. (b) ac Equivalent circuit Short CC, short all capacitors. (c) Replace transistor by its equivalent R i i (d) To find input resistance R i i / i i i b b.h ie ( h fe)bre RB R i.. R h (h )R h ie (h fe)r E.RB R B h ie ( h fe)re R h (h )R i b i b B ie fe E B ie fe E (e) To find output resistance R hie R R E R h g fe m R B E (f) To find voltage gain A v / i Output oltage ( ) ( b h fe).re A v nput oltage () i b. h ie (h fe)re ( h fe)re h ie (h fe)re Note : Since ( + h fe ) R E >> h ie and h fe >>, we get A. Hence i, the output voltage follows the input voltage. Hence the name voltage follower or buffer. Q i i R B b h ie i.h (h ) R b b h (h )R b ie fe b E ie fe E R E b (+h fe ) R E h fe b R 8 3/Engg/SE/Pre Pap/3/EXTC/AE_

9 Prelim Question Paper Solution 4. (a) (g) To find current gain A / i output current A i input current (h) Results i ( h ) R fe b B. b RB h ie (h fe)re ( h ).R R h (h )R fe B B ie fe E. b b i Without R L With R L ( h fe) RE ( h fe) RE RL ) A A. h ie (h fe)re h ie (h fe)re RE RL A ( RB h fe ). A R h ( h )R B ie ( RB h fe ). R h ( h )R fe E ) RE RE RL 3) R i R B [ h ie + ( h fe)re ] R i R B [ h ie + ( h fe)re ] hie hie R R E RE R o R E RE h 4) fe gm hfe gm R R R o o L B ie fe E (i) Applications of CC amplifier. Used as a buffer amplifer and an isolator to isolate the source and load due to its high input impedance and low output impedance. i) Circuit diagram R + CC R C i R R E Q. R E C E 3/Engg/SE/Pre Pap/3/EXTC/AE_ 9

10 : S.E. AE - ii) ac Equivalent circuit Short CC and short all the capacitors Q R C i R B R E R R iii) Replace transistor by its h parameter model iv) To find input resistance R i i / i i i b b.h ie ( h fe)bre RB R i.. R h (h )R i b i b B ie fe E h ( h )R.R ie fe E B R h (h )R B ie fe E R h ( h )R B ie fe E v) To find output resistance R R R C vi) To find voltage gain A v / i Output oltage ( ) A v nput oltage () i b hfe b RC h (h )R b ie fe E i h ie i R B R C b ( + h fe ) b R E b ie fe E.RC. h (h )R h fe b R i i b.h ie (h fe)br R E h (h )R b ie fe E h R fe C h ie (h fe)re The ve sign indicates that input and output voltages are 8 out of phase. 3/Engg/SE/Pre Pap/3/EXTC/AE_

11 Prelim Question Paper Solution vii) To find current gain A / i A i viii) Results output current input current h R i fe b B. b RB h ie (h fe)re h.r fe B RB h ie (h fe)re Without R L hfe RC ) A h (h )R ie fe E. b b i hfe RC A h (h )R With R L R R L. ie fe E RC RB RB RC ) A h fe. A h fe.. R h (h )R R h ( h )R R R B ie fe E B ie fe E 3) R i R B [ h ie + ( h fe)re ] R i R B [ h ie + ( h fe)re ] 4) R o R C R o R C R o R C R L The AC equivalent of the given circuit is as follows. i R R h ie hferc Now A v h ie (h fe)re A v 3.75 RB A i hfe R B h ie ( h fe ) R E A i R i R B (h ie ( h fe)r E ) 5k (.k ( )) 5 k (8.7 k) R i 9.85 k R R c 3. k R E R C k.k () 5k 5k.k () L C L 3/Engg/SE/Pre Pap/3/EXTC/AE_

12 : S.E. AE - 4. (b) The dc equivalent circuit is as shown : D k( ) k GS GS(th) D(on) GS(on) GS(th) ( ) ma (4 ).5mA.5 A / v 3 We use graphical method to solve for quiescent values. (i) For GS 3 ; D.5mA (ii) For GS 6; D 8 ma Also D(on) ma; GS(on) 4 and GS(th) These four points are sufficient to plot a curve as shown in figure (i). For network bias line : GS DD D R D 4 D (3.3 k) GS DD 4 D ma D DD 4 7.7mA GS RD 3.3k (ma) R DD D D(on) GS Qpoint R R 47 k 8.7 k Figure (i) The resulting bias line appears as figure (i) : DQ 5.6 ma; GSQ 5.4 with DSQ GSQ 5.4 R D 3.3k D(on) ma GS(on) 4 GS(th) ; g m 3 ms; in 5m R s.8k GS 3/Engg/SE/Pre Pap/3/EXTC/AE_

13 Prelim Question Paper Solution 5. (a) Now, A v g m R D ; neglecting r d A v 75.9 in A v 5 m ve sign indicates 8 phase shift w.r.t. input. Common Emitter BJT Amplifier with R E unbypassed (a) Circuit diagram i RB (b) ac Equivalent circuit Short CC and short all the capacitors R B R E (c) Replace transistor by its h parameter model Q + CC i R C i b h ie h fe b i R B R C ( + h fe ) b R E Q R C R E R i i b.h ie (h fe)br R E b b h (h )R ie fe E 3/Engg/SE/Pre Pap/3/EXTC/AE_ 3

14 : S.E. AE - (d) To find input resistance R i i / i i i b b.h ie ( h fe)bre RB R i.. R h (h )R i b i b B ie fe E h ( h )R.R ie fe E B R h (h )R B ie fe E (e) To find output resistance R R R C R h ( h )R B ie fe E (f) To find voltage gain A v / i Output oltage ( ).RC A v nput oltage (). h (h )R hfe b RC h (h )R b ie fe E i b ie fe E h R fe C h ie (h fe)re The ve sign indicates that input and output voltages are 8 out of phase. (g) To find current gain A / i output current A i input current i hfe b RB. R h (h )R h fe.rb R h (h )R (h) Results b B ie fe E B ie fe E b. b i Without R L With R L ) hfe RC hfe RC RL A A. h ie (h fe)re h ie (h fe)re RC RL ) RB RB A h fe. A h fe. R B h ie (h fe )R E R B h ie ( h fe )R E. RC RC RL 3) R i R B [ h ie + ( h fe)re ] R i R B [ h ie + ( h fe)re ] 4) R o R C R o R C R o R C R L 4 3/Engg/SE/Pre Pap/3/EXTC/AE_

15 Prelim Question Paper Solution 5. (b) (i) Positive Biased Clamper : This circuit is same as C positive clamper, only difference that a battery of potential is connected in series with the diode D. in D R L The battery is connected in such a way that it + R makes the diode reverse biased. The operation of the circuit can be explained as follows : During negative half cycle, when i >, then diode becomes forward biased and starts conducting and charges the capacitor to a voltage. C m.7 C m ( +.7) m ( +.7) m ( +.7) in + m m o ( +.7) After the peak value diode becomes reverse biased and acts as an open circuit. Now the output voltage is given as o i + C where C m ( +.7) o i + m ( +.7) Let i, then o m ( +.7) Let i m, then o m ( +.7) Let i m, then o ( +.7) t t O 3/Engg/SE/Pre Pap/3/EXTC/AE_ 5

16 : S.E. AE - This indicates that a dc level of m ( +.7) is added to the ac signal. The input and output waveforms as shown in figure. n the above circuit, if we reverse the polarity of the battery and if we connect the battery in such a way that it makes the diode forward biased, then we can prove that o i + C where C m +.7 o i + m +.7 Let i, then o m +.7 Let i m, then o m +.7 Let i m, then o.7 + m The input and output waveforms are as shown : (ii) n a transistor, E C + B C CB constant E C CE constant B From transistor working, C E + CBO where is that part of injected carriers reaching the collector. ( C + B ) + CBO ( ) C B + CBO CBQ C B But C. B ( ) ( + ) m m +.7 m t t 6 3/Engg/SE/Pre Pap/3/EXTC/AE_

17 6. (a) Prelim Question Paper Solution NChannel Enhancement MOSFET (NMOS) Construction The figure shows the construction of NMOS. t consists of p type substrate in which two n type regions are formed as shown in figure. The electrical connection taken from these n regions are known as DRAN and SOURCE. A insulating layer of SiO is formed on the top of the p substrate by oxidizing the silicon. The high conductivity polycrystalline silicon layer is deposited on the SiO and the electrical connection taken from it is known as GATE. An electron layer forms between Drain and Source after applying voltage at the gate. This layer is also known as nchannel. n the figure L is the length of the channel and W is the width of the channel and t ox is the thickness of the oxide layer. The electrical connection brought out from p substrate is known as Body Terminal. Basic Operation of NMOS For the NMOS to conduct we have to apply positive voltage at the gate. Thus when the applied gate voltage GS is less than the threshold voltage TN, then no electron inversion layer creates, and also the pn junction between Drain and Substrate is Reverse Biased therefore no current flows between Drain and Source of the NMOS. GS < TN G Now consider we are applying constant dc voltage DS between Drain and Source, if we increase the value of GS, then electron inversion layer is created between Drain and Source, and due to applied positive Drain to Source voltage, electron moves from Source to the positive terminal drain and Convention current flows from Drain to source. As shown in figure, for constant value of DS, as the value of GS increases, then the Drain current of the NMOS also increases. p S n + D Space Charge Region + DS D n + GS > TN GS > TN GS < TN G 3/Engg/SE/Pre Pap/3/EXTC/AE_ 7

18 : S.E. AE - Now let us keep the GS constant such that GS > TN, so the electron inversion layer is created between the Drain and Source, and no will increase DS in step. From the figure, Drain to Source voltage Drain to Gate voltage + Gate to source voltage DS DG + GS DG DS GS (A) Now initially as we increase DS from zero value, then Drain Current do also starts increasing as shown in figure (a). Now as we still increase DS, such that DS TN, then from equation (A) DG goes on decreasing, therefore attractive force for free carriers in the inversion layer goes on decreasing causing a reduction in the effective channel width, due to this incremental conductance of the channel at the Drain decreases, due to this increment of D due to DS decreases, i.e. slope of D vs DS curve decreases as shown in figure (b). The drain to source voltage at which this happens is known as DS (sat). Now when DS DS (sat), then it produces zero charge density at the Drain, and as DS goes on increasing then this zero charge density moves towards the source. n this case the electrons which are present right from beginning, enters through the source, and travels towards the zero charge density point, through the channel. After this, electrons gets injected into the space-charge region, and swifts towards the Drain terminal, due to the electricfield. This is similar to the electron moving in Reversebiased BC junction of B.J.T. Thus now if we increase DS, then D do not increase, infact it remains constant, i.e. Drain current D is pinchedoff and we say that NMOS operates in the Saturation Region. Transfer Characteristics : t is the graph of GS s D, as we know that when GS < TN, then electron inversion layer is absent, and hence Drain current is zero, and hence Drain current is zero, i.e. D. When GS TN, then it creates electron inversion layer between Drain and Source due to applied DS, the drain current D increases, as the GS increases. DS constant For PMOS D DS constant For NMOS TN TN DS 8 3/Engg/SE/Pre Pap/3/EXTC/AE_

19 Prelim Question Paper Solution 6. (b) WEN BRDGE OSCLLATOR R 3 R 4 f R C +ve feed back R 3 C R R A R C R R Wein-bridge R C T R C R B R 4 R 3 A A C R 4 C C C Wein-Bridge Oscillator CC R C R D T ve feed back R C C C R e C C 3/Engg/SE/Pre Pap/3/EXTC/AE_ 9

20 : S.E. AE - f can be obtained by using following equivalent circuit. R f C R C where Z series R jc Z parallel R X C Z f Z Z SC R R j C j C () (using voltage divider rule) But circuit employ voltage series feedback. Hence for voltage series feedback () f. Comparing equation () & () Z Z Z se R j C R Z Z Se R j CR Z + Z Se j C R jc R RjC jωc j C Rj ωc RjωC jωc Rj ωc ωc Let R R R C C C f Z series Z RjC ( j CR) ( j CR) ( j C R ) jc RjωC jωcr jωcrω CCRR ( jωc R ) jωc (3) 3/Engg/SE/Pre Pap/3/EXTC/AE_

21 Prelim Question Paper Solution Hence RjωC jωcr jωcr ω C R Z + Z se ( jωcr) jωc 3jCR C R ( jcr) j. C R jωcr + 3jωCRω C R ( j CR) jωc j RC + 3jCR C R RC j3 RCj R C Let divide by jrc (mag. part should always be in denominator) mge R C /RC, /3 Total phase shift around a closed loop should be. Condition A Using condition () eqn.(5) become j CR jc (To get phase shift imaginary part of (5) equal to ) j CR j C CR CR RC (4) 3/Engg/SE/Pre Pap/3/EXTC/AE_

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