Field-Effect (FET) transistors

Size: px
Start display at page:

Download "Field-Effect (FET) transistors"

Transcription

1 Field-Effect (FET) transistors References: Barbow (Chapter 8), Rizzoni (chapters 8 & 9) In a field-effect transistor (FET), the width of a conducting channel in a semiconductor and, therefore, its current-carrying capability, is varied by the application of an electric field (thus, the name field-effect transistor). As such, a FET is a voltage-controlled device. The most widely used FETs are Metal-Oxide-emiconductor FETs (or MOFET). MOFET can be manufactured as enhancement-type or depletion-type MOFETs. Another type of FET is the Junction Field-Effect Transistors (JFET) which is not based on metal-oxide fabrication technique. FETs in each of these three categories can be fabricated either as a n-channel device or a p-channel device. As transistors in these 6 FET categories behave in a very similar fashion, we will focus below on the operation of enhancement MOFETs that are the most popular. n-channel Enhancement-Type MOFET (NMO) The physical structure of a n-channel Enhancement-Type MOFET (NMO) is shown. The device is fabricated on a p-type substrate (or Body). Two heavily doped n-type regions (ource and rain) are created in the substrate. A thin (fraction of micron) layer of io 2, which is an excellent electrical insulator, is deposited between source and drain region. Metal is deposited on the insulator to form the ate of the device (thus, metal-oxide semiconductor). Metal contacts are also made to the source, drain, and body region. To see the operation of a NMO, let s ground the source and the body and apply a voltage v between the gate and the source, as is shown above. This voltage repels the holes in the p-type substrate near the gate region, lowering the concentration of the holes. As v increases, hole concentration decreases, and the region near gate behaves progressively more like intrinsic semiconductor material (when excess hole concentration is zero) and then, finally, like a n-type material as electrons from n + electrodes (source and drain) enter this region. As a result, when v become larger than a threshold voltage, V t, a narrow layer ECE60L Lecture Notes, pring

2 between source and drain regions is created that is populated with n-type charges (see figure). The thickness of this channel is controlled by the applied v (it is proportional to v V t ). As can be seen, this device works as a channel is induced in the semiconductor and this channel contains n-type charges (thus, n-channel MOFET). In addition, increasing v increases channel width (enhances it). Therefore, this is an n-channel Enhancement-type MOFET or Enhancement-type NMO. Now for a given values of v > V t (so that the channel is formed), let s apply a small and positive voltage v between drain and source. Then, electrons from n + source region enter the channel and reach the drain. If v is increased, current i flowing through the channel increases. Effectively, the device acts like a resistor; its resistance is set by the dimension of the channel and its n-type charge concentration. In this regime, plot of i versus v is a straight line (for a given values of v > V t ) as is shown. The slope of i versus v line is the conductance of the channel. For v V t no channel exists (zero conductance). As value of v V t increases, channel becomes wider and its conductivity increases (because its n-type charge concentration increases). Therefore, the channel conductance (slope of i versus v line) increases with any increase in v V t as is shown above. The above description is correct for small values of v as in that case, v = v v v and the induced channel is fairly uniform (i.e., has the same width near the drain as it has near the source). For a given v > V t, if we now increase v, v = v v becomes smaller than v. As such the size of channel near drain becomes smaller compared to its size near the source, as is shown. As the size of channel become smaller, its resistance increases and the curve of i versus v starts to roll over, as is shown below. ECE60L Lecture Notes, pring

3 For values of v = V t (or v = v V t ), width of the channel approaches zero near the drain (channel is pinched off). Increasing v beyond this value has little effect (no effect in our simple picture) on the channel shape, and the current through the channel remains constant at the value reached when v = v V t. o when the channel is pinched off, i only depends on v (right figure below). NMO Characteristic Curves i versus v in the active (or saturation) regime In sum, a FET can operate in three regimes: 1) Cut-off regime in which no channel exists (v < V t for NMO) and i = 0 for any v. 2) Ohmic or Triode regime in which the channel is formed and not pinched off (v > V t and v v V t for NMO) and FET behaves as a voltage-controlled resistor. 3) Active or aturation regime in which the channel is pinched off (v V t and v > v V t for NMO) and i does not change with v. everal important point should be noted: 1) No current flows into the gate, i = 0 (note the insulator between gate and the body). 2) FET acts as a voltage-controlled resistor in the ohmic region. In addition, when v v, FET would act as a linear resistor. 3) When FET is in cut-off, i = 0. However, if i = 0, this does not mean that FET is in cut-off. FET is in cut-off only when a channel does not exist (v < V t ) and i = 0 for any applied v. On the other hand, FET can be in ohmic region, i.e., a channel is formed, but i = 0 because v = 0. ECE60L Lecture Notes, pring

4 4) The third regime is called saturation in most electronic books because i is saturated in this regime and does not increase further. This is a rather unfortunate name as saturation regime in a FET means very different thing than it does in a BJT. ome newer books call this regime active (as it equivalent to active-linear regime of a BJT). 5) The transition between ohmic and active region is clearly defined by v = v V t the point where the channel is pinched off. The i versus v characteristic curves of a FET look very similar to i C versus v CE characteristics curves of a BJT. In fact, as there is a unique relationship between i B and v BE, the i C versus v CE characteristic curves of a BJT can be labeled with different values of v BE instead of i B, making the characteristic curves of the two devices even more similar. In FET v control device behavior and in BJT v BE. Both devices are in cut-off when the input voltage is below a threshold value: v BE < v γ for BJT and v < V t for NMO. They exhibit an active regime in which the output current (i C or i ) is roughly constant as the output voltage (v CE or v ) is changed. There are, however, major differences. Most importantly, a BJT requires i B to operate but in a FET i = 0 (actually very small). These differences become clearer as we explore FETs. As can be seen from NMO physical structure, the device is symmetric, that is position of drain and source can be replaced without any change in device properties. The circuit symbol for a NMO is shown on the right. For most applications, however, the body is connected to the source, leading to a 3-terminal element. In that case, source and drain are not interchangeable. A simplified circuit symbol for this configuration is usually used. By convention, current i flows into the drain for a NMO (see figure). As i = 0, the same current will flow out of the source. irection of arrows used to identify semiconductor types in a transistor may appear confusing. The arrows do NOT represent the direction of current flow in the device. Rather, they denote the direction of the underlying pn junction. For a NMO, the arrow is placed on the body and pointing inward as the body is made of p-type material. (Arrow is not on source or drain as they are interchangeable.) In the simplified symbol for the case when body and source is connected, arrow is on the source (device is not symmetric now) and is pointing outward as the source is made of n-type materials. (i.,e. arrow pointing inward for p-type, arrow pointing outward for n-type). i B i ECE60L Lecture Notes, pring

5 NMO i versus v Characteristics Equations Like BJT, a NMO (with source connected to body) has six parameters (three voltages and three currents), two of which (i and v ) can be found in terms of the other four by KVL and KCL. NMO is simpler than BJT because i = 0 (and i = i ). Therefore, three parameters describe behavior of a NMO (v, i, and v ). NMO has one characteristics equation that relates these three parameters. Again, situation is simpler than BJT as simple but accurate characteristics equations exist. Cut-off: v < V t, i = 0 for any v Ohmic: v > V t, i = K[2v (v V t ) v 2 ] for v < v V t Active: v > V t, i = K(v V t ) 2 for v > v V t In the above, K and V t are constants that depend on manufacturing of the NMO (given in manufacturer spec sheets). As mentioned above, for small values of v (v v V t ), NMO behaves as resistor, r, and the value of r is controlled by v V t. This can be seen by dropping v 2 in i equation of ohmic regime: r = v i 1 2K(v V t ) How to olve NMO Circuits: olution method is very similar to BJT circuit (actually simpler because i = 0). To solve, we assume that NMO is in a particular state, use NMO model for that state to solve the circuit and check the validity of our assumption by checking the inequalities in the model for that state. A formal procedure is: 1) Write down a KVL including terminals (call it -KVL). 2) Write down a KVL including terminals (call it -KVL). 3) From -KVL, compute v (using i = 0) 3a) If v < V t, NMO is in cut-off. Let i = 0, solve for v from -KVL. We are done. 3b) If v > V t, NMO is not in cut-off. o to step 4. 4) Assume NMO is in active region. Compute i from i = K(v V t ) 2. Then, use -KVL to compute v. If v > v V t, we are done. Otherwise go to step 5. 5) NMO has to be in ohmic region. ubstitute for i from i = K[2v (v V t ) v 2 ] in -KVL. You will get a quadratic equation in v. Find v (one of the two roots of the equation will be unphysical). Check to make sure that v < v V t. ubstitute v in -KVL to find i. ECE60L Lecture Notes, pring

6 Example: Consider NMO circuit below with K = 0.25 ma/v 2 and V t = 2 V. Find v o when v i = 0, 6, and 12 V for R = 1 KΩ and V = 12 V. -KVL: v = v i V -KVL: V = R i + v R v o A) v i = 0 V. From -KVL, we get v = v i = 0. As v < V t = 2 V, NMO is in cut-off, i = 0, and v is found from -KVL: v i i -KVL: v o = v = V R i = 12 V B) v i = 6 V. From -KVL, we get v = v i = 6 V. ince v = 6 > V t = 2, NMO is not in cut-off. Assume NMO in active region. Then: i = K(v V t ) 2 = (6 2) 2 = 4 ma -KVL: v = V R i = = 8 V ince v = 8 > v V t = 2, NMO is indeed in active region and i = 4 ma and v o = v = 8 V. C) v i = 12 V. From -KVL, we get v = 12 V. ince v > V t, NMO is not in cut-off. Assume NMO in active region. Then: i = K(v V t ) 2 = (12 2) 2 = 25 ma -KVL: v = V R i = = 13 V ince v = 13 < v V t = 12 2 = 10, NMO is NOT in active region. Assume NMO in ohmic region. Then: i = K[2v (v V t ) v 2 ] = [2v (12 2) v 2 ] i = [20v v 2 ] ubstituting for i in -KVL, we get: -KVL: V = R i + v 12 = [20v v 2 ] + v v 2 24v + 48 = 0 ECE60L Lecture Notes, pring

7 This is a quadratic equation in v. The two roots are: v = 2.2 V and v = 21.8 V. The second root is not physical as the circuit is powered by a 12 V supply. Therefore, v = 2.2 V. As v = 2.2 < v V t = 10, NMO is indeed in ohmic region with v o = v = 2.2 V and -KVL: v = V R i i = , 000 = 9.8 ma Load Line: Operation of NMO circuits can be better understood using the concept of load line. imilar to BJT, load line is basically the line representing -KVL in i versus v space. Load line of the example circuit is shown here. Exercise: Mark the Q-points of the previous example for v i = 0, 6, and 12 V on the load line figure below. Body Effect In deriving NMO (and other MO) i versus v characteristics, we had assumed that the body and source are connected. This is not possible in an integrated chip which has a common body and a large number of MO devices (connection of body to source for all devices means that all sources are connected). The common practice is to attach the body of the chip to the smallest voltage available from the power supply (zero or negative). In this case, the pn junction between the body and source of all devices will be reversed biased. The impact of this to lower threshold voltage for the MO devices slightly and its called the body effect. Body effect can degrade device performance. For analysis here, we will assume that body effect is negligible. ECE60L Lecture Notes, pring

8 p-channel Enhancement-Type MOFET (PMO) The physical structure of a PMO is identical to a NMO except that the semiconductor types are interchanged, i.e., body and gate are made of n-type material and source and drain are made of p-type material and a p-type channel is formed. As the sign of the charge carriers are reversed, all voltages and currents in a PMO are reversed. By convention, the drain current is flowing out of the drain as is shown. With this, all of the NMO discussion above applies to PMO as long as we multiply all voltages by a minus sign: i B i Cut-off: v > V t, i = 0 for any v Ohmic: v < V t, i = K[2v (v V t ) v 2 ] for v > v V t Active: v < V t, i = K(v V t ) 2 for v < v V t Note that V t is negative for a PMO. Complementary MO (CMO) Complementary MO technology employs MO transistors of both polarites as is shown below. CMO devices are more difficult to fabricate than NMO, but many more powerful circuits are possible with CMO configuration. As such, most of MO circuits today employ CMO configuration and CMO technology is rapildy taking over many applications that were possible only with bipolar devices a few years ago. 2 2 v i 2 i 2 v o 1 1 i 1 1 ECE60L Lecture Notes, pring

9 epletion-type MOFET The depletion-type MOFET has a structure similar to the enhancement-type MOFET with only one important difference; depletion-type MOFET has a physically implanted channel. Thus, a n-type depletion-type MOFET has already a n-type channel between drain and source. When a voltage v is applied to the device, a current i = I flows even for v = 0. (how I = KVt 2.) imilar to NMO, if v is increased, the channel become wider and i increases. However, in a n-type depletion-type MOFET, a negative v can also be applied to the device, which makes the channel smaller and reduces i. As such, negative v depletes the channels from n-type carriers leading to the name depletion-type MOFET. If v is reduced further, at some threshold value V t (which is negative), the channel disappears and i = 0, as is seen in the figure. It should be obvious that a depletion-type MOFET can be operated either in enhancement mode or in depletion mode. p-type depletion MOFET operate similarly to p-type enhancement MOFET expect that V t > 0 for depletion type and V t < 0 for the enhancement type. Figure below shows i versus v of four types of MOFET devices in the active region. Circuit symbols for depletion-type MOFET devices are also shown. B B i i i i n-type epletion MOFET p-type epletion MOFET ECE60L Lecture Notes, pring

10 NMO Inverter and witch The basic NMO inverter circuit is shown; the circuit is very similar to a BJT inverter. This circuit was solved in page 65 for V = 12 and R = 1 kω. We found that if v i = 0 (in fact v i < V t ), NMO will be in cut-off with i = 0 and v o = V. When v i = 12 V, NMO will be in ohmic region with i = 10 ma and v = 2.2 V. Therefore, the circuit is an inverter gate. It can also be used as switch. v i R V i v o There are some important difference between NMO and BJT inverter gates. First, BJT needs a resistor R B. This resistor converts the input voltages into an i B and keep v BE v γ. NMO does not need a resistor between the source and the input voltage as i = 0 and v i = v can be directly applied to the gate. econd, if the input voltage is high, the BJT will go into saturation with v o = v CE = V sat = 0.2 V. In the NMO gate, if the input voltage is high, NMO is in the ohmic region. In this case, v can have any value between 0 and v V t ; the value of v o = v is set by the value of the resistor R. This effect is shown in the transfer function of the inverter gate for two different values of R. Exercise: Compute v o for the above circuit with V = 12 and R = 10 kω when v i = 12 V. ECE60L Lecture Notes, pring

11 CMO Inverter The CMO inverter, the building block of CMO logic gates, is shown below. The low and high states for this circuit correspond to 0 and V, respectively. CMO gates are built on the same chip such that both NMO and PMO have the same threshold voltage V tn = V t, V tp = V t and same K (one needs different channel length and width to get the same K for PMO and NMO). In this case, the CMO will have a symmetric transfer characteristics, i.e., v o = 0.5V when v i = 0.5V as is shown below. This circuit works only if V > 2V t by a comfortable margin. v i = 0 ince v 1 = v i = 0 < V t, NMO will be in cut-off. Therefore, i 1 = 0. But v 2 = v i V = V < V t, thus, PMO will be ON. Recall i versus v characteristic curves of a NMO (page 63), each labeled with a values of V. As v 2 = V is a constant, operating point of PMO will be on one of the curves. But i 1 = i 2 = 0 and the only point that satisfies this condition is v 2 = 0. Note that PMO is NOT in cut-off, it is in ohmic region and acts like a resistor. v 2 = 0 because i 2 = 0. Output voltage can now be found by KVL: v o = V v 2 = V. o, when v i = 0, v o = V. v i = V ince v 1 = v i = V > V t, NMO will be ON. But since v 2 = v i V = 0 > V t, PMO will be in cut-off and i 2 = 0. ince i 1 = i 2, i 1 = 0. ince NMO is on and i 1 = 0, NMO should be in ohmic region with v 1 = 0. Then v o = v 1 = 0. o, when v i = V, v o = 0 v i = 0.5V In this case, v 1 = v i = 0.5V and v 2 = v i V = 0.5V. ince, v 1 > V t and v 2 < V t, both transistors will be ON. Furthermore, as transistors have same threshold voltage, same K, i 1 = i 2, and v 1 = v 2, both transistor will be in the same state (either ohmic or active) and will have identical v : v 1 = v 2. ince v 1 v 2 = V, then v 1 = 0.5V, v 2 = 0.5V, and v o = 0.5V. Note that since V > 2V t, both transistors are in the active region. The transfer function of the CMO inverter is shown below. 2 2 V V o NMO Off PMO Ohmic NMO Active PMO Ohmic v i 2 i 2 v o NMO Active PMO Active 1 1 i 1 NMO Ohmic PMO Active 1 NMO Ohmic PMO Off V i ECE60L Lecture Notes, pring

12 CMO inverter has many advantages compared to the NMO inverter. Its transfer function is much closer to an ideal inverter transfer function. The low and high states are clearly defined (low state of NMO depended on the value of R ). It does not include any resistors and thus takes less area on the chip. Lastly, i 1 = i 2 = 0 for both cases of output being low or high. This means that the gate consumes very little power (theoretically zero) in either state. A non-zero i 1 = i 2, however, flows in the circuit when the gate is transitioning from one state to another as is seen in the figure. The maximum value of i that flows through the gate during the transition can be easily calculated as this maximum current flows when v i = 0.5V and v o = 0.5V. For example, consider the CMO inverter with V = 12 V, V t = 2 V, and K = 0.25 ma/v 2. Maximum i flows when v i = v 1 = 0.5V = 6 V. At this point, v 1 = v o = 0.5V = 6 V. As, v 1 = 6 > v 1 v t = 4 V, NMO is in active regime. Then: i 1 = K(v 1 V t ) 2 = (6 2) 2 = 4 ma ECE60L Lecture Notes, pring

13 CMO NAN ate As mentioned before CMO logic gates have low and high states of 0 and V, respectively. We need to consider all possible cases to show that this a NAN gate. To start, we can several general observations: 1) by KVL v 1 = v 1, v 2 = v 2 v 1, v 3 = v 1 V, and v 4 = v 2 V, 2) by KCL i 1 = i 2 = i 3 + i 4 v 2 v 1 M 3 M 4 i 3 M 2 V i 4 i 2 i 1 v o 3) by KVL v o = v 1 + v 2 = V + v 3 and v 3 = v 4. M 1 The procedure to solve/analyze CMO gates are as follows: // A) For a given set of input voltages, use KVLs (similar to 1 above) to find v of all transistors and find which ones are ON or OFF.// B) et i = 0 for all transistors that are OFF. Use KCLs (similar to 2 above) to find i for other transistors.// C) Look for transistors that are ON and have i = 0. These transistors have to be in Ohmic region with v = 0. ) Use KVLs (similar to 3 above) to find v o based on v. v 1 = 0, v 2 = 0 We first find v and state of all transistors by using KVL in no. 1 above. v 1 = v 1 = 0 < V t M1 is OFF i 1 = 0 v 2 = v 2 v 1 = v 1 M2 is? v 3 = v 1 V = V < V t M3 is ON v 4 = v 2 V = V < V t M4 is ON ince i 1 = 0, by KCLs in no. 2 above, i 2 = i 1 = 0 and i 3 + i 4 = i 1 = 0. ince i 0 for both PMO and NMO, the last equation can be only satisfied if i 3 = i 4 = 0. We add the value of i to the table above and look for transistors that are ON and have i = 0. These transistors have to be in Ohmic region with v = 0. v 1 = v 1 = 0 < V t M1 is OFF i 1 = 0 v 2 = v 2 v 1 = v 1 M2 is? i 2 = 0 v 3 = v 1 V = V < V t M3 is ON i 3 = 0 v 3 = 0 v 4 = v 2 V = V < V t M4 is ON i 4 = 0 v 4 = 0 Finally, from KVLs in no. 3. above, we have v o = V + v 3 = V. o, when both inputs are low, the output is HIH. ECE60L Lecture Notes, pring

14 If needed, we can go back and find the state of M2. Assume M2 is ON. This requires v 2 > V t. ince i 2 = 0 and M2 is ON, v 2 = 0 (M2 in Ohmic). From KVLs in no. 3. above, we have v o = v 1 + v 2 = V. This gives v 1 = V and v 2 = v 2 v 1 = V V = 0 < V t, a contradiction of our assumption of M2 being ON. Therefore, M2 should be OFF. v 1 = 0, v 2 = V We first find v and state of all transistors by using KVL in no. 1 above. v 1 = v 1 = 0 < V t M1 is OFF i 1 = 0 v 2 = v 2 v 1 = V v 1 M2 is? v 3 = v 1 V = V < V t M3 is ON v 4 = v 2 V = 0 > V t M4 is OFF i 4 = 0 ince i 1 = 0, by KCLs in no. 2 above, i 2 = i 1 = 0. Also, i 3 + i 4 = i 1 = 0 leading to i 4 = 0. We add the value of i to the table above and look for transistors that are ON and have i = 0. These transistors have to be in Ohmic region with v = 0. v 1 = v 1 = 0 < V t M1 is OFF i 1 = 0 v 2 = v 2 v 1 = V v 1 M2 is? i 2 = 0 v 3 = v 1 V = V < V t M3 is ON i 3 = 0 v 3 = 0 v 4 = v 2 V = 0 > V t M4 is OFF i 4 = 0 Finally, from KVLs in no. 3. above, we have v o = V + v 3 = V. o, when v 1 is LOW and v 2 is HIH, the output is HIH. We can go back and find the state of M2. We will find M2 to be ON (left for students). v 1 = V, v 2 = 0 We first find v and state of all transistors by using KVL in no. 1 above. v 1 = v 1 = V > V t M1 is ON v 2 = v 2 v 1 = v 1 < V t M2 is OFF i 2 = 0 v 3 = v 1 V = 0 > V t M3 is OFF i 3 = 0 v 4 = v 2 V = V < V t M4 is ON In the above, we used the fact that v 1 0. ince i 2 = 0, by KCLs in no. 2 above, i 1 = i 2 = 0. Also, i 3 + i 4 = i 2 = 0 leading to i 4 = 0. We add the value of i to the ECE60L Lecture Notes, pring

15 table above and look for transistors that are ON and have i = 0. These transistors have to be in Ohmic region with v = 0. v 1 = v 1 = V > V t M1 is ON v 2 = v 2 v 1 = v 1 < V t M2 is OFF i 2 = 0 v 2 = 0 v 3 = v 1 V = 0 > V t M3 is OFF i 3 = 0 v 3 = 0 v 4 = v 2 V = V < V t M4 is ON Finally, from KVLs in no. 3. above, we have v o = V + v 3 = V. o, when v 1 is HIH and v 2 is LOW, the output is HIH. v 1 = V, v 2 = V We first find v and state of all transistors by using KVL in no. 1 above. v 1 = v 1 = V > V t M1 is ON v 2 = v 2 v 1 = V v 1 M2 is? v 3 = v 1 V = 0 > V t M3 is OFF i 3 = 0 v 4 = v 2 V = 0 > V t M4 is OFF i 4 = 0 From KCLs in no. 2 above, i 2 = i 1 = i 3 + i 4 = 0. We add the value of i to the table above and look for transistors that are ON and have i = 0. These transistors have to be in Ohmic region with v = 0. v 1 = v 1 = V > V t M1 is ON i 1 = 0 v 1 = 0 v 2 = v 2 v 1 = V v 1 = V > V t M2 is ON i 2 = 0 v 2 = 0 v 3 = v 1 V = 0 > V t M3 is OFF i 3 = 0 v 4 = v 2 V = 0 > V t M4 is OFF i 4 = 0 In the above, we used v 1 = 0 to find the state of M2 leading to v 2 = 0. Finally, from KVLs in no. 3. above, we have v o = v 1 + v 1 = 0. o, when v 1 is HIH and v 2 is HIH, the output is LOW. From the truth table, the output of this gate is LOW only if both input states are HIH. Therefore, this is a NAN gate. ECE60L Lecture Notes, pring

16 CMO NOR ate Exercise: how that this is a NOR gate. M 4 V v 2 M 3 i 4 i 3 v o v 1 i 1 i 2 M 1 M 2 ECE60L Lecture Notes, pring

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2

More information

Electronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices

Electronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices Electronic Circuits 1 Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Three-terminal device whose voltage-current relationship is controlled by a third voltage

More information

Announcements. EE105 - Fall 2005 Microelectronic Devices and Circuits. Lecture Material. MOS CV Curve. MOSFET Cross Section

Announcements. EE105 - Fall 2005 Microelectronic Devices and Circuits. Lecture Material. MOS CV Curve. MOSFET Cross Section Announcements EE0 - Fall 00 Microelectronic evices and Circuits ecture 7 Homework, due today Homework due net week ab this week Reading: Chapter MO Transistor ecture Material ast lecture iode currents

More information

V. Transistors. 3.1 III. Bipolar-Junction (BJT) Transistors

V. Transistors. 3.1 III. Bipolar-Junction (BJT) Transistors V. Transistors 3.1 III. Bipolar-Junction (BJT) Transistors A bipolar junction transistor is formed by joining three sections of semiconductors with alternatiely different dopings. The middle section (base)

More information

Chapter 4 Field-Effect Transistors

Chapter 4 Field-Effect Transistors Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation

More information

ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

More information

Lecture 11: J-FET and MOSFET

Lecture 11: J-FET and MOSFET ENE 311 Lecture 11: J-FET and MOSFET FETs vs. BJTs Similarities: Amplifiers Switching devices Impedance matching circuits Differences: FETs are voltage controlled devices. BJTs are current controlled devices.

More information

MOS Transistor Properties Review

MOS Transistor Properties Review MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

Lecture 12: MOSFET Devices

Lecture 12: MOSFET Devices Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background

More information

ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits. 3. MOS Transistors ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

More information

EE105 - Fall 2005 Microelectronic Devices and Circuits

EE105 - Fall 2005 Microelectronic Devices and Circuits EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture

More information

Lecture 12: MOS Capacitors, transistors. Context

Lecture 12: MOS Capacitors, transistors. Context Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those

More information

Electronics Fets and Mosfets Prof D C Dube Department of Physics Indian Institute of Technology, Delhi

Electronics Fets and Mosfets Prof D C Dube Department of Physics Indian Institute of Technology, Delhi Electronics Fets and Mosfets Prof D C Dube Department of Physics Indian Institute of Technology, Delhi Module No. #05 Lecture No. #02 FETS and MOSFETS (contd.) In the previous lecture, we studied the working

More information

Chapter 6: Field-Effect Transistors

Chapter 6: Field-Effect Transistors Chapter 6: Field-Effect Transistors slamic University of Gaza Dr. Talal Skaik FETs vs. BJTs Similarities: Amplifiers Switching devices mpedance matching circuits Differences: FETs are voltage controlled

More information

FIELD EFFECT TRANSISTORS:

FIELD EFFECT TRANSISTORS: Chapter 10 FIEL EFFECT TRANITOR: MOFET The following overview gures describe important issues related to the most important electronic device. NUMBER OF ACTIVE EVICE/CHIP MOORE' LAW Gordon Moore, co-founder

More information

Charge Storage in the MOS Structure. The Inverted MOS Capacitor (V GB > V Tn )

Charge Storage in the MOS Structure. The Inverted MOS Capacitor (V GB > V Tn ) The Inverted MO Capacitor (V > V Tn ) We consider the surface potential as Þxed (ÒpinnedÓ) at φ s,max = - φ p φ(x).5 V. V V ox Charge torage in the MO tructure Three regions of operation: Accumulation:

More information

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET: Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)

More information

Lecture 11: MOS Transistor

Lecture 11: MOS Transistor Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Cross-section and layout

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated

More information

Transistors - a primer

Transistors - a primer ransistors - a primer What is a transistor? Solid-state triode - three-terminal device, with voltage (or current) at third terminal used to control current between other two terminals. wo types: bipolar

More information

Field effect = Induction of an electronic charge due to an electric field Example: Planar capacitor

Field effect = Induction of an electronic charge due to an electric field Example: Planar capacitor JFETs AND MESFETs Introduction Field effect = Induction of an electronic charge due to an electric field Example: Planar capacitor Why would an FET made of a planar capacitor with two metal plates, as

More information

Important! EE141- Fall 2002 Lecture 5. CMOS Inverter MOS Transistor Model

Important! EE141- Fall 2002 Lecture 5. CMOS Inverter MOS Transistor Model - Fall 00 Lecture 5 CMO Inverter MO Transistor Model Important! Lab 3 this week You must show up in one of the lab sessions this week If you don t show up you will be dropped from the class» Unless you

More information

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1

More information

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula

More information

Lecture 0: Introduction

Lecture 0: Introduction Lecture 0: Introduction Introduction q Integrated circuits: many transistors on one chip q Very Large Scale Integration (VLSI): bucketloads! q Complementary Metal Oxide Semiconductor Fast, cheap, low power

More information

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring

More information

Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS

Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS Operation and Modeling of The MOS Transistor Second Edition Yannis Tsividis Columbia University New York Oxford OXFORD UNIVERSITY PRESS CONTENTS Chapter 1 l.l 1.2 1.3 1.4 1.5 1.6 1.7 Chapter 2 2.1 2.2

More information

Lecture 3: CMOS Transistor Theory

Lecture 3: CMOS Transistor Theory Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors

More information

nmos IC Design Report Module: EEE 112

nmos IC Design Report Module: EEE 112 nmos IC Design Report Author: 1302509 Zhao Ruimin Module: EEE 112 Lecturer: Date: Dr.Zhao Ce Zhou June/5/2015 Abstract This lab intended to train the experimental skills of the layout designing of the

More information

The Devices. Jan M. Rabaey

The Devices. Jan M. Rabaey The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models

More information

FET Small-Signal Analysis

FET Small-Signal Analysis CHAPTER FET mall-ignal Analysis 9 9.1 INTROUCTION Field-effect transistor amplifiers provide an excellent voltage gain with the added feature of a high input impedance. They are also considered low-power

More information

Lecture 4: CMOS Transistor Theory

Lecture 4: CMOS Transistor Theory Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

More information

B.Supmonchai June 26, q Introduction of device basic equations. q Introduction of models for manual analysis.

B.Supmonchai June 26, q Introduction of device basic equations. q Introduction of models for manual analysis. June 26, 2004 oal of this chapter Chapter 2 MO Transistor Theory oonchuay upmonchai Integrated esign Application Research (IAR) Laboratory June 16th, 2004; Revised June 16th, 2005 q Present intuitive understanding

More information

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B) 1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed

More information

MOS Transistor. EE141-Fall 2007 Digital Integrated Circuits. Review: What is a Transistor? Announcements. Class Material

MOS Transistor. EE141-Fall 2007 Digital Integrated Circuits. Review: What is a Transistor? Announcements. Class Material EE-Fall 7 igital Integrated Circuits MO Transistor Lecture MO Transistor Model Announcements Review: hat is a Transistor? Lab this week! Lab next week Homework # is due Thurs. Homework # due next Thurs.

More information

Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

More information

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view) CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN

More information

DC and Transient Responses (i.e. delay) (some comments on power too!)

DC and Transient Responses (i.e. delay) (some comments on power too!) DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02 - CMOS Transistor Theory & the Effects of Scaling

More information

Lecture 17 Field-Effect Transistors 2

Lecture 17 Field-Effect Transistors 2 Lecture 17 Field-Effect Transistors chroder: Chapters, 4, 6 1/57 Announcements Homework 4/6: Is online now. ue Monday May 1st at 10:00am. I will return it the following Monday (8 th May). Homework 5/6:

More information

CMOS Inverter (static view)

CMOS Inverter (static view) Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:

More information

Lecture 2 Thin Film Transistors

Lecture 2 Thin Film Transistors Lecture 2 Thin Film Transistors 1/60 Announcements Homework 1/4: Will be online after the Lecture on Tuesday October 2 nd. Total of 25 marks. Each homework contributes an equal weight. All homework contributes

More information

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 First Exam Closed Book and Notes Fall 2002 September 27, 2002 General Instructions: 1. Write on one side of

More information

FIELD-EFFECT TRANSISTORS

FIELD-EFFECT TRANSISTORS FIEL-EFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancement-type N-MOS transistor 3 I-V characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation

More information

Course Administration. CPE/EE 427, CPE 527 VLSI Design I L04: MOS Transistors. Review: CMOS Process at a Glance

Course Administration. CPE/EE 427, CPE 527 VLSI Design I L04: MOS Transistors. Review: CMOS Process at a Glance Course Administration CPE/EE 7, CPE 7 VLI esign I L: MO Transistors epartment of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic ( www.ece.uah.edu/~milenka

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to

More information

Digital Electronics Part II - Circuits

Digital Electronics Part II - Circuits Digital Electronics Part - Circuits Dr.. J. Wassell Gates from Transistors ntroduction Logic circuits are non-linear, consequently we will introduce a graphical technique for analysing such circuits The

More information

ECE 497 JS Lecture - 12 Device Technologies

ECE 497 JS Lecture - 12 Device Technologies ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density

More information

Microelectronics Part 1: Main CMOS circuits design rules

Microelectronics Part 1: Main CMOS circuits design rules GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! med-amine.miled@polymtl.ca!

More information

Semiconductor Physics fall 2012 problems

Semiconductor Physics fall 2012 problems Semiconductor Physics fall 2012 problems 1. An n-type sample of silicon has a uniform density N D = 10 16 atoms cm -3 of arsenic, and a p-type silicon sample has N A = 10 15 atoms cm -3 of boron. For each

More information

Current mechanisms Exam January 27, 2012

Current mechanisms Exam January 27, 2012 Current mechanisms Exam January 27, 2012 There are four mechanisms that typically cause currents to flow: thermionic emission, diffusion, drift, and tunneling. Explain briefly which kind of current mechanisms

More information

MOS Transistor Theory

MOS Transistor Theory CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

More information

The Devices: MOS Transistors

The Devices: MOS Transistors The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor

More information

Designing Information Devices and Systems II Spring 2018 J. Roychowdhury and M. Maharbiz Discussion 1A

Designing Information Devices and Systems II Spring 2018 J. Roychowdhury and M. Maharbiz Discussion 1A EEC 16B esigning Information evices and ystems II pring 2018 J. Roychowdhury and M. Maharbiz iscussion 1A 1 igit Bases (N) p is used to indicate that the number N is expressed in base p. For example, (N)

More information

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the

More information

MOS Capacitors ECE 2204

MOS Capacitors ECE 2204 MOS apacitors EE 2204 Some lasses of Field Effect Transistors Metal-Oxide-Semiconductor Field Effect Transistor MOSFET, which will be the type that we will study in this course. Metal-Semiconductor Field

More information

EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR

EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX = - 4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3

More information

Lecture 5: CMOS Transistor Theory

Lecture 5: CMOS Transistor Theory Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics

More information

MOSFET Physics: The Long Channel Approximation

MOSFET Physics: The Long Channel Approximation MOSFET Physics: The ong Channel Approximation A basic n-channel MOSFET (Figure 1) consists of two heavily-doped n-type regions, the Source and Drain, that comprise the main terminals of the device. The

More information

MOS Transistor I-V Characteristics and Parasitics

MOS Transistor I-V Characteristics and Parasitics ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

More information

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Chapter 2 CMOS Transistor Theory Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor Jin-Fu Li, EE,

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

Practice 3: Semiconductors

Practice 3: Semiconductors Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given

More information

VLSI Design I; A. Milenkovic 1

VLSI Design I; A. Milenkovic 1 Review: implified CMO Inverter Process CPE/EE 7, CPE 7 VLI esign I L: MO Transistor cut line epartment of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic (

More information

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view) ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]

More information

Lecture 04 Review of MOSFET

Lecture 04 Review of MOSFET ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D

More information

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics t ti Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE105 Fall 2007

More information

Semiconductor Physics Problems 2015

Semiconductor Physics Problems 2015 Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and M-K Lee 1. The purest semiconductor crystals it is possible

More information

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis

More information

6.012 Electronic Devices and Circuits Spring 2005

6.012 Electronic Devices and Circuits Spring 2005 6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):

More information

Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

More information

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model - Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

Introduction and Background

Introduction and Background Analog CMOS Integrated Circuit Design Introduction and Background Dr. Jawdat Abu-Taha Department of Electrical and Computer Engineering Islamic University of Gaza jtaha@iugaza.edu.ps 1 Marking Assignments

More information

EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET

EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET EE 230 Lecture 33 Nonlinear Circuits and Nonlinear Devices Diode BJT MOSFET Review from Last Time: n-channel MOSFET Source Gate L Drain W L EFF Poly Gate oxide n-active p-sub depletion region (electrically

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless

More information

! PN Junction. ! MOS Transistor Topology. ! Threshold. ! Operating Regions. " Resistive. " Saturation. " Subthreshold (next class)

! PN Junction. ! MOS Transistor Topology. ! Threshold. ! Operating Regions.  Resistive.  Saturation.  Subthreshold (next class) ESE370: ircuitlevel Modeling, Design, and Optimization for Digital Systems Lec 7: September 20, 2017 MOS Transistor Operating Regions Part 1 Today! PN Junction! MOS Transistor Topology! Threshold! Operating

More information

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis

More information

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK SUBJECT CODE: EC 1354 SUB.NAME : VLSI DESIGN YEAR / SEMESTER: III / VI UNIT I MOS TRANSISTOR THEORY AND

More information

FET ( Field Effect Transistor)

FET ( Field Effect Transistor) NMO MO NMO MO Enhancement eletion Enhancement eletion N kanál Transistors tyes Field effect transistors Electronics and Microelectronics AE4B34EM MOFET MEFET JFET 7. ecture Uniolar transistor arameters

More information

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE15 Spring 28 Lecture

More information

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing

More information

Lecture 18 Field-Effect Transistors 3

Lecture 18 Field-Effect Transistors 3 Lecture 18 Field-Effect Transistors 3 Schroder: Chapters, 4, 6 1/38 Announcements Homework 4/6: Is online now. Due Today. I will return it next Wednesday (30 th May). Homework 5/6: It will be online later

More information

Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

More information

MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor

MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET Calculation of t and Important 2 nd Order Effects SmallSignal Signal MOSFET Model Summary Material from: CMOS LSI Design By Weste

More information

Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model

Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model Content- MOS Devices and Switching Circuits Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model A Cantoni 2009-2013 Digital Switching 1 Content- MOS

More information

The Intrinsic Silicon

The Intrinsic Silicon The Intrinsic ilicon Thermally generated electrons and holes Carrier concentration p i =n i ni=1.45x10 10 cm-3 @ room temp Generally: n i = 3.1X10 16 T 3/2 e -1.21/2KT cm -3 T= temperature in K o (egrees

More information

ECE315 / ECE515 Lecture-2 Date:

ECE315 / ECE515 Lecture-2 Date: Lecture-2 Date: 04.08.2016 NMOS I/V Characteristics Discussion on I/V Characteristics MOSFET Second Order Effect NMOS I-V Characteristics ECE315 / ECE515 Gradual Channel Approximation: Cut-off Linear/Triode

More information

Section 12: Intro to Devices

Section 12: Intro to Devices Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si

More information

Bipolar Junction Transistor (BJT) - Introduction

Bipolar Junction Transistor (BJT) - Introduction Bipolar Junction Transistor (BJT) - Introduction It was found in 1948 at the Bell Telephone Laboratories. It is a three terminal device and has three semiconductor regions. It can be used in signal amplification

More information

Introduction to Computer Engineering ECE 203

Introduction to Computer Engineering ECE 203 Introduction to Computer Engineering ECE 203 Northwestern University Department of Electrical Engineering and Computer Science Teacher: Robert Dick Office: L477 Tech Email: dickrp@ece.northwestern.edu

More information

Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur

Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture No. # 08 MOS Inverters - III Hello, and welcome to today

More information

Metal-oxide-semiconductor field effect transistors (2 lectures)

Metal-oxide-semiconductor field effect transistors (2 lectures) Metal-ide-semiconductor field effect transistors ( lectures) MOS physics (brief in book) Current-voltage characteristics - pinch-off / channel length modulation - weak inversion - velocity saturation -

More information

Department of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Due on March 01, 2018 at 7:00 PM

Department of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Due on March 01, 2018 at 7:00 PM Department of Electrical and Computer Engineering, Cornell University ECE 3150: Microelectronics Spring 2018 Homework 4 Due on March 01, 2018 at 7:00 PM Suggested Readings: a) Lecture notes Important Note:

More information

Classification of Solids

Classification of Solids Classification of Solids Classification by conductivity, which is related to the band structure: (Filled bands are shown dark; D(E) = Density of states) Class Electron Density Density of States D(E) Examples

More information

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins,

More information

ECEN474/704: (Analog) VLSI Circuit Design Spring 2018

ECEN474/704: (Analog) VLSI Circuit Design Spring 2018 ECEN474/704: (Analog) SI Circuit Design Spring 2018 ecture 2: MOS ransistor Modeling Sam Palermo Analog & Mixed-Signal Center exas A&M University Announcements If you haven t already, turn in your 0.18um

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor

More information