3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti

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1

2 Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics.

3 Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db + C db2 + C gd 2 + C gd 2,ov + C L At low frequency: A v = V out V in = g m g ds + g ds2 with g m = g ds = λi D 2µC ox W L I D A v = W 2µC ox L ( λ n + λ ) p I D 2

4 The dc gain increases as the square root of the bias current is decreases. This holds until the devices enter the subthreshold region In subthreshold the dc gain becomes independent of the biasing current: g m = I D A v = n kt q ( λ n + λ p )n kt q 3

5 At high frequency: Miller's theorem is applied to C 2 The output total capacitance is C 2 + C 3 The output resistance is / (g ds + g ds2 ) The transfer function has one pole ( )I D ω p = g + g ds ds2 = λ n + λ p C 2 + C 3 C 2 + C 3 The unity gain frequency increases as the square root of the bias current. W f T = 2π ω A (0) = g m p v = 2µ C ox L I D 2π C 2 + C 3 2π C 2 + C 3 Due to the Miller's theorem the input capacitance becomes: C in = C + C 2 ( A v ), if A v >> it can be a significant load for the stage driving it. 4

6 Example Simulate an inverter with active load (V DD = 5 V) as the following figure with BSIM3 Models. Find the dc gain and unity gain frequency. The achieved gain is about 47 db, the unity gain frequency is around 500 MHz, and the phase margin is 87 degrees. 5

7 Cascode The cascode gain stage is used to attenuate the Miller effect on node. V B > V sat, +V GS2 = V sat, +V Th,n +V sat,2 = = V Th,n + I W 2µ n C ox L + I W 2µ n C ox L 2 The bias voltage V B keeps M in the saturation region. V B < V out,min V sat,2 +V GS2 = V out,min +V Th,n 6

8 Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov C 3 = C gd 2 + C gd 2,ov + C gd 3 + C gd 3,ov + C db2 + C db3 + C L C 4 = C gs2 + C gs2,ov + C db + C sb2 For low frequency, neglecting g ds and g ds2 : g m v in = g m2 v = g ds3 v out A v = V out V in = g m g ds3 A = V V in = g m g m2 The Miller effect is significantly reduced if g m g m2. 7

9 At high frequency: The circuit has two nodes: the output and node. The capacitance at the output is C 3 The output impedance is / g ds3 (neglecting the impedance at the drain of M2) The capacitance at the node is (C 2 + C 4 ) The impedance at the node is / g m2 The pole associated to the output node is: The pole associated to the node is: f p, = 2π f p,out = 2π where ζ = + r ds3 / r ds2 = τ 2π = τ out 2π 2 g m2 g ds3 C 3 / ζ g m (C 2 + C 4 ) + g m2 C 2 8

10 since g m >> g ds, f p,out is dominant. The gain-bandwidth product is: f T = f p,dom A v = 2π g m C 3 If a good phase margin is needed, it must be: g m g < m2 / ζ C 3 (C 2 + C 4 ) + C 2 g m / g m2 This condition can be fulfilled by increasing C L. 9

11 Impedance at the drain of M2 v x = i x g ds + i x + g m2 v s2 g ds2 v s2 = i x g ds r d2 = v x i x = r ds + r ds2 + g m2 r ds g m2 r ds2 g ds 0

12 Impedance at the node,r : v x = r ds3 i x + r ds2 (i x g m2 v x ) r s2 = g m2 + r ds3 r ds2 = ζ g m2

13 Cascode with cascode load Transconductance gain stages. The gain is increased by increasing g m or r out. 2

14 In the improved version the transconductance of M is increased by the factor: V B and V B2 must keep M and M4 out the triode region V B > V sat, + V GS2 V B2 < V DD V sat,4 V GS3 The figure plots the folded structure useful if we need to rise the voltage of the source of M. I M 4 + I M5 I M 4 3

15 Small signal analysis The output impedance is (conventional version): r out = r dsg m2 r ds2 r ds g m2 r ds2 + r ds4 g m3 r ds3 (for the improved and folded version r ds must be replaced with r ds // r ds5 ) The dc gain is: A v = g m The circuit has three nodes: output node source of M2 source of M3 ( )( r ds4 g m3 r ) ds3 ( r ds g m2 r ) ds2 r ds 4 g m3 r ds3 r ds g m2 r ds2 + r ds4 g m3 r ds3 ( ) ( 2 g mr ) 2 ds 4

16 The transfer function will have three poles. The dominant one is the output pole f p,out = 2π r out C out f 2 = 2π r 2 C 2 f 3 = 2π C out, C 2, C 3 capacitances incident on nodes, 2, 3. At low frequency: ( )( r ds4 g m3 r ) ds3 r out = r dsg m2 r ds2 r ds g m2 r ds2 + r ds4 g m3 r ds3 r 2 = + r g r ds4 m3 ds3 // r ds g m2 r ds2 r 3 = + r dsg m2 r ds2 // r ds 4 g m3 r ds3 r out >> r 2, r 3 r 3 C 3 5

17 At high frequency: r 2 g m2 r 3 g m3 Output swing: The output swing is limited by the conditions for which one of the transistors of the stage is brought out of saturation V out,max = V B2 +V GS3 V sat3 V out,min = V B +V GS2 V sat2 V B and V B2 must keep M, M4, and M5 out of the triode region. 6

18 Example Simulate the folded cascode amplifier, shown in the following figure, with V DD = 3.5 V. Use the BSIM3V2 models to find the gain and the phase from input to output and from input to node 2. We observe that the gain and the phase plots of the output show a 20 db roll-off with a good phase margin (60 degrees). The low frequency gain is 77 db and the unity gain frequency is around 80 MHz. The behavior of the gain from the input to node 2 is interesting: above the dominant pole, it holds 4 db, just 2 db more than the expected value g m /g m2. At low freq. goes to 34 db. 7

19 Differential stage M, M2 in saturation with (W/L) = (W/L) 2 I = µc ox W ( V GS V ) 2 Th I 2 = µc ox W 2 L 2 L 2 ( V GS2 V ) 2 Th assume: V GS = V GS0 + v in 2 V GS2 = V GS0 v in 2 8

20 The output variable is the differential current: ΔI = I I 2 = µc ox 2 W L since the bias current can be expressed as: I SS = I + I 2 = µc ox W 2 L v ( in V GS0 V ) Th ( V GS0 V ) 2 Th W it results: ΔI = v in µc ox I SS for small signals: L Δi = v g in m with a common mode signal: i CM = g m v CM + 2g m r v in 2r CMRR = i d i CM 2g m r i 9

21 Example W Verify the equation ΔI = v in µc ox L Consider an n-channel differential pair with (W/L)=00 and I SS =00 µa. I SS The transconductance transfer function is fairly linear over a wide range of the input signal. It starts to saturate only when the input signal approaches the overdrive voltage of the differential pair (75 mv). 20

22 Source follower Used as buffer or as dc-level shifter at low frequency: ( g + g ds ds2)v out + g mb v out g m v gs = 0 hence: A v = v out v in = g m g m + g ds + g ds2 + g mb 2

23 If g m >> g ds + g ds2 + g mb then A v at high frequency: where: A v (s) C out = C L + C gd2 + C gd2ov + C db2 + C sb C = C gs + C gsov The output impedance is obtained by applying a test source v x at the output node. i x = (g ds + g ds2 + g mb + g m ) v x hence: r out = g m + g ds + g ds2 + g mb g m The output is not symmetrical. For n-channel input device C C + C out V out-max = V DD V GS V out-min = V sat2 22

24 Example Simulate the large signal behavior and derive the dc small signal voltage gain. I B = 0. ma and V DD = 3.3 V. The output voltage, practically, follows the input shifted by V GS. However due to the body effect, the value of V GS is not constant; it rises from 73 mv to.3 V. Therefore the input-output characteristic is not but 0.8. The figure shows also the dc gain: its value ranges from 0.74 to 0.86 quite well match as theoretical results. 23

25 Level shifter Essential for NMOS circuits, useful for CMOS circuits High-impedance level shift Low-impedance, or "battery", level shift High input impedances: 24

26 ΔV = V GS = 2L kw I +V Th = V ov +V Th Body effect neglected Threshold voltage variation effect ( V Th ± 50 mv) Input and output swing limitation Level shift threshold-independent: ΔV = 2 k L W ( I I ) 2 L W (assuming M in saturation and neglecting λ) usually V < V Th 2 I 2 25

27 Low Impedance: It behaves like a voltage source a) ΔV = V DS = 2L kw I +V Th b) ΔV = V GS +V GS2 = V Th +V Th2 + 2L kw I + 2L kw 2 I 2 a) r out = / g m b) affected by twice voltage threshold variation 26

28 Improved output stages Source follower with local feedback: i x = ( g m + g ds2 )v x + g m4 v 2 R out = v 2 = g m r ds3 v x g ( m + g m4 r ) ds3 + g ds2 27

29 Class AB push-pull: V 2 = V GS3 +V GS4 = V Th,n +V Th,p + I 5 W L = k W L 3 W L 2 = k W L With R L = 0 V GS V GS3, V GS2 V GS4, I = I 2 = ki 5 The output conductance is g m = g m + g m2 4 2L 3 µ n W 3 C ox + 2L 4 µ p W 4 C ox With resistive load, the drop voltage across the output resistance determines: V GS > V GS3, V GS2 < V GS4, I 2 = I I out 28

30 For a given load I 2 0; the output conductance becomes g out = g m In general an output stage has the following equivalent circuit: R out = R ( 2 out0 + α I out + α 2 I out +K ) It determines harmonic distortion. 29

31 Class AB push-pull with gain stage: V g V g2 if it is verified the condition: + g m4 g m5 << r ds6 30

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