Switching circuits: basics and switching speed


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1 ECE137B notes; copyright 2018 Switching circuits: basics and switching speed Mark Rodwell, University of California, Santa Barbara
2 Amplifiers vs. switching circuits Some transistor circuit might have V in vs. V out characteristics like this: The characteristics have a nearly linear amplification region: Plus limiting or clipping regions set by cutoff (minimum current) or "saturation" (minimum voltage)
3 Trivial example: CS stage with resistive load Here, the lower limit on V out and the upper limit by cutoff is set by saturation,
4 Amplifiers vs. switching circuits Biased in the linear region, and with a sufficiently small input, the circuit is an *amplifier* But, if the input is large, then the output switches between the clipping values. This is a *switching circuit*
5 Switching circuits vs. logic gates Logic gates are a particular *type* of switching circuit A general switching cicuit might have a different range for V and V. out...and might not perform *logic* in
6 Switching circuits vs. logic gates Logic gates are a particular *type* of switching circuit A logic gate will have the same range for V and V. out...and usually has multiple inputs to perform Boolean operations in CMOS NAND gate:
7 Switching circuits vs. logic gates Our focus here is on switching circuits, and on calculating DC V in V out transfer characteristics switching risetimes and falltimes You should have, by now, studied basic logic gates in other classes
8 Noise margins " Noise" margins: tolerance for component variation, EMI Input low level can vary over a considerable range, yet always produce nearly the same output "high" level Input high level can vary over a considerable range, yet always produce nearly the same output "low" level Defining margins precisely is difficult for general switching circuits....easier for logic
9 Another switching circuit: CMOS 1 V I I and V V V D, NFET D, PFET DS, PFET DD DS, NFET From these relationships, we obtain the loadline constructions above Both the positive and negative clipping limits, hence switched output voltage levels, are set by transistor saturation.
10 Another switch: emittercoupled pair One example of this: the digital 50 coaxial cable interface between the PRBS pulse generator and the LED/laser driver in lab project choice #2.
11 Another switch: emittercoupled pair Zo Zo There are also logic families using bipolar differential pairs, current mode logic, left, and emitter coupled logic, right
12 emittercoupled pair transfer characteristics The stated levels on the diagram are easily found. But, how do we find V in?
13 emittercoupled pair transfer characteristics slope IoRL / 4V T DC bias V at zero Volts, then apply a small signal: what is the gain? in g g g I / 2 V, A V / V g R / 2 I R / 4V m m1 m2 o T v out in m L o L T
14 emittercoupled pair transfer characteristics slope IoRL / 4V T height IR o L so, the slope of the switching region is I R / 4 V, while the output voltage swing is IR, so the input voltage range must be the ratio of these: V ( I R ) / ( I R / 4 V ) 4V 4 kt / q in o L o L T T o L o L T
15 emittercoupled pair: comments You can repeat this calculation for a differential input different V in We have assume that Q, Q don't saturate over the logic swing. 1 2 if they do, then this will change the V in V out characteristics
16 Limiting mechanisms: currentsteering We can design differential currentsteering circuits such that both V and V are set by cutoff. out, high out, low
17 Limiting mechanisms: CS or CE In these commonsourcelike and commonemitterlike circuits either or both V and V are set by saturation. out, high out, low
18 Limiting mechanisms: CS or CE When BJT's saturate, they usually store large amounts of minority carrier change. Switching speed is then very slow. With a few exceptions, saturation is avoided in bipolar switching circuits
19 Computing risetimes: charge control method Charge control method: hand estimate switching circuit delay, risetime Compute total charge on all capacitors at high Compute voltage on node at high level Compute change in charge rise/ fall delay rise/ fall V high Q high and low levels Q Q Q and voltage V V V If node is charged by constant current I, then charging is linear T Q / I and T T / 2 rise/ fall and low level V low Q low high low high low If node is charged through resistance R, then charging is exponential Equivalent capacitance C Q / V, time constant RC T 2.2 and T ln(2) delay
20 Charging through a current source The input voltage falls suddenly, turning the FET off. Let's ignore, just for now, the PFET knee voltage; treat as current source. Now, constant current charges capacitance. Charging is linear T Q / I and T T / 2 rise/ fall 0 delay rise/ fall
21 Charging through a resistance The input voltage falls suddenly, turning the FET off. Node is charged through resistance R; charging is exponential Equivalent capacitance C Q / V, time constant RC T rise/ fall 2.2 and T delay ln(2)
22 Example: Waveform at Q1 drain V in switches at t 0. We will estimate V ( t). D1
23 Example: Waveform at Q1 drain Note: 1) V ( t) initially swings negative: V ( t) couples to V ( t) though D1 in D1 a capacitive voltage divider between C and ( C, C, C ) 2) V ( t) then charges towards +1V. D1 Between VD 1= 0V and 0.8V, Q 2 D2 2 gd1 gd 2 gd 3 gs3 is a constantcurrent source Between V = 0.8V and 1V, Q acts as a resistance (saturation)
24 Example: Waveform at Q1 drain Switching time between A and C: 1st part: charging to 0.8V change in charge in: C A: Q 1V C: Q 0.8V C, Q 1.8V C gd1 gd1 gd1 gd1 C A: Q 0.8V C: Q 0V C, Q 0.8V C C gd 2 gd 2 gd 2 gd 2 gd 3 A: Q 1V Q 0.8V C, Q 1.8V C gd 3 gd 3 gd 3 C A: Q 0V C: Q 0.8V C, Q 0.8V C gs3 gs3 gs3 gd 3 Time for drain of Q1 to charge to 0.8V: T = 1.8V C 0.8V C 1.8V C 0.8V C 1mA 1 gd1 gd 2 gd 3 gd 3
25 Example: Waveform at Q1 drain Switching time between C and D: 2nd part: charging from 0.8V towards 1V C C: Q 0.8 D: Q 1V C, Q 0.2V C gd1 gd1 gd1 gd1 C C: Q 0V D: Q 0.2V C, Q 0.2V C C gd 2 gd 2 gd 2 gd 2 gd 3 C: Q 0.8V D: Q 1V C, Q 0.2V C gd 3 gd 3 gd 3 C C: Q 0.8V D: Q 1V C, Q 0.2V C gs3 gs3 gs3 gd 3 Effective capacitance : RDS, satceff RDS, sat Cgd1 Cgd 2 Cgd 3 Cgd 3 C = 0.2V C 0.2V C 0.2V C 0.2V C 0.2V=... eff gd1 gd 2 gd 3 gd 3 Time constant Exponential charging: V ( t) 0.8V+(1V 0.8V)(1 exp(( t T ) / )) D1 1
26 Example: bipolar differential switch Let us calculate the risetime at the base of Q3
27 Example: bipolar differential switch Let us calculate the risetime at the base of Q3 Times are relative to the time at which the collector current of Q2 switches to zero.
28 Example: bipolar differential switch Switching time between A and B: change in charge in: C A: Q V B: Q V C, Q ( V V ) C cb2 low cb2 high cb2 high low cb2 A: Q ( Vlow VCC ) B: Q ( Vhigh VCC ) Ccb3, Q ( Vhigh Vlow) Ccb3 C A: Q ( V V ) B: Q ( V V ) C, Q ( V V ) C je2 low 0 je2 high high je2 0 low je2 C A: Q 0 B: Q I, Q I diff 2 f 2 0 f 2 0 f 2 Effective capacitance: C = Q / ( V V ) eff high low ( V high V low ) C ( V V ) C ( V V ) C I ( V V ) cb2 high low cb3 0 low je2 0 f 2 high low
29 Example: bipolar differential switch Effective capacitance: V V I C C C C but V V I R 0 low 0 f 2 eff cb2 cb3 je2 high low 0 L Vhigh Vlow Vhigh Vlow Charging time constant: 0 low charge L eff L cb2 L cb3 L je2 f 2 high low Voltage waveform: V () t V b3 V V R C R C R C R C V V ( V V )(1 exp( t / )) low high low charge
30 Limitations of charge control 1) the method is very approximate 2) We do not predict the detailed shape of the switching waveform More detailed analysis can find secondary switching transients at one or move points within the overall waveform. In some cases, spikes are produced. This is more advanced material
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