ECE 145A/218A Power Amplifier Design Lectures. Power Amplifier Design 1
|
|
- Elisabeth Crawford
- 6 years ago
- Views:
Transcription
1 Power Amplifiers; Part 1 Class A Device Limitations Large signal output match Define efficiency, power-added efficiency Class A operating conditions Thermal resistance We have studied the design of small-signal amplifiers The designs were based on small-signal S-parameters. The output was often conjugately matched to increase gain. I DQ V DQ conjugate match: SS AC Load Line Re{ Z L }= Re Z OUT { } 5/4/07 1 of 18 Prof. S. Long
2 The small signal conjugate match leads to limitations on voltage and current swing. Not important for SS amps, but crucial for power amps. ΔV << V DQ ΔI << I DQ Power amps require a large-signal design methodology: ΔV and ΔI are significant compared with V DQ and I DQ. Power Amp Objective: Get the largest ΔV and ΔI without: 1. Clipping large saturation of gain; - distortion generated. Destroying the device. avoid breakdown I MAX must be within device specs P DISS must not overheat the device 5/4/07 of 18 Prof. S. Long
3 Device limitations and clipping. Every device has maximum voltage and current limits. Breakdown voltage: Electric field large enough to generate electron-hole pair qv > E gap of semiconductor. Electrons injected into channel from source or into collector from emitter are accelerated in high field. S G D Electric field electrons holes Collisions transfer energy to Si atoms. Electron is released, accelerates creates hole. Electron-hole pairs are then accelerated further generating more electrons, holes. This leads to rapid increase in current for voltages beyond breakdown AVALANCHE BREAKDOWN!!! 5/4/07 3 of 18 Prof. S. Long
4 Maximum Current GaAs FET: I DSS for FET = I GS = 0 I D qnv sat n ( V GS V T ) m also must avoid forward gate conduction on MESFET or PHEMT Si MOSFET: Imax specified by foundry or manufacturer Also must avoid gate oxide breakdown BJT: I MAX is limited by collector electric field profile when mobile charge fixed charge, Ε= qn ( D n)x ε electric field 0 transit delay f T We will discuss thermal limitations later. Heat generation will limit the operation of all device types 5/4/07 4 of 18 Prof. S. Long
5 Conjugate Match Revisited. + I d jb I L V OUT - R ds R L -jb We have learned that max. power transfer occurs when R L = R ds. true for small signal condition -no device limitations. But what happens when we have limitations on voltage and current? Suppose V max =10V, I max =1A, R ds =100Ω 1. Conjugate Match. R L R ds = 50Ω =R L V OUT = I max R L = 50V! clearly, I max can t be reached since V max =10V ( ) P OUT = V max / R L = = 1 4W 5/4/07 5 of 18 Prof. S. Long
6 . Load Line Match. R L = V max =10Ω I max P OUT = 5 0 =1.5W This uses the maximum capability of the device more realistically, improvement of -3 db is typical Here you can see the large signal load line with slope 1/R L V Dsat I MAX I DQ V DQ V BR 5/4/07 6 of 18 Prof. S. Long
7 We have now shown that different criteria are used for output matching a power amp than a small signal amp. You may have noticed that the large signal load line doesn t extend to V DS = 0. To avoid excessive distortion, we must also take into account the knee voltage (V Dsat or V CEsat ). Clipping will occur if the drain voltage swing extends into the ohmic region of the device characteristic. Thus, our definition of the large signal load line resistance must take this into account: RL VBR Vknee Imax = for maximum voltage swing Some additional PA concepts Efficiency η = POUT PDC x 100% Power Dissipation PD = PDC POUT Must be removed as heat. P D can also limit the maximum P OUT T max = 150 o C 5/4/07 7 of 18 Prof. S. Long
8 P DC P IN P OUT Power-Added-Efficiency PAE POUT P = IN PDC Gain should be at least 10dB to avoid significant reduction in PAE. Efficiency is important because 1) PA s are used for power ) Wasted power must be removed as heat 3) Wasted power consumes batteries faster Suppose Pout = 10 kw (FM broadcast transmitter) η (%) P D (kw) P DC (kw) /4/07 8 of 18 Prof. S. Long
9 First PA: Class A. Most similar to small-signal amp. V DQ and I DQ set so that amp is always on. "on" time conduction angle = π = π T Case 1 : resistive load. bad idea for PA, but familiar. (we will refer later to this V DC as V DC1 ) V DC R L I MAX = I CQ I CQ V CQ =V DC / V DC = V BR Neglecting V knee, we find RL V = BR = Imax VDC ICQ 5/4/07 9 of 18 Prof. S. Long
10 I C ()= θ I CQ + I m sinθ (θ = ωt) Maximum value of I m = (just begins to clip) I CQ We can see that the average DC component is ICQ and the fundamental component of current is Im, OR: We can use Fourier integrals to determine P DC and P OUT. The DC term (a 0 ) can be used to calculate power dissipation: π VDC PDC = ic ( θ ) dθ π 0 V π DC = I + I sinθ dθ = V I π 0 CQ m DC CQ constant DC power, constant input current. You can use Fourier integrals to also find coefficients for fundamental and harmonics. T = π T/ 1 a0 = f ( x) dx T T T an = f ( x) sin( nx) dx T T T bn = f ( x) cos( nx) dx T T 5/4/07 10 of 18 Prof. S. Long
11 Power at fundamental frequency ω: n =1 π π 1 ai i I sin d I π 1 m = OUT ( ω) = m θ θ = m π sin θdθ = π π P OUT = 1 Re V * { mi m }= 1 V mi m V m = V DC ; I m = V m R L 1 V I V I 8 DC1 max DC1 max Thus: Pout = = R L and, P OUT = I mr L = I CQ = V DC 8R L since I max V = I CQ, BR DC V = V, R BR L = I max In terms of device limitations, the maximum output power is P OUT = 1 I max 4 V BR I max = V BRI max 8 5/4/07 11 of 18 Prof. S. Long
12 what about harmonics? n >1? 1 Iman = Imsinθ sin n θ d θ =0 π π - π with no nonlinearity in I c ( θ ), no harmonic currents. Efficiency: P DC = V DC I CQ = V DC R L I CQ V = R DC L so η = P OUT P DC = 1 4 ( 5% ) max! If we AC couple the load resistor: We have current divider. Efficiency can be much worse. so, bad idea for any power application 5/4/07 1 of 18 Prof. S. Long
13 For RF applications we can do much better. Case : inductive load. V DC = V DC = V DC1 / V DC R L I CQ V CQ =V DC V DC = V BR now, RL VBR Imax VDC ICQ = = (no change -assume same device limitations) but: VDC VDC I max VBRI max OUT RL 4 8 VDC 1 DC = DC CQ = = DC1 RL P = = = same as case 1 P V I P η = 1 ( 50% ) 5/4/07 13 of 18 Prof. S. Long
14 we have P OUT ( case )= P OUT ( case 1) but P DC ( case )= 1 P DC( case 1) because: ( ) V case = ( 1) DC 1 V DC case Thus, the inductive feed allows the amplifier to produce the same output power with half the supply voltage. This also applies to tuned amplifiers. So: 50% of P DC can be converted into useful output power if we swing rail to rail. Alternatively, we can get times more P OUT for the same V DC if the device has sufficient breakdown voltage. (twice the voltage; twice the R L ) V Vm = VDC RL = I DC max V V I V I Pout = = = R 4 DC DC max DC1 max L 5/4/07 14 of 18 Prof. S. Long
15 But, what about a more typical situation where we have a large range of signal powers to be amplified? How much power gets dissipated in the device? PD = PDC POUT (heat in transistor) Power P D P = V DC DC I CQ (constant) Pout = V DC /R L Pout I m I CQ = V DC /R L We have doubled the efficiency (now 50%), but still have maximum power dissipated in device at zero input. undesirable for power amp where high powers may be required. ok for driver stage low power; highly linear. 5/4/07 15 of 18 Prof. S. Long
16 Thermal Limitations T J 150 C why? reliability failure mechanisms are strongly temperature dependent MTTF e Ea/KT Ea = activation energy Thermal model. T J <150 C R TH J C T C package heat sink R THC HS T HS R TH HS A T Ambient air T = 5 C 5/4/07 16 of 18 Prof. S. Long
17 Thermal Resistance relates T to power dissipation (like ohm s law for heat) T = R P + T J TH, J C D C = ( R + R + R ) P + T TH, J C TH, C HS TH, HS A D A R TH has units of C /watt T J R TH JC T C R THC HS T HS R TH HS A T A 5/4/07 17 of 18 Prof. S. Long
18 Class A Power Amplifier Summary 1. Device limitations (V BR and I MAX and T MAX ) constrain the design for a PA. R opt V = BR V I MAX knee * not Γ OUT! Large signal load line match. T MAX =150 C for reliable operation 3. Waste power, P D = P DC P OUT is converted to heat. Must be removed 4. Efficiency, P OUT P DC, or PAE, P OUT P IN P DC are critical for PAs. For Class A with same output power, same R L : Resistive DC feed (1) Inductive feed () V DC V DC1 V DC = V DC1 / η 5% max 50% max P OUT VDC1 V DC max 8R R L = VBR VDC1 I I L V V = R 8R DC DC1 up to V BR up to V BR MAX BR DC DC1 = = = CQ L V V V I I I MAX CQ CQ L 5/4/07 18 of 18 Prof. S. Long
Lecture 11: J-FET and MOSFET
ENE 311 Lecture 11: J-FET and MOSFET FETs vs. BJTs Similarities: Amplifiers Switching devices Impedance matching circuits Differences: FETs are voltage controlled devices. BJTs are current controlled devices.
More informationESE319 Introduction to Microelectronics. Output Stages
Output Stages Power amplifier classification Class A amplifier circuits Class A Power conversion efficiency Class B amplifier circuits Class B Power conversion efficiency Class AB amplifier circuits Class
More information3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti
Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +
More informationHomework Assignment 09
Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3-dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =
More informationBiasing the CE Amplifier
Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th
More informationCircle the one best answer for each question. Five points per question.
ID # NAME EE-255 EXAM 3 November 8, 2001 Instructor (circle one) Talavage Gray This exam consists of 16 multiple choice questions and one workout problem. Record all answers to the multiple choice questions
More informationR. Ludwig and G. Bogdanov RF Circuit Design: Theory and Applications 2 nd edition. Figures for Chapter 6
R. Ludwig and G. Bogdanov RF Circuit Design: Theory and Applications 2 nd edition Figures for Chapter 6 Free electron Conduction band Hole W g W C Forbidden Band or Bandgap W V Electron energy Hole Valence
More information6.012 Electronic Devices and Circuits
Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to
More informationChapter 6: Field-Effect Transistors
Chapter 6: Field-Effect Transistors slamic University of Gaza Dr. Talal Skaik FETs vs. BJTs Similarities: Amplifiers Switching devices mpedance matching circuits Differences: FETs are voltage controlled
More informationVidyalankar S.E. Sem. III [EXTC] Analog Electronics - I Prelim Question Paper Solution
. (a) S.E. Sem. [EXTC] Analog Electronics - Prelim Question Paper Solution Comparison between BJT and JFET BJT JFET ) BJT is a bipolar device, both majority JFET is an unipolar device, electron and minority
More informationHomework Assignment 08
Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance
More informationBipolar Junction Transistor (BJT) - Introduction
Bipolar Junction Transistor (BJT) - Introduction It was found in 1948 at the Bell Telephone Laboratories. It is a three terminal device and has three semiconductor regions. It can be used in signal amplification
More informationLecture 23: NorCal 40A Power Amplifier. Thermal Modeling.
Whites, EE 322 Lecture 23 Page 1 of 13 Lecture 23: NorCal 40A Power Amplifier. Thermal Modeling. Recall from the last lecture that the NorCal 40A uses a Class C power amplifier. From Fig. 10.3(b) the collector
More informationEE 330 Lecture 22. Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits
EE 330 Lecture 22 Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits Exam 2 Friday March 9 Exam 3 Friday April 13 Review Session for Exam 2: 6:00
More informationELEC 3908, Physical Electronics, Lecture 18. The Early Effect, Breakdown and Self-Heating
ELEC 3908, Physical Electronics, Lecture 18 The Early Effect, Breakdown and Self-Heating Lecture Outline Previous 2 lectures analyzed fundamental static (dc) carrier transport in the bipolar transistor
More informationElectronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices
Electronic Circuits 1 Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Three-terminal device whose voltage-current relationship is controlled by a third voltage
More information6.012 Electronic Devices and Circuits
Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless
More informationMOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA
MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing
More informationLecture 6: 2D FET Electrostatics
Lecture 6: 2D FET Electrostatics 2016-02-01 Lecture 6, High Speed Devices 2014 1 Lecture 6: III-V FET DC I - MESFETs Reading Guide: Liu: 323-337 (he mainly focuses on the single heterostructure FET) Jena:
More informationChapter 3 Output stages
Chapter 3 utput stages 3.. Goals and properties 3.. Goals and properties deliver power into the load with good efficacy and small power dissipate on the final transistors small output impedance maximum
More informationECE 304: Design Issues for Voltage Follower as Output Stage S&S Chapter 14, pp
ECE 34: Design Issues for oltage Follower as Output Stage S&S Chapter 14, pp. 131133 Introduction The voltage follower provides a good buffer between a differential amplifier and a load in two ways: 1.
More informationOperational Amplifiers
Operational Amplifiers A Linear IC circuit Operational Amplifier (op-amp) An op-amp is a high-gain amplifier that has high input impedance and low output impedance. An ideal op-amp has infinite gain and
More informationECE-305: Fall 2017 MOS Capacitors and Transistors
ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue
More informationECE 497 JS Lecture - 12 Device Technologies
ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density
More informationEE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET
EE 230 Lecture 33 Nonlinear Circuits and Nonlinear Devices Diode BJT MOSFET Review from Last Time: n-channel MOSFET Source Gate L Drain W L EFF Poly Gate oxide n-active p-sub depletion region (electrically
More information55:041 Electronic Circuits The University of Iowa Fall Final Exam
Final Exam Name: Score Max: 135 Question 1 (1 point unless otherwise noted) a. What is the maximum theoretical efficiency for a class-b amplifier? Answer: 78% b. The abbreviation/term ESR is often encountered
More informationAppendix 1: List of symbols
Appendix 1: List of symbols Symbol Description MKS Units a Acceleration m/s 2 a 0 Bohr radius m A Area m 2 A* Richardson constant m/s A C Collector area m 2 A E Emitter area m 2 b Bimolecular recombination
More informationLecture 3: Transistor as an thermonic switch
Lecture 3: Transistor as an thermonic switch 2016-01-21 Lecture 3, High Speed Devices 2016 1 Lecture 3: Transistors as an thermionic switch Reading Guide: 54-57 in Jena Transistor metrics Reservoir equilibrium
More informationChapter 13 Small-Signal Modeling and Linear Amplification
Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors
More informationChapter 4 Field-Effect Transistors
Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationà FIELD EFFECT TRANSISTORS
Prof.M.G.Guvench à FIELD EFFECT TRANSISTORS ü FET: CONTENTS Principles of Operation Models: DC, S.S.A.C. and SPICE Applications: AC coupled S.S. Amplifiers ü FET: NAMES JFET Junction Field Effect Transistor
More informationFinal Examination EE 130 December 16, 1997 Time allotted: 180 minutes
Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and cross-sectional area 100µm 2
More informationCARLETON UNIVERSITY. FINAL EXAMINATION December DURATION 3 HOURS No. of Students 130
ALETON UNIVESITY FINAL EXAMINATION December 005 DUATION 3 HOUS No. of Students 130 Department Name & ourse Number: Electronics ELE 3509 ourse Instructor(s): Prof. John W. M. ogers and alvin Plett AUTHOIZED
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationEE105 Fall 2014 Microelectronic Devices and Circuits
EE05 Fall 204 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Terminal Gain and I/O Resistances of BJT Amplifiers Emitter (CE) Collector (CC) Base (CB)
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationTOSHIBA Field Effect Transistor Silicon N Channel MOS Type (π MOSIII) 2SK2610
TOSHIBA Field Effect Transistor Silicon N Channel MOS Type (π MOSIII) Chopper Regulator, DC DC Converter and Motor Drive Applications Unit: mm Low drain source ON resistance : RDS (ON) = 2.3 Ω (typ.) High
More informationThe Devices. Jan M. Rabaey
The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models
More informationElectronic Circuits. Bipolar Junction Transistors. Manar Mohaisen Office: F208 Department of EECE
Electronic Circuits Bipolar Junction Transistors Manar Mohaisen Office: F208 Email: manar.subhi@kut.ac.kr Department of EECE Review of Precedent Class Explain the Operation of the Zener Diode Explain Applications
More informationReview of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model
Content- MOS Devices and Switching Circuits Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model A Cantoni 2009-2013 Digital Switching 1 Content- MOS
More informationDISCRETE SEMICONDUCTORS DATA SHEET. BLF145 HF power MOS transistor
DISCRETE SEMICONDUCTORS DATA SHEET September 1992 FEATURES High power gain Low noise figure Good thermal stability Withstands full load mismatch. DESCRIPTION Silicon N-channel enhancement mode vertical
More informationChapter 10 Instructor Notes
G. izzoni, Principles and Applications of lectrical ngineering Problem solutions, hapter 10 hapter 10 nstructor Notes hapter 10 introduces bipolar junction transistors. The material on transistors has
More informationLecture 8: Ballistic FET I-V
Lecture 8: Ballistic FET I-V 1 Lecture 1: Ballistic FETs Jena: 61-70 Diffusive Field Effect Transistor Source Gate L g >> l Drain Source V GS Gate Drain I D Mean free path much shorter than channel length
More informationLecture 7: Transistors and Amplifiers
Lecture 7: Transistors and Amplifiers Hybrid Transistor Model for small AC : The previous model for a transistor used one parameter (β, the current gain) to describe the transistor. doesn't explain many
More informationEE 330 Lecture 25. Amplifier Biasing (precursor) Two-Port Amplifier Model
EE 330 Lecture 25 Amplifier Biasing (precursor) Two-Port Amplifier Model Review from Last Lecture Exam Schedule Exam 2 Friday March 24 Review from Last Lecture Graphical Analysis and Interpretation 2 OX
More informationCLASS C. James Buckwalter 1
CLASS C James Buckwalter 1 Class-C Amplifier Like class-b, I quiescent = 0 Unlike class-b, conduction angle < 180 deg Gain is low since device is turned on for only a short period Iout Imax Vmin Vmax ut
More informationClass E Design Formulas V DD
Class E Design Formulas V DD RFC C L+X/ω V s (θ) I s (θ) Cd R useful functions and identities Units Constants Table of Contents I. Introduction II. Process Parameters III. Inputs IV. Standard Class E Design
More informationMOSFET Physics: The Long Channel Approximation
MOSFET Physics: The ong Channel Approximation A basic n-channel MOSFET (Figure 1) consists of two heavily-doped n-type regions, the Source and Drain, that comprise the main terminals of the device. The
More informationDigital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationECE 205: Intro Elec & Electr Circuits
ECE 205: Intro Elec & Electr Circuits Final Exam Study Guide Version 1.00 Created by Charles Feng http://www.fenguin.net ECE 205: Intro Elec & Electr Circuits Final Exam Study Guide 1 Contents 1 Introductory
More informationFinal Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013.
Final Exam Name: Max: 130 Points Question 1 In the circuit shown, the op-amp is ideal, except for an input bias current I b = 1 na. Further, R F = 10K, R 1 = 100 Ω and C = 1 μf. The switch is opened at
More information55:041 Electronic Circuits The University of Iowa Fall Exam 2
Exam 2 Name: Score /60 Question 1 One point unless indicated otherwise. 1. An engineer measures the (step response) rise time of an amplifier as t r = 0.35 μs. Estimate the 3 db bandwidth of the amplifier.
More informationin Electronic Devices and Circuits
in Electronic Devices and Circuits Noise is any unwanted excitation of a circuit, any input that is not an information-bearing signal. Noise comes from External sources: Unintended coupling with other
More informationProblem 9.20 Threshold bias for an n-channel MOSFET: In the text we used a criterion that the inversion of the MOSFET channel occurs when V s = ;2 F w
Prof. Jasprit Singh Fall 2001 EECS 320 Homework 11 The nals for this course are set for Friday December 14, 6:30 8:30 pm and Friday Dec. 21, 10:30 am 12:30 pm. Please choose one of these times and inform
More informationELEN 610 Data Converters
Spring 04 S. Hoyos - EEN-60 ELEN 60 Data onverters Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group Spring 04 S. Hoyos - EEN-60 Electronic Noise Signal to Noise ratio SNR Signal Power
More informationSOME USEFUL NETWORK THEOREMS
APPENDIX D SOME USEFUL NETWORK THEOREMS Introduction In this appendix we review three network theorems that are useful in simplifying the analysis of electronic circuits: Thévenin s theorem Norton s theorem
More informationField effect = Induction of an electronic charge due to an electric field Example: Planar capacitor
JFETs AND MESFETs Introduction Field effect = Induction of an electronic charge due to an electric field Example: Planar capacitor Why would an FET made of a planar capacitor with two metal plates, as
More informationID # NAME. EE-255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom
ID # NAME EE-255 EXAM 3 April 7, 1998 Instructor (circle one) Ogborn Lundstrom This exam consists of 20 multiple choice questions. Record all answers on this page, but you must turn in the entire exam.
More informationSection 1: Common Emitter CE Amplifier Design
ECE 3274 BJT amplifier design CE, CE with Ref, and CC. Richard Cooper Section 1: CE amp Re completely bypassed (open Loop) Section 2: CE amp Re partially bypassed (gain controlled). Section 3: CC amp (open
More informationDISCRETE SEMICONDUCTORS DATA SHEET. BLF521 UHF power MOS transistor
DISCRETE SEMICONDUCTORS DATA SHEET November 1992 FEATURES PIN CONFIGURATION High power gain Easy power control ook, halfpage 1 Gold metallization Good thermal stability Withstands full load mismatch Designed
More informationS.E. Sem. III [ETRX] Electronic Circuits and Design I
S.E. Sem. [ETRX] Electronic ircuits and Design Time : 3 Hrs.] Prelim Paper Solution [Marks : 80 Q.1(a) What happens when diode is operated at high frequency? [5] Ans.: Diode High Frequency Model : This
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon
More informationCharge-Storage Elements: Base-Charging Capacitance C b
Charge-Storage Elements: Base-Charging Capacitance C b * Minority electrons are stored in the base -- this charge q NB is a function of the base-emitter voltage * base is still neutral... majority carriers
More informationLecture 12: MOSFET Devices
Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
More informationDEPARTMENT OF ECE UNIT VII BIASING & STABILIZATION AMPLIFIER:
UNIT VII IASING & STAILIZATION AMPLIFIE: - A circuit that increases the amplitude of given signal is an amplifier - Small ac signal applied to an amplifier is obtained as large a.c. signal of same frequency
More informationTypical example of the FET: MEtal Semiconductor FET (MESFET)
Typical example of the FET: MEtal Semiconductor FET (MESFET) Conducting channel (RED) is made of highly doped material. The electron concentration in the channel n = the donor impurity concentration N
More information5. EXPERIMENT 5. JFET NOISE MEASURE- MENTS
5. EXPERIMENT 5. JFET NOISE MEASURE- MENTS 5.1 Object The objects of this experiment are to measure the spectral density of the noise current output of a JFET, to compare the measured spectral density
More information1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp)
HW 3 1. (50 points, BJT curves & equivalent) For the 2N3904 =(npn) and the 2N3906 =(pnp) a) Obtain in Spice the transistor curves given on the course web page except do in separate plots, one for the npn
More informationSpring Semester 2012 Final Exam
Spring Semester 2012 Final Exam Note: Show your work, underline results, and always show units. Official exam time: 2.0 hours; an extension of at least 1.0 hour will be granted to anyone. Materials parameters
More informationSwitching circuits: basics and switching speed
ECE137B notes; copyright 2018 Switching circuits: basics and switching speed Mark Rodwell, University of California, Santa Barbara Amplifiers vs. switching circuits Some transistor circuit might have V
More informationMetal-oxide-semiconductor field effect transistors (2 lectures)
Metal-ide-semiconductor field effect transistors ( lectures) MOS physics (brief in book) Current-voltage characteristics - pinch-off / channel length modulation - weak inversion - velocity saturation -
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationEE105 - Fall 2006 Microelectronic Devices and Circuits. Some Administrative Issues
EE105 - Fall 006 Microelectronic evices and Circuits Prof. Jan M. Rabaey (jan@eecs Lecture 8: MOS Small Signal Model Some Administrative Issues REIEW Session Next Week Tu Sept 6 6:00-7:30pm; 060 alley
More informationSECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University
NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationCommon Drain Stage (Source Follower) Claudio Talarico, Gonzaga University
Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage v gs v i - v o V DD v bs - v o R S Vv IN i v i G C gd C+C gd gb B&D v s vv OUT o + V S I B R L C L v gs - C
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type
More informationModeling of Devices for Power Amplifier Applications
Modeling of Devices for Power Amplifier Applications David E. Root Masaya Iwamoto John Wood Contributions from Jonathan Scott Alex Cognata Agilent Worldwide Process and Technology Centers Santa Rosa, CA
More informationECE315 / ECE515 Lecture-2 Date:
Lecture-2 Date: 04.08.2016 NMOS I/V Characteristics Discussion on I/V Characteristics MOSFET Second Order Effect NMOS I-V Characteristics ECE315 / ECE515 Gradual Channel Approximation: Cut-off Linear/Triode
More informationDISCRETE SEMICONDUCTORS DATA SHEET. BLF245 VHF power MOS transistor
DISCRETE SEMICONDUCTORS DATA SHEET September 1992 FEATURES High power gain Low noise figure Easy power control Good thermal stability Withstands full load mismatch. DESCRIPTION Silicon N-channel enhancement
More informationEE 330 Lecture 25. Small Signal Modeling
EE 330 Lecture 25 Small Signal Modeling Review from Last Lecture Amplification with Transistors From Wikipedia: Generall, an amplifier or simpl amp, is an device that changes, usuall increases, the amplitude
More informationTunnel Diodes (Esaki Diode)
Tunnel Diodes (Esaki Diode) Tunnel diode is the p-n junction device that exhibits negative resistance. That means when the voltage is increased the current through it decreases. Esaki diodes was named
More informationECE 305: Fall MOSFET Energy Bands
ECE 305: Fall 2016 MOSFET Energy Bands Professor Peter Bermel Electrical and Computer Engineering Purdue University, West Lafayette, IN USA pbermel@purdue.edu Pierret, Semiconductor Device Fundamentals
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationDISCRETE SEMICONDUCTORS DATA SHEET. BLF543 UHF power MOS transistor
DISCRETE SEMICONDUCTORS DATA SHEET October 1992 FEATURES High power gain Easy power control Good thermal stability Gold metallization ensures excellent reliability Designed for broadband operation. DESCRIPTION
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationElectronic Devices and Circuits Lecture 18 - Single Transistor Amplifier Stages - Outline Announcements. Notes on Single Transistor Amplifiers
6.012 Electronic Devices and Circuits Lecture 18 Single Transistor Amplifier Stages Outline Announcements Handouts Lecture Outline and Summary Notes on Single Transistor Amplifiers Exam 2 Wednesday night,
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More informationCHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN. Hà Nội, 9/24/2012
1 CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN Hà Nội, 9/24/2012 Chapter 3: MOSFET 2 Introduction Classifications JFET D-FET (Depletion MOS) MOSFET (Enhancement E-FET) DC biasing Small signal
More informationLecture 050 Followers (1/11/04) Page ECE Analog Integrated Circuits and Systems II P.E. Allen
Lecture 5 Followers (1/11/4) Page 51 LECTURE 5 FOLLOWERS (READING: GHLM 344362, AH 221226) Objective The objective of this presentation is: Show how to design stages that 1.) Provide sufficient output
More information7. DESIGN OF AC-COUPLED BJT AMPLIFIERS FOR MAXIMUM UNDISTORTED VOLTAGE SWING
à 7. DESIGN OF AC-COUPLED BJT AMPLIFIERS FOR MAXIMUM UNDISTORTED VOLTAGE SWING Figure. AC coupled common emitter amplifier circuit ü The DC Load Line V CC = I CQ + V CEQ + R E I EQ I EQ = I CQ + I BQ I
More informationHigh-to-Low Propagation Delay t PHL
High-to-Low Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (n-channel) immediately switches from cutoff to saturation; the p-channel pull-up switches from triode to
More informationDISCRETE SEMICONDUCTORS DATA SHEET. BLF246 VHF power MOS transistor Oct 21. Product specification Supersedes data of September 1992
DISCRETE SEMICONDUCTORS DATA SHEET Supersedes data of September 1992 1996 Oct 21 FEATURES High power gain Low noise figure Easy power control Good thermal stability Withstands full load mismatch. PINNING
More informationCapacitors Diodes Transistors. PC200 Lectures. Terry Sturtevant. Wilfrid Laurier University. June 4, 2009
Wilfrid Laurier University June 4, 2009 Capacitor an electronic device which consists of two conductive plates separated by an insulator Capacitor an electronic device which consists of two conductive
More informationLecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)
More informationN-Channel Enhancement-Mode Vertical DMOS FET
N-Channel Enhancement-Mode Vertical DMOS FET Features Free from secondary breakdown Low power drive requirement Ease of paralleling Low C ISS and fast switching speeds Excellent thermal stability Integral
More informationLecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation
Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Text sec 1.2 pp. 28-32; sec 3.2 pp. 128-129 Current source Ideal goal Small signal model: Open
More information6.012 Electronic Devices and Circuits Spring 2005
6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):
More information