ESE 570: Digital Integrated Circuits and VLSI Fundamentals

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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1

2 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation! Level 1 Model 2

3 MOS Capacitor with External Bias! Three Regions of Operation: " Accumulation Region V G < 0 (Cutoff) " Depletion Region V G > 0, small (Subthreshold) " Inversion Region V G V T, large (Above Threshold) V G V T Cutoff/Subthreshold Above threshold Penn ESE 570 Spring 2018 Khanna 3

4 2terminal MOS Cap # 3terminal nmos VS V G V D depletion region Penn ESE 570 Spring 2018 Khanna 4

5 nmos = MOS cap + source/drain V SB = 0 V S V G V D Penn ESE 570 Spring 2018 Khanna 5

6 Review: Threshold Voltage for V SB = 0 V T =V T 0 = Φ GC Q ox C ox 2Φ F Q B0 C ox for V SB!= 0 V T = V T 0 +γ ( 2Φ F V SB 2Φ ) F γ = 2qN Aε Si C ox Penn ESE 570 Spring 2018 Khanna 6

7 MOSFET IV Characteristics 50 V DS S Drain current [arbitrary unit] Gate to source voltage [V] V GS Penn ESE 570 Spring 2018 Khanna 7

8 MOSFET IV Characteristics V DS <V GS V TH S V GS V th V DS V GS V TH Penn ESE 570 Spring 2018 Khanna V DS 8

9 Cutoff Region V GS < 0 NMOS TRANSISTOR IN CUTOFF REGION V G V D V S Depletion region Substrate or Bulk B p Immobile acceptor ions No depletion or inversion layer under oxide, no current flow 9

10 Depletion Region 0 < V GS < V TH V S V G V D depletion region Depletion layer under oxide, leakage/subthreshold current flow Penn ESE 570 Spring 2018 Khanna 10

11 Onset of Inversion Region V GS = V T0n + δ V DS = 0 V G V D Q I Q B0 Depletion region, and thin inversion layer (aka channel) Thermal equilibrium in channel, leakagelevel current flow 11

12 MOSFET IV Characteristics 50 V DS S Drain current [arbitrary unit] Gate to source voltage [V] V GS Penn ESE 570 Spring 2018 Khanna 12

13 Linear Region V GS > V T0 V DS small, V DS < V GS V T0 n + n + Channel acts like voltage controlled resistor Current flows proportional to V DS ( V DS ) As V D increases, channel depth at the drain decreases 13

14 Channel Voltage! Voltage varies along channel! Channel acts as a resistor " Serves as a voltage divider between V S and V D 14

15 Voltage along Channel! Voltage divider between V S and V D y=0 y=l V(y) y 15

16 Voltage along Channel! Voltage divider between V S and V D V(y) y=0 y=l Vd Vs y 16

17 Voltage along Channel! Voltage divider between V S and V D V(y) y=0 y=l Vd Vs y 17

18 Voltage along Channel! Voltage divider between V S and V D V(y) y=0 y=l Vd Vs y 18

19 Linear/Saturation Region Edge V GS > V T0 V DS = V GS V T0 n + n + Voltage divider along channel, until pinch off As V D increases, channel depth at the drain decreases 19

20 Channel Field! When voltage gap V G V y drops below V th, channel drops out of inversion " If V DS = V GS V th #V GS V DS =V G V D = V th 20

21 Saturation Region V GS > V T0 V DS > V GS V T0 V DS V DSAT V(x) = V DSAT n + z n + 21

22 Channel Field! When voltage gap V G V y drops below V th, drops out of inversion " What if V DS > V GS V th #V DS V GS > V th? " Upper limit on current, channel is pinched off " nmos current saturated 22

23 MOSFET IV Characteristics Linear Region V GS > V T0 V DS small, V DS < V GS V T0 n + z n + 23

24 MOSFET IV Characteristics Linear Region V GS > V T0 V DS small, V DS < V GS V T0 n + z n + V(y) Boundary Conditions: Mobile charge in inverted channel: V(y=0) = V S = 0, V(y=L) = V DS =V D Q I (y) = C ox [V GS V(y) V T0 ] 24

25 MOSFET IV Characteristics Linear Region z x y dr = dy W µ n Q I (y) µ n = electron mobility = cm 2 /(V sec) 25

26 MOSFET IV Characteristics Linear Region Q I (y) = C ox [V GS V(y) V T0 ] dr = dy W µ n Q I (y) Incremental potential drop along the channel segment with width dy dv CS dv C = dr = W µ n Q I (y) dy W µ n Q I (y) dv C = dy 26

27 MOSFET IV Characteristics Linear Region Q I (y) = C ox [V GS V(y) V T0 ] dr = dy W µ n Q I (y) Incremental potential drop along the channel segment with width dy dv CS dv C = dr = W µ n Q I (y) dy W µ n Q I (y) dv C = dy Integrate along the channel: V(y=0) = V S = 0, V(y=L) = V DS L dy = W µ n Q I ( y) dv C 0 V DS L =W µ n C ox 0 V DS 0 (V GS V C V T 0 ) dv C W = µ n C ox L (V V )V V 2 DS GS T 0 DS 2 27

28 MOSFET IV Characteristics Linear Region W # = µ n C ox L (V GS V T 0 )V DS V 2 DS % $ 2 & ( ' k ' = µ n C ox k = k ' W L = k ' 2 W L 2(V GS V T 0 )V DS V 2 DS ( ) = k ( 2 2(V V )V V 2 GS T 0 DS DS ) 28

29 MOSFET IV Characteristics! Example: For an nmos transistor with μ n = 600cm 2 /Vsec, C ox = 7x10 8 F/cm 2, W = 20μm, L = 2 μm, V T0 = 1V, plot the relationship between and V DS, V GS. 29

30 MOSFET IV Characteristics! Example: For an nmos transistor with μ n = 600cm 2 /Vsec, C ox = 7x10 8 F/cm 2, W = 20μm, L = 2 μm, V T0 = 1V, plot the relationship between and V DS, V GS. W = µ n C ox L (V V )V V 2 DS GS T 0 DS 2 = 0.42mA /V 2 (V GS 1.0)V DS V 2 DS 2 30

31 MOSFET IV Characteristics! Example: For an nmos transistor with μ n = 600cm 2 /Vsec, C ox = 7x10 8 F/cm 2, W = 20μm, L = 2 μm, V T0 = 1V, plot the relationship between and V DS, V GS. W = µ n C ox L (V V )V V 2 DS GS T 0 DS 2 = 0.42mA /V 2 (V GS 1.0)V DS V 2 DS 2 (V DS = V DSAT ) and V DSAT = V GS V T0 Assumptions: 31

32 MOSFET IV Characteristics W = µ n C ox L (V V )V V 2 DS GS T 0 DS 2 V DS =V DSAT =V GS V T 0 W = µ n C ox L (V V )(V V ) (V V GS T 0 )2 GS T 0 GS T 0 2 = µ n C ox 2 W L (V GS V T 0 )2 32

33 MOSFET IV Characteristics W = µ n C ox L (V V )V V 2 DS GS T 0 DS 2 LINEAR (V DS = V DSAT ) = (sat) SAT V DS =V DSAT =V GS V T 0 W = µ n C ox L (V V )(V V ) (V V GS T 0 )2 GS T 0 GS T 0 2 = µ n C ox 2 W L (V GS V T 0 )2 IN GENERAL (sat) 33

34 MOSFET IV Characteristics Saturation V DSAT V GS > V T0 V DS > V GS V T0 ΔL n + n + SAT = µ n C ox 2 W L' ( V GS V T 0 ) 2 = µ n C ox 2 W $ L& 1 ΔL % L empirically ΔL V DS V DSAT 1 ΔL L 1 λ V DS ' ) ( ( V GS V T 0 ) 2 If λ$v DS <<1, 1 ΔL L 1 λ V DS 1+ λ V DS 34

35 MOSFET IV Characteristics Saturation SAT = µ n C ox 2 W L' ( V GS V T 0 ) 2 = µ C n ox 2 W $ L& 1 ΔL % L emprically ΔL V DS V DSAT 1 ΔL L 1 λ V DS ' ) ( ( V GS V T 0 ) 2 If λ$v DS <<1, 1 ΔL L 1 λ V DS 1+ λ V DS = µ n C ox 2 W ( L V GS V T 0 ) 2 (1+ λ V DS ) 35

36 MOSFET IV Characteristics Linear Region: W # = µ n C ox L (V GS V T 0 )V DS V 2 DS % $ 2 & ( ' Saturation Region: = µ n C ox 2 W ( L V V GS T 0) 2 (1+ λ V DS ) λ 0 λ=0 36

37 MOSFET IV Characteristics Linear Region: W # = µ n C ox L (V GS V T 0 )V DS V 2 DS % $ 2 & ( ' Saturation Region: = µ n C ox 2 W ( L V V GS T 0) 2 (1+ λ V DS ) V DS = V DSAT λ 0 λ=0 37

38 MOSFET IV Characteristics Linear Region: W # = µ n C ox L (V GS V T 0 )V DS V 2 DS % $ 2 & ((1+ λ V DS ) ' Saturation Region: = µ n C ox 2 W ( L V V GS T 0) 2 (1+ λ V DS ) V DS = V DSAT λ 0 λ=0 38

39 MOSFET IV Characteristics Linear Region: W # = µ n C ox L (V GS V T 0 )V DS V 2 DS % $ 2 & ((1+ λ V DS ) ' Saturation Region: Level 1 model λ$v DS <<1 = µ n C ox 2 W ( L V V GS T 0) 2 (1+ λ V DS ) V DS = V DSAT λ 0 λ=0 39

40 MOSFET IV Characteristics, V SB 0 V T = V T 0 +γ ( 2Φ F V SB 2Φ ) F Linear Region: W # = µ n C ox L (V GS V T (V SB ))V DS V 2 DS % $ 2 & ((1+ λ V DS ) ' Saturation Region: = µ n C ox 2 W L V GS V T (V SB ) ( ) 2 (1+ λ V DS ) = f (V GS,V DS,V SB ) 40

41 nmos IV Characteristics % ' ' ' = & ' ' ' ( 0 V GS V Tn Cutoff/Subthreshold µ n C ox W ( 2 L 2 ( V GS V Tn (V SB ))V DS V 2 DS )(1+ λ V DS ) V GS > V Tn,V DS < V GS V Tn Linear/Resistive µ n C ox W ( 2 L V GS V Tn (V SB )) 2 (1+ λ V DS ) V GS > V Tn,V DS V GS V Tn Saturation 41

42 pmos IV Characteristics % ' ' ' = & ' ' ' ( 0 V GS V Tp Cutoff/Subthreshold µ p C ox W ( 2 L 2 ( V GS V Tp (V SB ))V DS V 2 DS )(1+ λ V DS ) V GS < V Tp,V DS > V GS V Tp Linear/Resistive µ p C ox W ( 2 L V GS V Tp (V SB )) 2 (1+ λ V DS ) V GS < V Tp,V DS V GS V Tp Saturation 42

43 Measurement of Parameters k n,p D G B S 43

44 Measurement of Parameters k n,p D G B S 44

45 Measurement of Parameters k n,p D G B S 45

46 Measurement of Parameters γ D G S B => SA T 46

47 Measurement of Parameters λ => SAT 47

48 Measurement of Parameters λ => SAT 48

49 Measurement of Parameters λ => SAT 49

50 Subthreshold 50

51 Below Threshold! Transition from insulating to conducting is nonlinear, but not abrupt! Current does flow " But exponentially dependent on V GS 51

52 Below Threshold! Transition from insulating to conducting is nonlinear, but not abrupt! Current does flow " But exponentially dependent on V GS 52

53 Parasitic NPN BJT! We have an NPN sandwich, mobile minority carriers in the P region! This is a BJT! " Except that the base potential is here controlled through a capacitive divider, and not directly an electrode Penn ESE 570 Spring 2018 Khanna 53

54 Subthreshold If V GS < V th, S = I S W L e V GS V th nkt /q 1 e V DS kt /q 1+ λv DS ( )! Current is from the parasitic NPN BJT transistor when gate is below threshold and there is no conducting channel " n is the capacitive divider between parasitic capacitances " Typically 1 < n < 1.5 n = C js + C ox C ox 54

55 Subthreshold If V GS < V th, S = I S W L e V GS V th nkt /q 1 e V DS kt /q 1+ λv DS ( )! Current is from the parasitic NPN BJT transistor when gate is below threshold and there is no conducting channel " n is the capacitive divider between parasitic capacitances " Typically 1 < n < 1.5 n = C js + C ox C ox 55

56 Subthreshold! W/L dependence follow from resistor behavior (parallel, series) " Not shown explicitly in text S = I S W L e V GS V th nkt /q 1 e V DS kt /q 1+ λv DS ( ) 56

57 Subthreshold Slope! Exponent in V GS determines how steep the turnon is " S = n kt % $ ' ln( 10) # q & " Units: V/decade " Every S Volts, S is scaled by factor of 10 S = I S W L e V GS V th nkt /q 1 e V DS kt /q 1+ λv DS ( ) 57

58 Subthreshold Slope! Exponent in V GS determines how steep the turnon is " S = n kt % $ ' ln( 10) # q & " Units: V/dec " Every S Volts, S is scaled by factor of 10! n depends on parasitic capacitance divider " n=1 # S=60mV at Room Temp. (ideal) " n=1.5 # S=90mV " Single gate structure showing S=90110mV 58

59 S vs. V GS (Logscale) 59

60 S vs. V GS S (Logscale) 60

61 Subthreshold Slope! If S=100mV and V th =300mV, what is Ids(Vgs=300mV)/Ids(Vgs=0V)?! What if S=60mV? " S = n$ kt # q % ' ln 10 & ( ) S = I S W L e V GS V th nkt /q 1 e V DS kt /q 1+ λv DS ( ) 61

62 Steady State! What current flows in steady state?! What causes (and determines) the magnitude of current flow?! Which device? 62

63 Leakage! Call this steadystate current flow leakage! I ds,leak 63

64 Big Idea! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation " Pinch Off " Channel length modulation! Level 1 Model " =f (V GS, V DS, V SB ) " Empirical measured parameters: k, γ,λ 64

65 Admin! HW 2 due tonight! HW 3 due Thursday, 2/1 " Posted tonight after class " Gets you started with Cadence " Make sure you can setup and launch Cadence tonight or tomorrow " Don t wait until night before homework is due! Penn ESE 570 Spring 2018 Khanna 65

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