ECE 342 Electronic Circuits. 3. MOS Transistors

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1 ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois 1

2 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to 100 m, and the thickness of the oxide layer (t ox ) is in the range of 2 to 50 nm. 2

3 NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type substrate MOS devices are smaller than BJTs MOS devices consume less power than BJTs 3

4 NMOS Transistor - Layout Top View Cross Section 4

5 MOS Regions of Operation Resistive Triode V V GS DS V T small Nonlinear V GS V T V < ( V V ) DS GS T Active Saturation V GS V T V V V DS GS T 5

6 MOS Transistor Operation As V G increases from zero Holes in the p substrate are repelled from the gate area leaving negative ions behind A depletion region is created No current flows since no carriers are available As V G increases The width of the depletion region and the potential at the oxide-silicon interface also increase When the interface potential reaches a sufficiently positive value, electrons flow in the channel. The transistor is turned on As V G rises further The charge in the depletion region remains relatively constant The channel current continues to increase 6

7 MOS Triode Region - 1 W ID Cox VGS VT VDS L V V V DS GS T C ox t ox ox 3.9 o t ox C ox : gate oxide capacitance : electron mobility L: channel length W: channel width V T : threshold voltage 7

8 MOS Triode Region FET is like a linear resistor with r ds 1 C W V L V n ox GS T 8

9 MOS Triode Region - 2 V GS V T V V V DS GS T Charge distribution is nonuniform across channel Less charge induced in proximity of drain W 1 I C V V V V L 2 2 D n ox GS T DS DS 9

10 MOS Active Region V V V V Saturation occurs at pinch off when DS GS T DSP V GS V T V V V DS GS T (saturation) W I C V V 2L 2 D n ox GS T 10

11 NMOS Drain Current 11

12 NMOS Circuit Symbols 12

13 NMOS IV Characteristics characteristics for a device with k n (W/L) = 1.0 ma/v 2. 13

14 MOS Threshold Voltage The value of V G for which the channel is inverted is called the threshold voltage V T (or V t ). Characteristics of the threshold voltage Depends on equilibrium potential Controlled by inversion in channel Adjusted by implantation of dopants into the channel Can be positive or negative Influenced by the body effect 14

15 nmos Device Types Enhancement Mode Normally off & requires positive potential on gate Good at passing low voltages Cannot pass full V DD (pinch off) Depletion Mode Normally on (negative threshold voltage) Channel is implanted with positive ions (V T ) Provides inverter with full output swings 15

16 Types of MOSFETS 16

17 MOS Active Region Saturation Channel is pinched off Increase in V DS has little effect on i D Square-law behavior wrt (V GS -V T ) Acts like a current source 17

18 Diode-Connected Transistor When the drain and gate of a MOSFET are connected together the result is a two-terminal device known as a diode-connected transistor V GD V T for saturation region. Since V GD is zero, then the device is always in the saturation region. 18

19 incremental resistance Diode-Connected Transistor 1 W i i k V V 2 L 2 ' D n GS t If we replace by and use r ' ' VGS V k kn W L 2 ' ik V Vt 1 i 1 1 V W W L L ' 2 k' V Vt kn Vov V V V t ov

20 Example An MOS process technology has L min = 0.4 m, t ox = 8 nm, = 450 cm 2 /V.s, V T = 0.7V (a)find C ox and k n = n C ox (b) W/L = 8 m/0.8m. Calculate V GS, V DSmin for operation in saturation with I D = 100 A (c)find V GS for the device in (b) to operate as a 1 k resistor for small v DS 20

21 Example - Solution 11 ox Cox F/ m 4.32 ff/ m 9 t 810 ox k C 450 cm / V. s4.32 ff/ m 194 A/ V ' n n ox For operation in saturation region C 4.32 ff/ m 1 ' W i 2 D kn VGS VT 2 L V GS VGS V VGS 1.02V VDS min VGS VT 0.32V ox 2 V DS min 0.32 V 21

22 Example (con t) Triode region with v DS very small r DS vds 1 i ' W D small v DS kn VGS VT L V GS 0.7 VGS V VGS 1.22 V 22

23 Body Effect The body effect V T varies with bias between source and body Leads to modulation of V T Potential on substrate affects threshold voltage V ( ) T VSB VTo 2F VSB 2F 1/2 1/2 F kt N a ln q ni Fermi potential of material 2qN 1/2 a C ox s Body bias coefficient 23

24 Channel-Length Modulation With depletion layer widening, the channel length is in effect reduced from L to L-L Channel-length modulation This leads to the following I-V relationship 1 i k W v V v 2 L ' 2 D n GS T 1 DS Where is a process technology parameter 24

25 Channel-Length Modulation Channel-length modulation causes i D to increase with v DS in saturation region 25

26 Problem A MOSFET has V T = 1 V with measured data: Find V GS (V) V DS (V) I D (A) ( a) VGS VT VDS VGS VT Pinchoff ( b) V V V V V 1V Active region GS T DS GS T 26

27 Problem (cont ) Find i D at pinchoff V DSP = V GS -V T =1V 1 I k W V V V 2 L ' 2 D n GS T 1 DS 1 I k W V V V 2 L ' 2 D1 n GS1 T 1 DS1 1 I k W V V V 2 L ' 2 D2 n GS2 T 1 DS2 27

28 Problem (cont ) R 1 VDS V 80 DS1 1VDS 2 RRVDS1 ( V RV ) R1 DS 2 DS1 R V V RV 81 DS 2 DS1 1 28

29 NMOS IV Curves 700 NMOS 600 VGS=1.0 VGS=1.5 VGS=2.0 VGS= IDS Vds 29

30 NMOS IV Curves 30

31 MOSFET Circuit at DC Problem 1 The MOSFET in the circuit shown has V t = 1V, k n = 100A/V 2 and = 0. Find the required values of W/L and of R so that when v I =V DD =+5 V, r DS =50 and v o = 50 mv. v V 5 V, v V 0.05V I GS o DS VDS 0.05 rds 50 ID A1 ma I 50 D R VDD vo k I 1 D 31

32 MOSFET Circuit at DC Problem 1 (cont ) VDS VGS Vt triode region ' W I D kn VGS Vt VDS L V 2 2 DS 2 3 W L W L

33 The NMOS transistors in the circuit shown have V t = 1V, n C ox = 120A/V 2, = 0 and L 1 =L 2 =1m. Find the required values of gate width for each of Q 1 and Q 2 and the value of R, to obtain the voltage and current values indicated. V MOSFET Circuit at DC Problem 2 GS1 1.5 V 1 ' W Using I 2 D kn VGS Vt 2 L 1 W 120 A W2 2m R 12.5 k

34 Gate Capacitance V 0 V 0, V small GT GT DS Capacitance Depends on bias Fringing fields are present Account for overlap C V GT 0, V large DS 34

35 Capacitance Gate Capacitance C G determines the amount of charge to switch gate Several distributed components Large discontinuity as device turns on At saturation capacitance is entirely between gate and source Define VDS X V V GS T 2 1 X Cgs Cgso WLCox X 2 1 Cgd Cgdo WLCox X

36 MOS Capacitances Expect capacitance between every two of the four terminals. 36

37 MOS Parasitics - Capacitance from gate to other 3 terminals - Diodes to body - Series resistance - Wiring parasitics 37

38 PMOS Transistor 0 PMOS VGS= VGS=-1.0 VGS=-1.5 VGS=-2.0 VGS= All polarities are reversed from nmos - v GS, v DS and V t are negative - Current i D enters source and leaves through drain - Hole mobility is lower low transconductance - nmos favored over pmos Vds 38

39 PMOS Circuit The PMOS transistor in the circuit shown has V t = -0.7 V, p C ox = 60A/V 2, = 0 and L=0.8m. Find the values required for W and R, in order to establish a drain current of 115 A and a voltage V D of 3.5 V. R k W ( 0.7) ma W 4.8 m 2 39

40 Complementary MOS CMOS Characteristics Combine nmos and pmos transistors pmos size is larger for electrical symmetry 40

41 CMOS Advantages Virtually, no DC power consumed No DC path between power and ground Excellent noise margins (V OL =0, V OH =V DD ) Inverter has sharp transfer curve Drawbacks Requires more transistors Process is more complicated pmos size larger to achieve electrical symmetry Latch up 41

42 MOSFET Switch NMOS PMOS Characteristics of MOS Switch MOS approximates switch better than BJT in off state Resistance in on state can vary from 100 to 1 k 42

43 CMOS Switch CMOS switch is called an inverter 43

44 CMOS Switch Off State OFF State (V in : low) nmos transistor is off Path from V out to V 1 is through PMOS V out : high 44

45 CMOS Switch On State ON State (V in : high) pmos transistor is off Path from V out to ground is through nmos V out : low 45

46 CMOS Inverter r dsn 1 k W V V ' N DD T L n r dsp 1 k W V V ' P DD T L p Short switching transient current low power 46

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