ECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model


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1 ECE 34 Electronic Circuits Lecture 35 CMOS Delay Model Jose E. SchuttAine Electrical & Computer Engineering University of Illinois ECE 34 Jose Schutt Aine 1
2 Digital Circuits V IH : Input voltage at high state V IHmin V IL : Input voltage at low state V ILmax V OH : Output voltage at high state V OHmin V OL : Output voltage at low state V OLmin Likewise for current we can define Currents into input Currents into output I IH I IHmax I IL I ILmax I OH I OHmax I OL I OLmax ECE 34 Jose Schutt Aine
3 Voltage Transfer Characteristics (VTC) The static operation of a logic circuit is determined by its VTC In low state: noise margin is NM L NM V V L IL OL In high state: noise margin is NM H NM V V H OH IH An ideal VTC will maximize noise margins NM L NM H V IL and V IH are the points where the slope of the VTC=1 Optimum: NM NM V L H DD / ECE 34 Jose Schutt Aine 3
4 CMOS Inverter VTC Q P and Q N are matched ECE 34 Jose Schutt Aine 4
5 CMOS Inverter VTC Derivation Assume that transistors are matched Vertical segment of VTC is when both Q N and Q P are saturated No channel length modulation effect = 0 Vertical segment occurs at v i =V DD / V IL : maximum permitted logic0 level of input (slope=1) V IH : minimum permitted logic1 level of input (slope=1) CMOS inverter can be made to switch at V DD / by appropriate sizing LOGIC Threshold: V M V th V V k / k V DD tp n p tn 1 k / k n p k k W / L and k k W / L ' where ' n n n p p p ECE 34 Jose Schutt Aine 5
6 Matched CMOS Inverter VTC CMOS inverter can be made to switch at specific threshold voltage by appropriately sizing the transistors W n W L L p p Symmetrical transfer characteristics is obtained via matching equal current driving capabilities in both directions (pullup and pulldown) n ECE 34 Jose Schutt Aine 6
7 Switching Time & Propagation Delay input output ECE 34 Jose Schutt Aine 7
8 Switching Time & Propagation Delay t r =rise time (from 10% to 90%) t f =fall time (from 90% to 10%) t plh =lowtohigh propagation delay t phl =hightolow propagation delay Inverter propagation delay: t p tplh tphl 1 ECE 34 Jose Schutt Aine 8
9 CMOS Dynamic Operation Exact analysis is too tedious Replace all the capacitances in the circuit by a single equivalent capacitance C connected between the output node of the inverter and ground Analyze capacitively loaded inverter to determine propagation delay ECE 34 Jose Schutt Aine 9
10 CMOS Dynamic Operation C C C C C C C C gd1 gd db1 db g3 g4 w ECE 34 Jose Schutt Aine 10
11 CMOS Dynamic Operation ECE 34 Jose Schutt Aine 11
12 CMOS Dynamic Operation Need interval t PHL during which v o reduces from V DD to V DD / I t C V V av PHL DD DD / Which gives I av is given by t PHL CV I DD av 1 Iav idn E idn M ECE 34 Jose Schutt Aine 1
13 CMOS Dynamic Operation where 1 W i E k V V L ' DN n DD tn n and ' W V 1 DD VDD idn M kn VDD Vtn L n this gives t PHL nc k W / L V ' n n DD ECE 34 Jose Schutt Aine 13
14 Where a is given by CMOS Dynamic Operation n 7 4 3V V tn DD V V tn DD Likewise, t PLH is given by t PLH C 7 4 VDD V DD p with p ' k / p W L V 3 Vtp Vtp p DD ECE 34 Jose Schutt Aine 14
15 Where a is given by CMOS Dynamic Operation 1 t t t P PHL PLH Components can be equalized by matching transistors t P is proportional to C reduce capacitance Larger V DD means lower t p Conflicting requirements exist ECE 34 Jose Schutt Aine 15
16 CMOS Propagation Delay ECE 34 Jose Schutt Aine 16
17 CMOS Propagation Delay Capacitance C is the sum of: Internal capacitances of Q N and Q P Interconnect wire capacitance Input of the other logic gate t PHL 1.6C k W / L V ' n n DD To lower propagation delay Minimize C Increase process transconductance k Increase W/L Increase V DD ECE 34 Jose Schutt Aine 17
18 n Propagation Delay  Example Find the propagation delay for a minimumsize inverter for which k n =3k p =180 A/V and (W/L) n = (W/L) p =0.75 m/0.5 m, V DD = 3.3 V, V tn = V tp = 0.7 V, and the capacitance is roughly ff/mm of device width plus 1 ff/device. What does t p become if the design is changed to a matched one? Use the method of average current Solution 7 3V tn V tn VDD VDD nc ff ff tphl ' k / n W L V n DD ECE 34 Jose Schutt Aine 18
19 Propagation Delay  Example tphl 4.85 ps Since V V, then 1.73 tn tp n p W W We also have, hence L n L p ' kn tplh tphl ps ' k n 1 1 t p tphl tplh 9.7 ps ECE 34 Jose Schutt Aine 19
20 Propagation Delay  Example If both devices are matched, then k ' p k ' n t PLH t PHL and 1 t p tphl tplh tphl 4.85 ps ECE 34 Jose Schutt Aine 0
21 CMOS Dynamic Power Dissipation In every cycle Q N dissipate ½ CV DD of energy Q P dissipate ½ CV DD of energy Total energy dissipation is CV DD If inverter is switched at f cycles per second, dynamic power dissipation is: P D fcv DD ECE 34 Jose Schutt Aine 1
22 Power Dissipation  Example In this problem, we estimate the inverter power dissipation resulting from the current pulse that flows in Q N and Q P when the input pulse has finite rise and fall times. Let V tn =V tp =0.5 V, V DD = 1.8V, and k n =k p =450A/V. Let the input rising and falling edges be linear ramps with the 0toV DD and V DD to0 transitions taking 1 ns each. Find I peak ECE 34 Jose Schutt Aine
23 Power Dissipation  Example To determine the energy drawn from the supply per transition, assume that the current pulse can be approximated by a triangle with a base corresponding to the time for the rising or falling edge to go from V t to V DD V t, and the height equal to I peak. Also, determine the power dissipation that results when the inverter is switched at 100 MHz. ECE 34 Jose Schutt Aine 3
24 Power Dissipation  Example 1 W VDD IPeak ncox Vtn L n I Peak 1 A A V ECE 34 Jose Schutt Aine 4
25 Power Dissipation  Example The time when the input reaches V t is: 0.5 1ns 0.8ns 1.8 The time when the input reaches V DD  V t is: ns 0.7ns 1.8 The base of the triangle is t ns wide ECE 34 Jose Schutt Aine 5
26 Power Dissipation  Example 1 1 E IPeak VDD t 36 A ns E 14.3 fj 6 15 P f E W ECE 34 Jose Schutt Aine 6
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