EKV MOS Transistor Modelling & RF Application

Size: px
Start display at page:

Download "EKV MOS Transistor Modelling & RF Application"

Transcription

1 HP-RF MOS Modelling Workshop, Munich, February 15-16, 1999 EKV MOS Transistor Modelling & RF Application Matthias Bucher, Wladek Grabinski Electronics Laboratory (LEG) Swiss Federal Institute of Technology, Lausanne (EPFL) Part I: Charge-based DC, AC and Noise Modelling Part II: RF Application PART I: Charge-based DC, AC and Noise Modelling Introduction: EKV v.6 Charge-based Static Model Quasi-static Charge & Transcapacitances Model NQS Model Noise Model Mobility Model & Short-Channel Effects MB-WG 1999 EKV MOS Transistor Modelling & RF Application

2 Introduction: EKV v.6 MOS Transistor (MOST) Model Motivation: RF circuit design requires complete MOST model from DC to RF, including noise. All current levels need to be well modelled, in particular also moderate inversion. EKV v.6 in summary: A physics-based compact MOST model in the public domain. Dedicated to analog circuit simulation for submicron CMOS. Includes weak-moderate-strong inversion modelling, doping & mobility effects, short-channel effects, geometry- and bias-dependent matching. Small number of intrinsic model parameters: EKV v.6: <, BSIM3v3: > 65, MM9: > 55 MB-WG 1999 EKV MOS Transistor Modelling & RF Application 3 Charge-based Static Model B p+ V S V G V D G S L n+ n+ L eff D t ox x V G G V S D S VD B y p substrate Bulk-reference, symmetric model structure. Drain current expression including drift and diffusion: dv ch = W µ ( Q I ) dx (1) MB-WG 1999 EKV MOS Transistor Modelling & RF Application 4

3 Charge-based Static Model Q I C ox Inversion Charge Density n V P g ms β B A V S I D β strong inversion E D V D C V P = I F I R g md β weak inversion V ch W eff β = µ C ox Channel Voltage L eff Integration of V D Q I Q I = β d V = ch V S C ox from source to drain: β V S Q I d V ch C ox I F ( V P V S ) β V D Q I d V ch C ox I R ( V P V D ) () MB-WG 1999 EKV MOS Transistor Modelling & RF Application 5 Drain Current Normalization and Pinch-off Voltage Current normalization using the Specific current : I S = I F I R = I S ( i f i r ) = nβu T ( ) i f i r (3) Pinch-off voltage V P accounts for... threshold voltage V TO and substrate effect γ qε s N sub = ( ) C ox γ V P V G V TO γ V G V + TO Ψ + -- γ = Ψ + -- (4) Slope factor n: n 1 V P = = V G γ Ψ + V P (5) MB-WG 1999 EKV MOS Transistor Modelling & RF Application 6

4 Charge-based Static Model g ms U T / asymptotes analytical numerical (GAMMA=.7 V) i f = / I S 1/ if g ms U T / analytic interpolation measured characteristics for:.5 µm, GAMMA=.64 V.7 µm, GAMMA=.75 V 1 µm, GAMMA=.7 V / I S Normalized transconductance-to-current ratio vs. normalized current I S from weak through moderate to strong inversion. Comparison with numerical solution of the Poisson equation. Comparison with three different CMOS processes (long-channel devices in saturation). Almost technology independent! g ms U T MB-WG 1999 EKV MOS Transistor Modelling & RF Application 7 Drain Current and Pinch-off Voltage [A] n-channel W=1 µm L=1 µm V D =3V VS=V.5V 1V 1.5V V G [V] I S V S [V] simulated measured 1 W=µm L=.7µm W=µm L=µm 3 V G [V] n-channel VTO=.75 V GAMMA=.755 V PHI=.576 V LETA=.53 WETA=.56 4 W=.8µm L=µm 5 Valid from weak to strong inversion, and from linear to saturation. Accuracy of weak inversion slope and substrate effect. no additional parameters used for adapting weak inversion slope MB-WG 1999 EKV MOS Transistor Modelling & RF Application 8

5 Quasistatic Charge- & Transcapacitances Model Charges normalized to WLCox [V] QB QG (VD=V) QG (VD=V) QS, QD (VD=V) QS & QD (VD=V) C OX = C ox W L Node charges: integration of inversion charge density along channel: L Q I = W Q I ( x) dx Q D = W x L -- Q I ( x ) dx Q S = Q I Q D n 1 Q B = γ C OX V P + Ψ Q n I Q G = Q I Q B Q ox Drain and source charges are obtained using Ward s charge partitioning scheme. Single equation expressions are used from weak to strong inversion. VG [V] L (6) (7) MB-WG 1999 EKV MOS Transistor Modelling & RF Application 9 (Trans-)Capacitances Model Intrinsic Capacitances C/(C ox WL) T OX =6.6nm V D =V S =V W=µm, L=5µm C GG C GD =C GS C GB 1 V G [V] Simulated: Measured: 3 Normalized intrinsic capacitances CGD (VG=V) CBD (VG=V) CGD (VG=.8V) CBD (VG=.8V) CGS (VG=V) CGS (VG=.8V) CGB (VG=.8V) CGB (VG=V) VDB [V] Transcapacitances: derivation with respect to the terminal voltage: C MN = ± ( Q M ) MN, = G, D, S, B Accurate capacitances through all inversion levels. Symmetric C GS and C GD at V D =V S =. V N (8) MB-WG 1999 EKV MOS Transistor Modelling & RF Application 1

6 Intrinsic MOST - Small Signal Equivalent G Cgs Ymg Vg Cgd S Yms Vs Cgb D Transcapacitances are not shown Ymd Vd Cbs Cbd Distributed time constant accounting for transmission line effect B First-order model for the transadmittances using bias-dependent time constant : τ i d Y mgds (,, ) v ( gds,, ) g mgds (,, ) = with τ = τ 1+ s τ fi ( f, i r ) L τ = µ U T (9) (1) MB-WG 1999 EKV MOS Transistor Modelling & RF Application 11 Non-Quasistatic Model mag(y1) phase(y1) C (QS) Q (QS) C (QS) Q: charge C: capacitance Model: W/L=36x9/ C (NQS) Q (NQS) Q (NQS) C (NQS) Q (QS) Intrinsic MOST: effect of QS/NQS models on charges-transcapacitances- and capacitances-only models. Y1 Phase prediction is similar for all models except C-only QS model. Y1 Magnitude prediction is incorrect for Q (QS) and C (QS) models. MB-WG 1999 EKV MOS Transistor Modelling & RF Application 1

7 Noise Model 3-Feb-99 13:54:9 File : noise.cou ELDO v4.6_1.1 (production) : * M.BUCHER - LEG/DE/EPFL DB(INOISE)_1:3 DB(INOISE)_:3 DB(INOISE)_3:3 DB(INOISE)_4:3 db db DB(INOISE)_5:3 input noise PSD 5e-1 1e+1 1e+ 1e+3 1e+4 1e+5 1e+6 Hz DB(ONOISE)_1:3 DB(ONOISE)_:3 DB(ONOISE)_3:3 DB(ONOISE)_4:3 DB(ONOISE)_5:3 output noise PSD Noise PSD [dbv/ Hz] f = 1kHz KF = (no 1/f noise) LEVEL 3 EKV model V DS [V] e-1 1e+1 1e+ 1e+3 1e+4 1e+5 1e+6 Hz Thermal noise is proportional to total inversion charge. Valid for all inversion levels, and from linear to saturation. 1/f noise modelling included. Q I MB-WG 1999 EKV MOS Transistor Modelling & RF Application 13 Mobility Model 14x1-6 4x n-channel W=L=1µm V DS =5 V 3 p-channel W=L=1µm V DS =5 V EKV v.6 for.5um CMOS (NMOS, PMOS) 4 V B = V B =-1.5V Measured Simulated 1 V B = V B =1.5V Measured Simulated V GS V GS Field- and position-dependent mobility: µ ( x) µ ' = where: E E eff ( x) eff ( x) E = Q' B ( x) + η Q' inv ( x) ε ε si (11) One parameter: E vertical critical field in the oxide η = 1 η = 1 3 for n-channel, for p-channel) No back-bias dependence needed due to inclusion of bulk charge. MB-WG 1999 EKV MOS Transistor Modelling & RF Application 14

8 Short-channel Effects 3.5x1-3 [A] n-channel W=1 µm L=.5 µm V S = V VG=3V.5V V 1.5V 1V V T [mv] Measure Simulation L drawn [µm] g ds [A/V] V D [V] [A] 1 - n-channel 1-3 W=1 µm L=.5 µm 1-4 V D =3V VS=V.5V 1V 1.5V V G [V] 3. I S Includes short-channel effects (here:.5um CMOS) Velocity saturation, Channel length modulation (CLM), D-charge sharing, RSCE MB-WG 1999 EKV MOS Transistor Modelling & RF Application 15 Summary EKV v.6 MOST model is a charge-based compact model Continuous, physics-based and valid for all bias conditions. Includes charge-based static and dynamic models, and noise. Non-quasistatic (NQS) model for small-signal. Availability early 99: Eldo, SmartSpice, Saber, Spectre, HSpice, PSpice, Aplac, Smash (check model versions). EKV v.6 on the web: < MB-WG 1999 EKV MOS Transistor Modelling & RF Application 16

9 PART II: RF Application of the EKV v.6 MOST Model Intrinsic MOST and Extrinsic Parasitic Elements RF Test Structure Simulation and Measurement Environment DC Measurements and Simulations RF Measurements and Simulations MB-WG 1999 EKV MOS Transistor Modelling & RF Application 17 Intrinsic MOST and Extrinsic Parasitic Elements Structure of the MOST Corresponding small-signal EKV model G Lov S intrinsic part G Lov D Cgso Rg intrinsic part Cgs Cgd Ymg Vg Cgbo Cgdo As L W Ad S Rs gs Cjs Yms Vs Ymd Vd Cbs Cgb Cbd Cjd gd Rd D B C js(d) = A s(d) * C j + P s(d) * C jsw C ov = W * L ov * C ox P s, P d - perimeter A s, A d - area Rb MB-WG 1999 EKV MOS Transistor Modelling & RF Application 18

10 Simulation and Measurement Environment Measurements: HP851 and HP 8719 Network Analyzers HP4145 and HP4156 DC Parameter Analyzers Cascade HF Probe Station Ground-Signal-Ground (GSG) probes Test Devices: RF MOS transistor matrix with 36 parallel devices in GSG pad frame Geometry of single circular MOST: L =.5 um, W = 9.um OPEN pad frame for de-embedding thru Y parameters Parameter Extraction and Simulation: IC-CAP 5 ELDO v4.6 with EKV v.6 (LEVEL=44) MB-WG 1999 EKV MOS Transistor Modelling & RF Application 19 RF Test Structure courtesy A.-S. Porret The GSG pad frame and matrix of the RF MOSTs Minimized extrinsic drain capacitance using circular layout MB-WG 1999 EKV MOS Transistor Modelling & RF Application

11 DC Measurements and Simulations vs. V G g m vs. V G Transfer current and conductance characteristics VD = 5mV MB-WG 1999 EKV MOS Transistor Modelling & RF Application 1 DC Measurements and Simulations vs. V D g ds vs. V D Output current and conductance characteristics MB-WG 1999 EKV MOS Transistor Modelling & RF Application

12 RF Measurements and Simulations S11, S S1, S1 S1 S S1 S11 Measured de-embedded and simulated S-parameters Frequency sweep 45MHz - GHz DC bias VG = 1.5 V VD = 3.V MB-WG 1999 EKV MOS Transistor Modelling & RF Application 3 RF Measurements and Simulations Re(Y1) Im(Y1) Real and Imaginary parts of the forward admittance Y 1 MB-WG 1999 EKV MOS Transistor Modelling & RF Application 4

13 RF Measurements and Simulations Re(Y 11 ) Re(Y ) Real parts of the input and output admittances Y 11, Y MB-WG 1999 EKV MOS Transistor Modelling & RF Application 5 RF Measurements and Simulations G max Maximum power gain G max MB-WG 1999 EKV MOS Transistor Modelling & RF Application 6

14 Summary Application of the physics-based EKV v.6 MOST model for RF simulation has been presented DC parameter set was verified on the RF MOST test structure measurements The small-signal characteristics were corrected for interconnections and bond pads parasitics Effective gate and bulk (substrate) resistances were introduced to allow proper small signal simulation Simulated small-signal S- and Y- parameters match on-the-wafers measurements over wide range of frequencies (45MHz - GHz) MB-WG 1999 EKV MOS Transistor Modelling & RF Application 7

Compact Modeling of Ultra Deep Submicron CMOS Devices

Compact Modeling of Ultra Deep Submicron CMOS Devices Compact Modeling of Ultra Deep Submicron CMOS Devices Wladyslaw Grabinski*, Matthias Bucher, Jean-Michel Sallese, François Krummenacher Swiss Federal Institute of Technology (EPFL), Electronics Laboratory,

More information

Analysis of Transconductances in Deep Submicron CMOS with EKV 3.0

Analysis of Transconductances in Deep Submicron CMOS with EKV 3.0 MOS Models & Parameter Extraction Workgroup Arbeitskreis MOS Modelle & Parameterextraktion XFAB, Erfurt, Germany, October 2, 2002 Analysis of Transconductances in Deep Submicron CMOS with EKV 3.0 Matthias

More information

The Devices. Devices

The Devices. Devices The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Cross-Section of CMOS Technology MOS transistors

More information

MIXDES 2001 Zakopane, POLAND June 2001

MIXDES 2001 Zakopane, POLAND June 2001 8 th International Conference ADVANCEMENTS IN DC AND RF MOSFET MODELING WITH THE EPFL-EKV CHARGE BASED MODEL,;(' '(6,* J.-M. SALLESE *, W. GRABINSKI **, A.S. PORRET *, M. BUCHER +, C. LALLEMENT ++, F.

More information

ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits. 3. MOS Transistors ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

More information

The HV-EKV MOSFET Model

The HV-EKV MOSFET Model The HV-EKV MOSFET Model Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland EPFL Team Yogesh Singh Chauhan, Costin Anghel, Francois Krummenacher, Adrian Mihai Ionescu and Michel Declercq CMC Meeting,

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

Lecture 3: CMOS Transistor Theory

Lecture 3: CMOS Transistor Theory Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors

More information

MOS Transistor I-V Characteristics and Parasitics

MOS Transistor I-V Characteristics and Parasitics ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

More information

MOSFET Capacitance Model

MOSFET Capacitance Model MOSFET Capacitance Model So far we discussed the MOSFET DC models. In real circuit operation, the device operates under time varying terminal voltages and the device operation can be described by: 1 small

More information

! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications

! MOS Capacitances.  Extrinsic.  Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February, 07 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance Model!

More information

ECE 497 JS Lecture - 12 Device Technologies

ECE 497 JS Lecture - 12 Device Technologies ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

University of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA

University of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA University of Pennsylvania Department of Electrical Engineering ESE 570 Midterm Exam March 4, 03 FORMULAS AND DATA. PHYSICAL CONSTANTS: n i = intrinsic concentration undoped) silicon =.45 x 0 0 cm -3 @

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February 4, 2016 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance

More information

MOS Transistor Properties Review

MOS Transistor Properties Review MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO

More information

Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS

Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS Operation and Modeling of The MOS Transistor Second Edition Yannis Tsividis Columbia University New York Oxford OXFORD UNIVERSITY PRESS CONTENTS Chapter 1 l.l 1.2 1.3 1.4 1.5 1.6 1.7 Chapter 2 2.1 2.2

More information

The Devices: MOS Transistors

The Devices: MOS Transistors The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor

More information

ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

More information

Practice 3: Semiconductors

Practice 3: Semiconductors Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given

More information

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model - Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 6: January 30, 2018 MOS Operating Regions, pt. 2 Lecture Outline! Operating Regions (review) " Subthreshold " Resistive " Saturation! Intro.

More information

ELEC 3908, Physical Electronics, Lecture 26. MOSFET Small Signal Modelling

ELEC 3908, Physical Electronics, Lecture 26. MOSFET Small Signal Modelling ELEC 3908, Physical Electronics, Lecture 26 MOSFET Small Signal Modelling Lecture Outline MOSFET small signal behavior will be considered in the same way as for the diode and BJT Capacitances will be considered

More information

ELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model

ELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model ELEC 3908, Physical Electronics, Lecture 23 The MOSFET Square Law Model Lecture Outline As with the diode and bipolar, have looked at basic structure of the MOSFET and now turn to derivation of a current

More information

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET: Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)

More information

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated

More information

Microelectronics Part 1: Main CMOS circuits design rules

Microelectronics Part 1: Main CMOS circuits design rules GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! med-amine.miled@polymtl.ca!

More information

Advanced Compact Models for MOSFETs

Advanced Compact Models for MOSFETs Advanced Compact Models for MOSFETs Christian Enz, Carlos Galup-Montoro, Gennady Gildenblat, Chenming Hu, Ronald van Langevelde, Mitiko Miura-Mattausch, Rafael Rios, Chih-Tang (Tom) Sah Josef Watts (editor)

More information

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1

More information

Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

More information

EE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania

EE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania 1 EE 560 MOS TRANSISTOR THEORY PART nmos TRANSISTOR IN LINEAR REGION V S = 0 V G > V T0 channel SiO V D = small 4 C GC C BC substrate depletion region or bulk B p nmos TRANSISTOR AT EDGE OF SATURATION

More information

Circuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

Circuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number EE610: CMOS Analog Circuits L: MOS Models- (1 st Aug. 013) B. Mazhari Dept. of EE, IIT Kanpur 3 NMOS Models MOS MODEL Above Threshold Subthreshold ( GS > TN ) ( GS < TN ) Saturation ti Ti Triode ( DS >

More information

The PSP compact MOSFET model An update

The PSP compact MOSFET model An update The PSP compact MOSFET model An update Gert-Jan Smit, Andries Scholten, D.B.M. Klaassen NXP Semiconductors Ronald van Langevelde Philips Research Europe Gennady Gildenblat, Weimin Wu, Xin Li, Amit Jha,

More information

EKV based L-DMOS Model update including internal temperatures

EKV based L-DMOS Model update including internal temperatures ROBUSPIC (IST-507653) Deliverable D1.2 EKV based L-DMOS Model update including internal temperatures Yogesh Singh Chauhan, Costin Anghel, Francois Krummenacher, Adrian Ionescu and Michel Declercq Ecole

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

More information

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing EE115C Winter 2017 Digital Electronic Circuits Lecture 3: MOS RC Model, CMOS Manufacturing Agenda MOS Transistor: RC Model (pp. 104-113) S R on D CMOS Manufacturing Process (pp. 36-46) S S C GS G G C GD

More information

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing

More information

EE5311- Digital IC Design

EE5311- Digital IC Design EE5311- Digital IC Design Module 1 - The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM

More information

Chapter 4 Field-Effect Transistors

Chapter 4 Field-Effect Transistors Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation

More information

ESE 570 MOS TRANSISTOR THEORY Part 2

ESE 570 MOS TRANSISTOR THEORY Part 2 ESE 570 MOS TRANSISTOR THEORY Part 2 GCA (gradual channel approximation) MOS Transistor Model Strong Inversion Operation CMOS = NMOS + PMOS 2 TwoTerminal MOS Capacitor > nmos Transistor VGS

More information

EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM

More information

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;

More information

Physics-based compact model for ultimate FinFETs

Physics-based compact model for ultimate FinFETs Physics-based compact model for ultimate FinFETs Ashkhen YESAYAN, Nicolas CHEVILLON, Fabien PREGALDINY, Morgan MADEC, Christophe LALLEMENT, Jean-Michel SALLESE nicolas.chevillon@iness.c-strasbourg.fr Research

More information

Investigation of the Thermal Noise of MOS Transistors under Analog and RF Operating Conditions

Investigation of the Thermal Noise of MOS Transistors under Analog and RF Operating Conditions Investigation of the Thermal Noise of MOS Transistors under Analog and RF Operating Conditions Ralf Brederlow 1, Georg Wenig 2, and Roland Thewes 1 1 Infineon Technologies, Corporate Research, 2 Technical

More information

Introduction and Background

Introduction and Background Analog CMOS Integrated Circuit Design Introduction and Background Dr. Jawdat Abu-Taha Department of Electrical and Computer Engineering Islamic University of Gaza jtaha@iugaza.edu.ps 1 Marking Assignments

More information

ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN

ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN CMOS PROCESS CHARACTERIZATION VISHAL SAXENA VSAXENA@UIDAHO.EDU Vishal Saxena DESIGN PARAMETERS Analog circuit designers care about: Open-loop Gain: g m r o

More information

Lecture 12: MOSFET Devices

Lecture 12: MOSFET Devices Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background

More information

EE105 - Fall 2005 Microelectronic Devices and Circuits

EE105 - Fall 2005 Microelectronic Devices and Circuits EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture

More information

EKV Modelling of MOS Varactors and LC Tank Oscillator Design

EKV Modelling of MOS Varactors and LC Tank Oscillator Design EKV Modelling of MOS Varactors and LC Tank Oscillator Design Wolfgang Mathis TET Leibniz Universität Hannover Jan-K. Bremer NXP Hamburg MOS-AK Workshop 01 6. 7. April 01, Dresden Content: Motivation: VCO

More information

Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

More information

Sadayuki Yoshitomi. Semiconductor Company 2007/01/25

Sadayuki Yoshitomi. Semiconductor Company 2007/01/25 Sadayuki Yoshitomi. Semiconductor Company Sadayuki.yoshitomi@toshiba.co.jp Copyright 2006, Toshiba Corporation. ASP-DAC 2007 . Make the best of Electro-Magnetic (EM) simulation. Is EM simulator applicable

More information

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

More information

Conduction in Semiconductors -Review

Conduction in Semiconductors -Review Conduction in Semiconductors Review Intrinsic (undoped) Semiconductors intrinsic carrier concentration n i =.45x0 0 cm 3, at room temp. n = p = n i, in intrinsic (undoped) material n number of electrons,

More information

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2

More information

The Devices. Jan M. Rabaey

The Devices. Jan M. Rabaey The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models

More information

MOS Transistor Theory

MOS Transistor Theory CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

More information

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins,

More information

CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS

CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS 98 CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS In this chapter, the effect of gate electrode work function variation on DC

More information

LEVEL 61 RPI a-si TFT Model

LEVEL 61 RPI a-si TFT Model LEVEL 61 RPI a-si TFT Model Star-Hspice LEVEL 61 is an AIM-SPICE MOS15 amorphous silicon (a-si) thin-film transistor (TFT) model. Model Features AIM-SPICE MOS15 a-si TFT model features include: Modified

More information

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Chapter 2 CMOS Transistor Theory Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor Jin-Fu Li, EE,

More information

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Lecture 1 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;

More information

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the

More information

Lecture 4: CMOS Transistor Theory

Lecture 4: CMOS Transistor Theory Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

More information

SMALL-SIGNAL MODELING OF RF CMOS

SMALL-SIGNAL MODELING OF RF CMOS SMALL-SIGNAL MODELING OF RF CMOS A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS

More information

Lecture 5: CMOS Transistor Theory

Lecture 5: CMOS Transistor Theory Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics

More information

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION ECE-343 Test : Feb 0, 00 6:00-8:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z

More information

VLSI Design and Simulation

VLSI Design and Simulation VLSI Design and Simulation Performance Characterization Topics Performance Characterization Resistance Estimation Capacitance Estimation Inductance Estimation Performance Characterization Inverter Voltage

More information

3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti

3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +

More information

ECE 546 Lecture 11 MOS Amplifiers

ECE 546 Lecture 11 MOS Amplifiers ECE 546 Lecture MOS Amplifiers Spring 208 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine Amplifiers Definitions Used to increase

More information

VLSI Design The MOS Transistor

VLSI Design The MOS Transistor VLSI Design The MOS Transistor Frank Sill Torres Universidade Federal de Minas Gerais (UFMG), Brazil VLSI Design: CMOS Technology 1 Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V

More information

Section 12: Intro to Devices

Section 12: Intro to Devices Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon

More information

MOSFET Physics: The Long Channel Approximation

MOSFET Physics: The Long Channel Approximation MOSFET Physics: The ong Channel Approximation A basic n-channel MOSFET (Figure 1) consists of two heavily-doped n-type regions, the Source and Drain, that comprise the main terminals of the device. The

More information

Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University

Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage v gs v i - v o V DD v bs - v o R S Vv IN i v i G C gd C+C gd gb B&D v s vv OUT o + V S I B R L C L v gs - C

More information

N Channel MOSFET level 3

N Channel MOSFET level 3 N Channel MOSFET level 3 mosn3 NSource NBulk NSource NBulk NSource NBulk NSource (a) (b) (c) (d) NBulk Figure 1: MOSFET Types Form: mosn3: instance name n 1 n n 3 n n 1 is the drain node, n is the gate

More information

Chapter 5 MOSFET Theory for Submicron Technology

Chapter 5 MOSFET Theory for Submicron Technology Chapter 5 MOSFET Theory for Submicron Technology Short channel effects Other small geometry effects Parasitic components Velocity saturation/overshoot Hot carrier effects ** Majority of these notes are

More information

6.012 Electronic Devices and Circuits Spring 2005

6.012 Electronic Devices and Circuits Spring 2005 6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):

More information

Robert W. Brodersen EECS140 Analog Circuit Design

Robert W. Brodersen EECS140 Analog Circuit Design INTRODUCTION University of California Berkeley College of Engineering Department of Electrical Engineering and Computer Science Robert. Brodersen EECS40 Analog Circuit Design ROBERT. BRODERSEN LECTURE

More information

Topics to be Covered. capacitance inductance transmission lines

Topics to be Covered. capacitance inductance transmission lines Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of

More information

L ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling

L ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling L13 04202017 ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling Scaling laws: Generalized scaling (GS) p. 610 Design steps p.613 Nanotransistor issues (page 626) Degradation

More information

LECTURE 3 MOSFETS II. MOS SCALING What is Scaling?

LECTURE 3 MOSFETS II. MOS SCALING What is Scaling? LECTURE 3 MOSFETS II Lecture 3 Goals* * Understand constant field and constant voltage scaling and their effects. Understand small geometry effects for MOS transistors and their implications modeling and

More information

The Physical Structure (NMOS)

The Physical Structure (NMOS) The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two

More information

II III IV V VI B C N. Al Si P S. Zn Ga Ge As Se Cd In Sn Sb Te. Silicon (Si) the dominating material in IC manufacturing

II III IV V VI B C N. Al Si P S. Zn Ga Ge As Se Cd In Sn Sb Te. Silicon (Si) the dominating material in IC manufacturing II III IV V VI B N Al Si P S Zn Ga Ge As Se d In Sn Sb Te Silicon (Si) the dominating material in I manufacturing ompound semiconductors III - V group: GaAs GaN GaSb GaP InAs InP InSb... The Energy Band

More information

MOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations

MOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY Volume 10, Number 2, 2007, 189 197 MOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations S. EFTIMIE 1, ALEX. RUSU

More information

A Multi-Gate CMOS Compact Model BSIMMG

A Multi-Gate CMOS Compact Model BSIMMG A Multi-Gate CMOS Compact Model BSIMMG Darsen Lu, Sriramkumar Venugopalan, Tanvir Morshed, Yogesh Singh Chauhan, Chung-Hsun Lin, Mohan Dunga, Ali Niknejad and Chenming Hu University of California, Berkeley

More information

HW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7

HW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7 HW 5 posted due in two weeks Lab this week Midterm graded Project to be launched in week 7 2 What do digital IC designers need to know? 5 EE4 EECS4 6 3 0< V GS - V T < V DS Pinch-off 7 For (V GS V T )

More information

Lecture 11: MOS Transistor

Lecture 11: MOS Transistor Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Cross-section and layout

More information

EE382M-14 CMOS Analog Integrated Circuit Design

EE382M-14 CMOS Analog Integrated Circuit Design EE382M-14 CMOS Analog Integrated Circuit Design Lecture 3, MOS Capacitances, Passive Components, and Layout of Analog Integrated Circuits MOS Capacitances Type of MOS transistor capacitors Depletion capacitance

More information

Quantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current.

Quantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. Quantitative MOSFET Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. V DS _ n source polysilicon gate y = y * 0 x metal interconnect to

More information

Towards a Scalable EKV Compact Model Including Ballistic and Quasi-Ballistic Transport

Towards a Scalable EKV Compact Model Including Ballistic and Quasi-Ballistic Transport 2011 Workshop on Compact Modeling Towards a Scalable EKV Compact Model Including Ballistic and Quasi-Ballistic Transport Christian Enz 1,2, A. Mangla 2 and J.-M. Sallese 2 1) Swiss Center for Electronics

More information

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal

More information

Characteristics of Active Devices

Characteristics of Active Devices 007/Oct/17 1 haracteristics of Active Devices Review of MOSFET Physics MOS ircuit Applications Review of JT Physics MOS Noise JT Noise MS/RF Technology Roadmap MS MOS 1., 1.0, 0.8µm 0.60, 0.50µm 0.45,

More information

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS ) ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets

More information

Section 12: Intro to Devices

Section 12: Intro to Devices Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si

More information

Philips Research apple PHILIPS

Philips Research apple PHILIPS c Electronics N.V. 1997 Modelling Compact of Submicron CMOS D.B.M. Klaassen Research Laboratories The Netherlands Eindhoven, contents accuracy and benchmark criteria new applications í RF modelling advanced

More information

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and

More information

1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012

1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012 /3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS -V th " VGS vi - I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F

More information