University of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA


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1 University of Pennsylvania Department of Electrical Engineering ESE 570 Midterm Exam March 4, 03 FORMULAS AND DATA. PHYSICAL CONSTANTS: n i = intrinsic concentration undoped) silicon =.45 x 0 0 cm 300 o K k = Boltzmans constant =.38 x 03 J/ o K q = electronic charge =.60 x 09 C Å = 08 cm ε Si = permittivity of Si =.06 x 0  F/cm ε SiO = ε ox = permittivity of SiO = 0.34 x 0  F/cm. MOS TRANSISTOR IV CHARACTERITICS for nchannel DEVICE: I D = k n V GS! V [ Tn )V DS! V DS ] + "V DS ) for 0 < V DS < V GS  V Tn ) I D = k n V GS  V Tn ) + λ V DS ) for V DS > V GS  V Tn ) k n = µ n! SiO t ox W n L n a. Threshold Voltage: ) ± qn I V T = V T 0 +! " F + V SB " " F φ F psub) = kt q C ox ln n i N A and φ F nsub) = kt q ln N D n i γ = ε Si qn A C ox 3. CMOS RESISTORS: TABLE Sheet Resistance for Materials in an nwell CMOS process with 3 metal Layers Material Min Typical Max Ω/sq Ω/sq Ω/sq Metal,Metal Metal Polysilicon Silicide 3 6 Diffusion n+,p+) Silicide diffusion 4 0 nwell K K 5K
2  4. CMOS CAPACITORS: C ox = ε ox t ox C GS0 = C ox WL D ) C GD0 = C ox WL D ) C BG0 = C ox W ov L M ) a. MOS Gate Capacitance TABLE Gate Capacitance Capacitor OFF Nonsaturated Saturated C gb total) C ox WL eff + C BG0 C BG0 C BG0 C gs total) C GS0 C ox WL eff 3 C oxwl eff + C GS0 + C GS0 C gd total) C GD0 C oxwl eff C GD0 + C GD b. MOS Diffusion Source/Drain) Capacitance Y 5 3 x j n W + Channel n + 4 Source Drain p  Substrate > N A p +  Channelstop > 0N A Junction Area Type W x j Y x j W x j Y x j WY n + /p n + /p + n + /p + n + /p + n + /p
3 3 C db = A D C j 0 + P D C j 0sw sw) C j V ) = A! C j 0 + V & " 0 where φ 0 = kt q m and C jsw V ) = P!C jsw + V " 0sw & msw) ln N AN D n i and φ 0sw = kt q ln N Asw) N D n i =! 0 ) V " V ) " m j sw) = V " V! 0sw ) + * + + V! 0 ) ) " m j sw) " m j & " + V & ) + V & +! 0sw * + where V V V and V 0, V 0! 0 " m j " m j sw),. . " + V &! 0sw " m j sw),. . C load = C dbn W n ) + C dbp W p ) + C int + C gb c. Routing Capacitance TABLE 3 Typical µm CMOS Capacitances Capacitor Capacitance Description af 08 )/µm C p 50 Poly to substrate  over field oxide C m 30 Metal to substrate  over field oxide C mp 60 Metal to poly C md 60 Metal to diffusion C m 0 Metal to substrate  over field oxide C mm 50 Metal to metal C mp 30 Metal to poly C md 30 Metal to diffusion C m3 0 Metal3 to substrate  over field oxide C m3m 30 Metal3 to metal C m3m 5 Metal3 to metal C m3p Metal3 to poly C m3d 0 Metal3 to diffusion
4 45. SCALING: a. CONSTANT FIELD Scaling: a. All dimensions, including those vertical to the surface /α) b. device voltages /α) c. concentration densities α). b. CONSTANT VOLTAGE Scaling: a. All dimensions, including those vertical to the surface /α) b. device voltages ) c. concentration densities α ). c. LATERAL Scaling: a. gate L /α) only. 6. STATIC/DYNAMIC CHARACTERISTICS OF GATES: a. Temporal Performance Definitions: V 50 = V OL + V OH ) τ PHL = time for output voltage to fall from V OH to V 50. τ PHL = time for output voltage to rise from V OL to V 50. τ P = t PHL + t PHL τ PHL = C load ΔV HL I avghl τ PLH = C load ΔV LH I avglh b. Complementary CMOS Inverter step input): C load τ PHL = k n V DD  V Tn ) [ V Tn V DD  V + ln 4V DD  V Tn ) Tn V  )] DD C load τ PLH = k p V DD  V Tp ) [ V Tp V DD  V Tp + ln 4V DD  V Tp ) V  )] DD V " dv out = k n V in! V Tn )V out! V out k n V in! V Tn V [ ] c. Including t r and t f of input: ) ln V out V in! V Tn )! V out & V out = V V out = V τ PHL actual) = τ PLH actual) = τ PHL step input) + t r ) τ PLH step input) + t f ) d. Super Buffer: a N+ = C LOAD Cg t total = N + )! 0 C d + ac g C d + C g
5 5 a opt [ ln a opt )!] = C d C g 7. NOMINAL SPICE PARAMETERS for µm nwell CMOS PROCESS TABLE 4 Parameter nmos pmos Units VT V KP 8.5 E E5 A/V GAMMA V LAMBDA V  CGS0 6.0 E E0 F/m CGD0 6.0 E E0 F/m CGB0.0 E0.0 E0 F/m CJ 3.0 E E4 F/m MJ CJSW 4.0 E E0 F/m MJSW PB V LD 0. E7 0. E7 m TOX E8 E8 m PHI V NSUB E6 4 E6 cm 3 NFS 5E0 9E0 cm  U cm /Vs XJ.0 E7.0 E7 m DL 0 0 m DW .0 E E7 m 8. nwell CMOS DESIGN RULES Layer/Dimension λ RULE A. Nwell Layer A. Minimum size 0 λ A. Minimum spacing wells at same potential) 6 λ A.3 Minimum spacing wels at different potential) 8 λ B. Active Area B. Minimum size 3 λ B. Minimum spacing 3 λ B.3 Nwell overlap of p+ 5 λ B.4 Nwell overlap of n+ 3 λ B.5 Nwell space to n+ 5 λ B.6 Nwell space to p+ 3 λ C. Poly C. Minimum size λ
6 6 C. Minimum spacing λ C.3 Spacing to n+ or p+ λ C.4 Gate extension λ C.5 Minimum n+ or p+ extension 3 λ E. Contact E. Minimum size λ E. Minimum spacing poly) λ E.3 Minimum spacing n+ or p+) λ E.4 Minimum overlap of n+ or p+ λ E.5 Minimum overlap of poly λ E.6 Minimum overlap of metal λ E.7 Minimum spacing to gate λ F. Metal F. Minimum size 3 λ F. Minimum spacing 3 λ Layer/Dimension λ RULE G. Via G. Minimum size λ G. Minimum spacing 3 λ G.3 Minimum metal overlap λ G.4 Minimum metal overlap λ H. Metal H. Minimum size 3 λ H. Minimum spacing 4 λ I. Via I. Minimum size λ I. Minimum spacing 3 λ J. Metal3 J. Minimum size 8 λ J. Minimum spacing 5 λ J.3 Minimum via overlap λ J.4 Minimum via overlap λ
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