P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions

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1 P. R. Nelson 1 ECE418 - VLSI Midterm Exam Solutions 1. (8 points) Draw the cross-section view for A-A. The cross-section view is as shown below.. ( points) Can you tell which of the metal1 regions is the source of the transistor shown in problem 1? Explain. The metal1 contact on the right in the figure is the source because it is directly connected to the transistor body (n-well).

2 P. R. Nelson 3. (0.5 point each) List the following process steps in the correct order. (a) Deposit field and gate oxides (b) Implant n + and p + (c) Deposit first insulating oxide (d) Deposit and pattern poly (e) Etch contact windows to Si, poly, and metal1 (f) Create the n-wells (g) Apply first metal layer (h) Deposit second insulating oxide (i) Pattern first metal layer (metal1) (j) Etch contact windows to Si and poly (k) Deposit metal f, a, d, b, c, j, g, i, h, e, k 4. (4 points) Briefly explain the effect represented by each of the four terms in the following expression for the threshold voltage of a MOSFET. V T = Φ GC φ F Q B Q ox φ GC φ F Q B / Q ox / work-function difference between gate and channel gate-body voltage to achieve surface inversion voltage due to depletion region (fixed) charge density voltage across gate oxide 5. ( points) In an n-channel MOSFET, does a source-body voltage V SB > 0 increase or decrease the threshold voltage V T? Explain. For an n-channel MOSFET the channel is p-type, so φ F < 0. The change in V T due to V SB is ( V T = V T V T 0,n = γ φf + V SB ) φ F > 0 so V T is increased by a positive V SB. 6. (3 points) A p-channel MOSFET has a threshold voltage V T 0,p = 0.8 V. If the oxide thickness is 500 Å, find the implant type (p or n) and implant dose N I in cm that are required to make V T 0,p = 0.5 V. V T = qn I = 0.5 V ( 0.8 V) = 0.3 V where = ɛ ox t ox N I = V T ɛ ox qt ox = cm and, since the dose is positive, the implant is p-type.

3 P. R. Nelson 3 7. (1 point) What extra step is required (compared to the standard CMOS n-well process) to make depletion-mode NMOS devices? Depletion-mode NMOSFETS require an extra implant of donors in the channel. 8. (0.5 point per answer) In full scaling, the electric field is kept constant, voltages (increase / decrease) by the scale factor S, doping densities (increase / decrease) by S, the oxide capacitance (increases / decreases), and the power dissipation per unit area remains the same. 9. (1 point) Short-channel effects are important under what conditions? Short-channel effects are important when the channel length L is of the same order of magnitude as the source and drain depletion region thickness x j. 10. Assume that both transistors have the same values of k n, W/L, and γ, and that λ = 0. (a) ( points) Do M 1 and M have the same value of V T? Why or why not? No. V SB = 0 for M 1, but not for M. (b) ( points) What mode of operation do you expect for M 1? Why? Linear mode because V GS1 = V DD and M acts as a load, letting V DS1 be relatively small. (c) ( points) What mode of operation do you expect for M? Why? Saturation because V DS = V GS > V GS V T. 11. (1 point) Find the built-in voltage of a p-n junction with N A = cm 3 and N D = cm 3. φ 0 = k BT q ln N AN D n i = V ln (10 10 ) = 0.8 V 1. (3 points) The zero-bias junction capacitance per unit area between the substrate and the drain of an n-channel MOSFET is C j0 = 50 nf cm. If the area of the drain is 5 µm and the applied voltage is V GS = V GB = 4 V, find the plate capacitance of the drain. (Assume an abrupt junction with φ 0 = 0.8 V.) C j (V ) = A C j0 1 V/φ0 where V = 4 V C plate = 5.1 ff 13. ( points) Sketch the circuit diagram which is realized by this layout.

4 P. R. Nelson (3 points) Write the equation you need to solve to find V OL for this circuit. (You don t need to solve it.) To find V OL, set V in = V DD. Then the pfet is off and the nfet is in linear mode. 3 V V OL R i R = i D = 1 k [ n (3 V VT 0 ) V OL VOL] 15. (5 points) Given a symmetric CMOS inverter with a 5 pf load. If µ n (W/L) = 50 µa V = µ p (W/L) and V T 0,n = V t0,p = 0.6 V, explain in detain how you would find τ plh when V DD = 3.3 V using the differential equation method. (You don t have to do any integrals over voltage, but you should show them.) At t = 0, V in makes an instantaneous transition from V DD to 0 V. The nmosfet turns off and the pmosfet is in saturation (because V GS = V DS ). As the capacitance charges to V 50% = V DD /, the pmosfet passes the boundary of saturation at V out = V T 0,p. t V τ 1 = dt = C L i D,p (V out ) t 1 V 1 τ plh = τ p,linear + τ p,sat τ p,linear = C L VT 0,p 0 1 k p [ (V DD + V T 0,p ) V out V out] τ p,sat = C L V50% V T 0,p 1 k p (V DD + V T 0,p ) 16. A CMOS inverter has µ n = 45 µa V, µ p = 15 µa V, V T 0,n = 0.7 V, and V T 0,p = 0.9 V. If V DD = 3.3 V, (a) ( points) Can this inverter be completely symmetric? Why or why not? No because V T 0,n V T 0,p. (b) (3 points) Find (W/L) p /(W/L) n to make V th = V DD /. From the class notes, (W/L) p (W/L) n = ( ) ( ) µn VDD / V T 0,n = 4.81 µ p V DD / + V T 0,p

5 P. R. Nelson For the CMOS inverter in the previous problem, (a) ( points) At what input voltage will the inverter draw the maximum current from the power supply? The maximum current is when both transistors are in saturation. (Note that when λ = 0 the current is independent of V out, so di D / = 0.) This condition occurrs when V in = V th = V DD / = 1.65 V. (b) (3 points) Find the range of possible values of V out for which V in = V DD /. When V in = V DD / = V th and λ = 0, the minimum value V xn of V out for which the nmosfet is in saturation is given by V DS = V GS V T n V xn = V DD V T n = 0.95 V and the maximum value V xp of V out for which the pmosfet is in saturation is found from V DS = V GS V T p V xp V DD = ( VDD V DD ) V T p V xp = V DD V T p =.55 V The range of V out for which V in = V th is thus V out = V xp V xn = 1.60 V

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