Digital Integrated Circuits EECS 312
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1 Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP) NTT Fujitsu M-780 IBM RY5 Jayhawk(dual) IBM RY7 Prescott T-Rex Mckinley Squadrons IBM GP Pentium Radio Receive for Mesh Maintenance 2-6 ma Typical Current Draw 1 sec Heartbeat 30 beats per sample Sampling and Radio Transmission 9-15 ma Low Power Sleep ma Heartbeat 1-2 ma Time (seconds) Digital Integrated Circuits EECS Teacher: Robert Dick Office: 2417-E EECS dickrp@umich.edu Phone: Cellphone: GSI: Office: Shengshou Lu 2725 BBB luss@umich.edu HW engineers SW engineers Current (ma) IBM ES9000 Bipolar CMOS Power density (Watts/cm 2 ) Year of announcement IBM Z9
2 Announcement 1 I will be in Montreal on Tuesday presenting a research paper at Embedded Systems Week. 2 I will lecture at the Friday discussion time and location. 3 Mr. Lu will hold discussion at the Tuesday lecture time slot and location. 2 Robert Dick Digital Integrated Circuits
3 Review 1 How many metal layers are there in modern processes? 2 What is the problem with isotropic etching? 3 Explain a method of anisotropic etching. 4 Why Cu? 5 Why damascene? 6 What is CMP? 7 What is DRC? 3 Robert Dick Digital Integrated Circuits
4 Example low-k dielectric materials Still active area. Porous SiO 2. Carbon-doped SiO 2. Polymer. 4 Robert Dick Digital Integrated Circuits
5 Synchronous integrated circuit organization Combinational networks separated by memory elements. When memory elements clocked, changed signals race through next stage. Clock frequency must be low enough to allow signal to propagate along worst-case combinational path in circuit. Derive and explain. 5 Robert Dick Digital Integrated Circuits
6 Lecture plan Robert Dick Digital Integrated Circuits
7 RC curves f(v i, v f, τ, t) = v f + (v i - v f ) e -t/τ 5 4 V C (V) 3 2 f(0, 5, 1, x) f(5, 0, 1, x) f(0, 5, 5, x) f(5, 0, 5, x) Time (s) v(t) = v f + (v i v f )e t /RC
8 Diode dynamic behavior Vin (V) t (s) I (A) t (s) 8 Robert Dick Digital Integrated Circuits
9 MOSFET capacitances 9 Robert Dick Digital Integrated Circuits
10 Gate capacitance 10 Robert Dick Digital Integrated Circuits
11 Gate capacitance schematic Mode C GCB C GCS C GCD C G Cutoff C ox WL 0 0 C ox WL + 2C O W Triode 0 C ox WL/2 C ox WL/2 C ox WL + 2C O W Saturation 0 2/3C ox WL 0 2/3C ox WL + 2C O W C O is the overlap capacitance. 11 Robert Dick Digital Integrated Circuits
12 Gate capacitance variation with V GS 12 Robert Dick Digital Integrated Circuits
13 Gate capacitance variation with saturation 13 Robert Dick Digital Integrated Circuits
14 Diffusion capacitance diagram 14 Robert Dick Digital Integrated Circuits
15 Diffusion capacitance expression C diff = C bot + C sw C diff = C j A + C jsw P C diff = C j L S W + C jsw (2L S + W ) C bot : Bottom capacitance to substrate. C sw : Side-wall capacitances for three non-channel sides. C j : Junction capacitance constant in F/m 2 (base units). A: Diffusion area. C jsw : Junction side-wall capacitance constant in F/m. P: Perimeter for three non-channel sides. L S : Length of diffusion region. W : Width of diffusion region (and transistor). 15 Robert Dick Digital Integrated Circuits
16 Junction capacitance C jsw is actually the diode capacitance we considered before. What happens as reverse bias increases? Can use worst-case approximation. 16 Robert Dick Digital Integrated Circuits
17 Capacitance linearization I Can approximate variable capacitance as fixed capacitance. Uses fitting. C eq = Q j V D C eq = Q j (V high ) Q j (V low ) V high V low C eq = K eq C j0 φ m 0 K eq = ((φ 0 V high ) 1 m (φ 0 V low ) 1 m) (V high V low ) (1 m) 17 Robert Dick Digital Integrated Circuits
18 Capacitance linearization II C j0 : Capacitance when voltage bias of diode is 0 V. m: Grading coefficient used to model effects of sharp (0.5) or linear (0.33) junction transition (see Page 82 in textbook). ( ) φ 0 = φ T ln NA N D n 2 : Built-in potential, i.e., voltage across i junction due to diffusion at drift diffusion equalibrium. 18 Robert Dick Digital Integrated Circuits
19 Capacitance parameters for default 0.25 µm process technology C OX C O C j (ff/µm 2 ) (ff/µm) (ff/µm 2 ) NMOS PMOS m j φ b C jsw m jsw φ bsw (V) (ff/µm) (V) NMOS PMOS Properties of bottom and sidewall. 19 Robert Dick Digital Integrated Circuits
20 Upcoming topics MOSFET dynamic behavior. Wires. CMOS inverters. 20 Robert Dick Digital Integrated Circuits
21 Review What are the five most important to model capacitances for MOSFETs? Explain their locations/sources. How do they depend on operating region? How are drain and source capacitances calculated? 21 Robert Dick Digital Integrated Circuits
22 Review: diode capacitance C J = C J0 (1 V D /Φ 0 ) m m = 0.5 for abrupt junctions, m = 0.33 for linear junctions
23 A change to gate insulation Mark T. Bohr, Robert S. Chau, Tahir Ghani, and Kaizad Mistry. The High-k Solution. IEEE Spectrum, October What was the problem? What was its cause? What was the solution? Key concepts: gate leakage, tunneling, high-κ dielectric, charge traps, single atomic layer deposition, and threshold voltage control. 23 Robert Dick Digital Integrated Circuits
24 Lecture plan Robert Dick Digital Integrated Circuits
25 Simple inverter context 25 Robert Dick Digital Integrated Circuits
26 Inverter layout 26 Robert Dick Digital Integrated Circuits
27 Implications of cell-based design Power and ground sharing breaks isolation. 27 Robert Dick Digital Integrated Circuits
28 Simplest switch model of inverter 28 Robert Dick Digital Integrated Circuits
29 Switch model transient behavior Repeatedly charging/discharging load C. t phl = f (R on C L ). Why? 29 Robert Dick Digital Integrated Circuits
30 t phl derivation Both t phl and t plh defined as time from 0.5 V DD input crossing to 0.5 V DD output crossing. Assume step function on input. Solve for V C = V DD /2. V C = V DD e t /RC V DD/2 = V DD e t /RC 1/2 = e t /RC (1) (2) (3) ln ( 1 /2) = t /RC (4) t = RC 0.69 (5) t = 0.69RC = 0.69τ (6) 30 Robert Dick Digital Integrated Circuits
31 Lecture plan Robert Dick Digital Integrated Circuits
32 NMOSFET I V characteristics Review: Is this a velocity-saturated short-channel device? How can you tell? 32 Robert Dick Digital Integrated Circuits
33 Inverter load characteristics 33 Robert Dick Digital Integrated Circuits
34 CMOS inverter transfer curve 34 Robert Dick Digital Integrated Circuits
35 Switching threshold derivation I Find voltage for which V in = V out. Known: Both NMOSFET and PMOSFET saturated at this point. Recall that W I DSAT = µc ox ((V GS V T ) V DSAT V DSAT 2 ) L 2 (1) 35 Robert Dick Digital Integrated Circuits
36 Switching threshold derivation II Working to find V M. Find V GS at which NMOSFET and PMOSFET I D values equal. = kv DSAT (V GS V T ) V DSAT ( 2 0 = k n V DSATn V M V Tn V ) DSATn + 2 ( k p V DSATp V M V Tp V ) DSATp 2 (2) (3) 36 Robert Dick Digital Integrated Circuits
37 Switching threshold derivation III Solve for V M. V M = ( V Tn + V DSATn 2 ) ( + r 1 + r V DD + V Tp + V DSATp 2 ). (4) r = k pv DSATp = ν satpw p (5) k n V DSATn ν satn W n µξ ν = (6) 1 + ξ/ξ c ν: Charge carrier speed. ξ: Field strength. ξ c : Field strength at which scattering limits further increase in carrier speed. 37 Robert Dick Digital Integrated Circuits
38 Inverter threshold dependence on transistor conductance ratio 38 Robert Dick Digital Integrated Circuits
39 Upcoming topics CMOS inverter dynamic behavior. Logic gates. 39 Robert Dick Digital Integrated Circuits
40 Lecture plan Robert Dick Digital Integrated Circuits
41 assignment 1 October: Read sections 3.3.3, 5.1, 5.2, 1.3.2, and in J. Rabaey, A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits: A Design Perspective. Prentice-Hall, second edition, Read as much as you can by 27 September. 26 October: Extended 1 due date due to difficulty getting help during office hours. 3 October: Lab Robert Dick Digital Integrated Circuits
1 cover it in more detail right away, 2 indicate when it will be covered in detail, or. 3 invite you to office hours.
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