Lecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010


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1 EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng 6.1
2 Outline Power and Energy Dynamic Power Static Power 6.2
3 Power and Energy Power is drawn from a voltage source attached to the V DD pin(s) of a chip. Instantaneous Power: Pt () = ItV () () t Energy: Average Power: E P avg T = Ptdt () 0 T = E 1 T = T 0 Ptdt () 6.3
4 Power in Circuit Elements () = ( ) P t I t V VDD DD DD () t 2 VR 2 PR() t = = IR() t R R dv E C = I ( t ) V ( t ) dt = C V ( t ) dt dt () 0 0 V C = C V t dv = CV C 6.4
5 Charging ga Capacitor When the gate output rises Energy stored in capacitor is E = CV 1 2 C 2 L DD But energy drawn from the supply is dv EVDD = I( t) VDDdt = CL VDDdt dt 0 0 VDD 2 CV L DD dv CV L DD 0 = = Half the energy from V DD is dissipated in the pmos transistor as heat, other half stored in capacitor When the gate output falls Energy in capacitor is dumped to GND Dissipated as heat in the nmos transistor 6.5
6 Switching Waveforms Example: V DD = 1.0 V, C L = 150 ff, f = 1 GHz 6.6
7 Switching Power 1 T Pswitching = idd () t VDDdt T 0 T VDD = i T 0 DD VDD = T = CV f () t dt [ Tf CV ] 2 DD sw sw DD VDD i DD (t) f sw C 6.7
8 Activity Factor Suppose the system clock frequency = f Let f sw = αf, where α = activity factor If the signal is a clock, α = 1 If the signal switches once per cycle, α = ½ Dynamic power: 2 Pswitching = α CVDD f 6.8
9 Short Circuit Current When transistors switch, both nmos and pmos networks may be momentarily ON at once Leads to a short circuit current. < 10% of dynamic power if rise/fall times are comparable for input and output We will generally ignore this component 6.9
10 Power Dissipation Sources P total = P dynamic + P static Dynamic power: P dynamic = P switching + P shortcircuit Switching load capacitances Shortcircuit current Static power: P static = (I sub + I gate + I junct + I contention )V DD Subthreshold leakage Gate leakage Junction leakage Contention current 6.10
11 Dynamic Power Example 1 billion transistor chip 50M logic transistors Average width: 12 λ Activity factor = M memory transistors Average width: 4 λ Activity factor = V 65 nm process C = 1 ff/μm (gate) ff/μm (diffusion) i Estimate dynamic power 1 GHz. Neglect wire capacitance and shortcircuit current. 6.11
12 Solution ( 6 )( λ )( μ λ )( f μ ) C logic = m/ 1.8 ff / m = 27 nf mem ( 6 )( λ)( μ λ)( μ ) C = m/ 1.8 ff / m = 171 nf 2 ( dynamic logic mem ) ( ) P = 0.1 C C GHz = 6.1 W 6.12
13 Dynamic Power Reduction 2 Pswitching = αcvdd f Try to minimize: Activity factor Capacitance Supply voltage Frequency 6.13
14 Activity Factor Estimation Let P i = Prob(node i = 1) P i = 1P i α i = P i * P i Completely random data has P = 0.5 and α = 0.25 Data is often not completely random e.g. upper bits of 64bit words representing bank account balances are usually 0 Data propagating through ANDs and ORs has lower activity factor Depends on design, but typically α
15 Switching Probability 6.15
16 Example A 4input AND is built out of two levels of gates Estimate the activity factor at each node if the inputs have P =
17 Clock Gating The best way to reduce the activity is to turn off the clock to registers in unused blocks Saves clock activity (α = 1) Eliminates all switching activity in the block Requires determining if block will be used 6.17
18 Capacitance Gate capacitance Fewer stages of logic Small gate sizes Wire capacitance Good floorplanning l to keep communicating blocks close to each other Drive long wires with inverters or buffers rather than complex gates 6.18
19 Voltage / Frequency Run each block at the lowest possible voltage and frequency that meets performance requirements Voltage Domains Provide separate supplies to different blocks Level converters required when crossing from low to high V DD domains Dynamic Voltage Scaling Adjust V DD and f according to workload 6.19
20 Static Power Static power is consumed even when chip is quiescent. Leakage draws power from nominally OFF devices Ratioed circuits burn power in fight between ON transistors 6.20
21 Static Power Example Revisit power estimation for 1 billion transistor chip Estimate static power consumption Subthreshold leakage Normal V t : 100 na/μm High V t : 10 na/μm High Vt used in all memories and in 95% of logic gates Gate leakage 5 na/μm Junction leakage negligible 6.21
22 Solution t ( )( )( )( ) W λ μ λ μ W 6 6 normalv = m / 0.05 = m highv t ( )( )( ) ( )( ) ( ) = + = λ λ 0.025μm / λ μm Isub = WnormalV 100 na/ μm+ W t highv 10 na/ μm / 2 = 584 ma t ( ) Igate = WnormalV + W t highv 5 na/ μm / 2 = 275 ma t P = ( 584 ma + static 275 ma)( 1.0 V) = 859 mw 6.22
23 Subthreshold Leakage For V ds > 50 mv Typical values in 65 nm Vgs+ η( Vds VDD) kγvsb I off = 100 V t = 0.3 V S Isub Ioff 10 I off = 10 V t = 0.4 V I off = 1 V t = 0.5 V η = I off = leakage at V gs = 0, V ds = V DD k γ = 0.1 S = 100 mv/decade 6.23
24 Stack Effect Series OFF transistors have less leakage V x > 0, so N2 has negative V gs ( V V ) η( ( ) ) η x DD V + V V V k V S S Isub = Ioff 10 = Ioff 10 N2 N1 x DD x DD γ x V x ηvdd = 1 + 2η + k γ 1+ η + kγ ηvdd 1 2η k + + γ ηv S S sub = off 10 off 10 I I I Leakage through 2stack reduces ~10x Leakage through 3stack reduces further DD 6.24
25 Leakage Control Leakage and delay trade off Aim for low leakage in sleep and low delay in active mode To reduce leakage: Increase V t : multiple V t Use low V t only in critical circuits t Increase V s : stack effect Input vector control in sleep Decrease V b Reverse body bias in sleep Or forward body bias in active mode 6.25
26 Gate Leakage Extremely strong function of t ox and V gs Negligible for older processes Approaches subthreshold leakage at 65 nm and below in some processes An order of magnitude less for pmos than nmos Control leakage in the process using t ox > 10.5 Å Highk gate dielectrics help Some processes provide multiple t ox e.g. thicker oxide for 3.3 V I/O transistors Control leakage in circuits by limiting V DD 6.26
27 NAND3 Leakage Example 100 nm process I gn = 6.3 na I gp = 0 I offn = 5.63 na I offp = 9.3 na Data from [Lee03] 6.27
28 Junction Leakage From reversebiased pn junctions Between diffusion and substrate or well Ordinary diode leakage is negligible Bandtoband tunneling (BTBT) can be significant ifi Especially in highv t transistors where other leakage is small Worst at V db = V DD Gateinduced drain leakage (GIDL) exacerbates Worst for V gd = V DD (or more negative) 6.28
29 Power Gating Turn OFF power to blocks when they are idle to save leakage Use virtual V DD (V DDV ) Gate outputs t to prevent invalid logic levels to next block Voltage drop across sleep transistor degrades performance during normal operation Size the transistor wide enough to minimize impact Switching wide sleep transistor costs dynamic power Only justified when circuit sleeps long enough 6.29
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