Dynamic operation 20


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1 Dynamic operation 20 A simple model for the propagation delay Symmetric inverter (rise and fall delays are identical) otal capacitance is linear t p Minimum length devices R W C L t = 0.69R C = p W L 0.69 RC (1 + C / C ) = W int ext int t (1 + C / C ) p0 ext int t p0 C ext /C int Propagation delay vs. C ext /C int ratio R W C L =C int +C ext C int intrinsic (selfloading) output capacitance C ext extrinsic load capacitance (fanout + wiring) 1. t p0 (for minimuml devices) is independent of the sizing (W s) of the gate; 2. Making W infinitely large eliminates the impact of any external load 1
2 Dynamic operation 21 Inverter Delay Minimum length devices Assume that for W P = 2W N =2W same pullup and pulldown currents approx. equal resistances R N = R P approx. equal rise t plh and fall t phl delays Analyze as an RC network 2W W Inverter 1 1 W R N unit W unit WP R P = Runit = RN = W unit Delay (D): t phl = (ln 2) R N C L Load for previous stage: C = 3 gin R W t plh = (ln 2) R P C L W W unit C unit 2W unit W unit Unit inverter 2
3 Dynamic operation 22 Inverter Delay C P = 2C unit 2W Delay W C int C ext C N = C unit Delay = 0.69R W (C int + C ext ) = 0.69R W C int R W C ext = 0.69R W C int (1+ C ext /C int ) = Delay (Internal) + Delay (Load) Load Note: R W L/W C int WL 3
4 Dynamic operation 23 Delay Formula Delay ~ R ( C + C ) W int ext int ( + ) = ( γ ) t p = kr C C / C t 1 + W 1 ext int p 0 f / C int = γc gin with γ 1 f = C ext /C gin  effective fanout R = R unit /W ; C int =WC unit t p0 = 0.69R unit C unit Note: R W L/W C int WL t p0 L 2 minimum L for minimum delay 4
5 Dynamic operation 24 Ring oscillators  1 N: (odd) number of inverters (usually >5) int ( + ) = ( ) t p = kr C C / C t 1+ f W 1 ext int p0 /γ C int = γc gin with γ 1 f = C ext /C gin =1 f osc 1 1 = tp = 2Nt 2Nf p osc Ring oscillators are used as process monitors to verify if a chip is faster or slower than nominally expected. Ex: 31stage ring oscillator in a 180 nm process oscillates at 540 MHz. Sources: Rabaey Weste 5
6 Dynamic operation 25 Ring oscillators  2 N: (odd) number of inverters (usually >5) Source: 6
7 Dynamic operation 26 Inverter chain  1 In Out C L If C L is given:  How many stages are needed to minimize the delay?  How to size the inverters? May need some additional constraints. 7
8 Dynamic operation 27 Inverter chain  2 jth inverter C g,j ( 1 + / γ ) ( 1 / γ ) t = t + C C = t + f p, j p0 g, j 1 g, j p0 j In Out C int =γc g.j C g,j N C L N N ( ) tp = tpj, = tp0 1 + Cgj, + 1 / γcgj, ; CgN, + 1= C N1 unknowns: C L g,2, C g,3, j= 1 j= 1.C g,n1, C g,n First inverter is minimally sized 8
9 Dynamic operation 28 Inverter chain  3 N N ( γ ) Let s minimize t = t = t 1 + C / C ; C = C p pj, p0 gj, + 1 gj, gn, + 1 L j= 1 j= 1 aking the N1 derivatives partial derivatives Cg, j = Cg, j 1 Cg, j+ 1 and equating them to 0 we find that hus, each inverter is sized up by the same factor f wrt the preceding gate he minimum delay is 0 N p p p0 j= 1 f = C / C = C / C = N F g, j+ 1 g, j N L g,1 ( ) ( N 1 / γ 1 / γ ) t = t + f = Nt + F What s N that minimizes delay? 9
10 Dynamic operation 29 Inverter chain N p p p0 j= 1 ( ) ( N 1 / γ 1 / γ ) t = t + f = Nt + F he minimum delay is for N obtained from or, equivalently Canonical case: γ =0 In ( F N) γ + N F 1 ln / = 0 ( 1 + / f ) f = e γ 1 e e N1 dt p /dn=0 (,1 ) f = e, N = ln F = ln CL / Cg (,1 ) t = et ln C / C p pi L g Out t pi : propagation delay of unit inverter loaded with another unit inverter C g,1 C L 10
11 Dynamic operation 30 Inverter chain  5 Optimum effective fanout f f = exp( 1+ γ f ) f opt = 3.6 for γ=1 11
12 Dynamic operation 31 Inverter chain  6 Buffer Design N f t p 1 64 Small area and power and close to minimum t p Sources: Weste and Rabaey * Values normalized to t po 12
13 Power, energy, and energy delay 1 Power is drawn from a voltage source attached to the V DD pin(s) of a chip. Instantaneous Power: Delivered by the power source Energy: Average Power: pt () = itvt ()() pt () i () tv E = ptdt () = itvtdt ()() P avg 0 0 = DD DD E 1 = = itvtdt ()() 0 Source: Weste 13
14 Power, energy, and energy delay 2 Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking diodes and transistors 14
15 Power, energy, and energy delay 3 Dynamic Power Dissipation V DD V I i DD (t) f sw V I VO C v o Energy delivered by the power supply (E DD ) to charge C DD V 2 () () DD DD DD DD DD DD o DD E = i t V dt = V i t dt = V Cdv = CV he energy stored in the fully charged capacitor is V 2 = = DD VDD C o C o o = E v i dt v Cdv C Where s the other half of the energy delivered by V DD? 15
16 Power, energy, and energy delay 4 Dynamic Power Dissipation V DD V I i DD (t) f sw V I VO C v o Where s the energy delivered by V DD? During the 1 0 transition of the output, the energy stored on C is dissipated into the nchannel transistor One half of the energy is stored in C whereas the other half is converted into heat in the pullup network 2 ( p) = DD E M CV 2 ( ) = 2 /2 E M CV N DD HEA 16
17 Power, energy, and energy delay 5 Dynamic Power Dissipation V DD i DD (t) V I f sw V I VO C v o VDD DD DD DD Pdynamic = i () t V dt = i () t dt V [ ] DD = sw DD = f CV CV f 2 DD sw clock frequency = f ck f sw = αf ck, α activity factor For low power reduce C, V DD, and f sw Source: Weste 17
18 Power, energy, and energy delay 6 Dynamic Power Dissipation Example: f sw V DD V DD =2.5 V C=6 ff t p =50 ps C Energy delivered by the power supply (E DD ) to charge C 2 2 EDD = CV DD = = 37.5 fj Assume that f ck =1/4t p =5 GHz For f sw =f ck =5 GHz, the average dynamic power dissipation is P CV f μ 2 dynamic = DD sw = fj GHz=187.5 W For an activity factor of 0.1, the average dynamic power dissipation is ~ 18 μw One million identical inverters with the same activity factor of 0.1 would give a total power dissipation of ~ 18 W Source: Weste 18
19 Power, energy, and energy delay 7 Short Circuit Currents When transistors switch, both nmos and pmos transistors may be momentarily ON at once ypically < 10% of dynamic power if rise/fall times are comparable for input and output Vdd 0.15 Vin Vout IV DD (ma) C L V in (V)
20 Power, energy, and energy delay 8 Short Circuit Currents 20
21 Power, energy, and energy delay 9 Short Circuit Currents Minimizing ShortCircuit Power Vdd =3.3 P norm 4 3 Vdd = Vdd = t sin /t sout 21
22 Power, energy, and energy delay 10 Leakage static dissipation Vdd ReverseBiased Diode Leakage GAE Vout Drain Junction Leakage Subhreshold Current p + p+ N +  V dd I DL = J S A Reverse Leakage Current Subthreshold current one of most compelling issues in lowenergy circuit design! 22
23 Power, energy, and energy delay 11 Leakage static dissipation ~ ~ 23
24 Power, energy, and energy delay 12 Leakage static dissipation Subthreshold Leakage Component In our simplified model, currents for V GS below V were assumed to be zero. However, subthreshold current is very important, especially for advanced technologies (low V s) and can be the major component of power dissipation. 24
25 Power, energy, and energy delay 13 Leakage static dissipation Static power is due to the current that flows between supply rails in the absence of switching activity P = I V stat stat DD P = P + P tot stat dyn Diode leakage + subthreshold current Charge/discharge Cs + shortcircuit current P tot P stat 0 f sw 25
26 Power, energy, and energy delay 14 PowerDelay Product (PDP) =Average energy consumed 2 per switching event (0 1 or 1 0) EnergyDelay Product (EDP) = quality metric of gate = E t p 2 CVDD EDP = PDP t p = t 2 p PDP = Energy delay CV DD 2 Energy Delay V DD 26
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