Digital Integrated Circuits A Design Perspective

Size: px
Start display at page:

Transcription

1 Designing ombinational Logic ircuits dapted from hapter 6 of Digital Integrated ircuits Design Perspective Jan M. Rabaey et al. opyright 2003 Prentice Hall/Pearson 1 ombinational vs. Sequential Logic In ombinational Logic ircuit In ombinational Logic ircuit State ombinational Sequential put = f(in) put = f(in, Previous In) 2

2 Static MOS ircuit t every point in time (except during the switching transients) each gate output is connected to either or V ss via a low-resistive path. The outputs of the gates assume at all times the value of the oolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. 3 Static omplementary MOS In1 In2 InN In1 In2 InN PUN PDN PMOS only NMOS only F(In1,In2, InN) PUN and PDN are dual logic networks 4

3 NMOS Transistors in Series/Parallel onnection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high X Y Y = X if and X Y Y = X if OR NMOS Transistors pass a strong 0 but a weak 1 5 PMOS Transistors in Series/Parallel onnection PMOS switch closes when switch control input is low X Y Y = X if ND = + X Y Y = X if OR = PMOS Transistors pass a strong 1 but a weak 0 6

4 Threshold Drops PUN S D D 0 V GS S 0 -V Tn L L PDN D L 0 V GS S L V Tp S D 7 omplementary MOS Logic Style 8

5 Example Gate: NND 9 Example Gate: NOR 10

6 omplex MOS Gate D D OUT = D + ( + ) 11 onstructing a omplex Gate D F SN1 D F SN4 SN2 SN3 D F (a) pull-down network (b) Deriving the pull-up network hierarchically by identifying sub-nets D (c) complete gate 12

7 ell Design Standard ells General purpose logic an be synthesized Same height, varying width Datapath ells For regular, structured designs (arithmetic) Includes some wiring in the cell Fixed height and width 13 Standard ell Layout Methodology 1980s Routing channel signals GND 14

8 Standard ell Layout Methodology 1990s Mirrored ell No Routing channels M2 M3 GND Mirrored ell GND 15 Standard ells N Well ell height 12 metal tracks Metal track is approx. 3λ + 3λ Pitch = repetitive distance between objects ell height is 12 pitch 2λ In ell boundary GND Rails ~10λ 16

9 Standard ells With minimal diffusion routing With silicided diffusion In M 2 In In M 1 GND GND 17 Standard ells 2-input NND gate GND 18

10 Stick Diagrams ontains no dimensions Represents relative positions of transistors Inverter NND2 GND In GND 19 Stick Diagrams j Logic Graph X PUN X = ( + ) X i i j GND PDN 20

11 Two Versions of ( + ) X X GND GND 21 onsistent Euler Path X X i j GND 22

12 OI22 Logic Graph X PUN D D X = (+) (+D) X D D GND PDN 23 Example: x = ab+cd x x b c b c x x a d a d GND GND (a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d} x GND a b c d (c) stick diagram for ordering {a b c d} 24

13 Multi-Fingered Transistors One finger Two fingers (folded) Less diffusion capacitance 25 Properties of omplementary MOS Gates Snapshot High noise margins: V OH and V OL are at and GND, respectively. No static power consumption: There never exists a direct path between and V SS (GND) in steady-state mode. omparable rise and fall times: (under appropriate sizing conditions) 26

14 MOS Properties Full rail-to-rail swing; high noise margins Logic levels not dependent upon the relative device sizes; ratioless lways a path to Vdd or Gnd in steady state; low output impedance Extremely high input resistance; nearly zero steady-state input current No direct path steady state between power and ground; no static power dissipation Propagation delay function of load capacitance and resistance of transistors 27 Switch Delay Model R eq R p R p R p R p R n L R n L R p int R n NND2 int INV R n R n L NOR2 28

15 Input Pattern Effects on Delay R p R n R n R p L int Delay is dependent on the pattern of inputs Low to high transition both inputs go low delay is 0.69 R p /2 L one input goes low delay is 0.69 R p L High to low transition both inputs go high delay is R n L 29 Delay Dependence on Input Patterns Voltage [V] ==1 0 =1, =1 0 =1 0, = time [ps] Input Data Pattern ==0 1 =1, =0 1 = 0 1, =1 ==1 0 =1, =1 0 = 1 0, =1 Delay (psec) NMOS = 0.5µm/0.25 µm PMOS = 0.75µm/0.25 µm L = 100 ff

16 Transistor Sizing R p R p R p 2 R n L 4 R p int 2 R n int 1 R n R n 1 L 31 Transistor Sizing a omplex MOS Gate D 4 6 D OUT = D + ( + ) 32

17 Fan-In onsiderations D D L Distributed R model (Elmore delay) t phl = 0.69 R eqn ( L ) Propagation delay deteriorates rapidly as a function of fan-in quadratically in the worst case. 33 t p as a Function of Fan-In t p (psec) t phl t plh linear fan-in t p quadratic Gates with a fan-in greater than 4 should be avoided. 34

18 t p as a Function of Fan- t p (psec) t p NOR2 t p NND2 t p INV eff. fan-out ll gates have the same drive current. Slope is a function of driving strength 35 t p as a Function of Fan-In and Fan- Fan-in: quadratic due to increasing resistance and capacitance Fan-out: each additional fan-out gate adds two gate capacitances to L t p = a 1 FI + a 2 FI 2 + a 3 FO 36

19 Fast omplex Gates: Design Technique 1 Transistor sizing as long as fan-out capacitance dominates Progressive sizing In N MN L Distributed R line In 3 M3 3 M1 > M2 > M3 > > MN (the fet closest to the output is the smallest) In 2 In 1 M2 M1 2 1 an reduce delay by more than 20%; decreasing gains as technology shrinks 37 Fast omplex Gates: Design Technique 2 Transistor ordering critical path critical path In 3 1 In 2 1 In M3 0 1 charged L In 1 M3 charged L M2 2 charged In 2 1 M2 2 discharged In M1 charged 3 1 M1 discharged 1 1 delay determined by time to discharge L, 1 and 2 delay determined by time to discharge L 38

20 Fast omplex Gates: Design Technique 3 lternative logic structures F = DEFGH 39 Fast omplex Gates: Design Technique 4 Isolating fan-in from fan-out using buffer insertion L L 40

21 Fast omplex Gates: Design Technique 5 Reducing the voltage swing t phl = 0.69 (3/4 ( L )/ I DSTn ) = 0.69 (3/4 ( L V swing )/ I DSTn ) linear reduction in delay also reduces power consumption ut the following gate is much slower! Or requires use of sense amplifiers on the receiving end to restore the signal level (memory design) 41 Ratioed Logic 42

22 Ratioed Logic Resistive Load R L F Depletion Load V T < 0 F PMOS Load V SS F In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN V SS V SS V SS (a) resistive load (b) depletion load NMOS (c) pseudo-nmos Goal: to reduce the number of devices over complementary MOS 43 Ratioed Logic Resistive Load R L N transistors + Load V OH = F V OL = R PN R PN + R L In 1 In 2 In 3 PDN ssymetrical response Static power consumption V SS t pl = 0.69 R L L 44

23 ctive Loads Depletion Load V T < 0 PMOS Load F V SS F In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN V SS V SS depletion load NMOS pseudo-nmos 45 Pseudo-NMOS D F L V OH = (similar to complementary MOS) V2 k n ( V OL k DD V Tn )V p OL = ( V 2 2 DD V Tp ) 2 V OL ( V DD V T ) 1 1 k p = (assuming that V k T = V Tn = V Tp ) n SMLLER RE & LOD UT STTI POWER DISSIPTION!!! 46

24 Pseudo-NMOS VT W/L p = 4 V out [V] W/L p = W/L p = 0.5 W/L p = 0.25 W/L p = V in [V] 47 Improved Loads Enable M1 M2 M1 >> M2 F D L daptive Load 48

25 Improved Loads (2) M1 M2 PDN1 PDN2 V SS V SS Differential ascode Voltage Switch Logic (DVSL) 49 DVSL Example XOR-NXOR gate 50

26 DVSL Transient Response 2.5 V ol ta ge [V] ,, Time [ns] 51 Pass-Transistor Logic 52

27 Pass-Transistor Logic Inputs Switch Network N transistors No static consumption 53 Example: ND Gate 0 F = 54

28 NMOS-Only Only Logic In x 0.5µm/0.25µm 1.5µm/ 0.25µm 0.5µm/ 0.25µm Voltage [V] x In Time [ns] 55 NMOS-only Switch = 2.5V = 2.5 V = 2.5 V = 2.5 V M n M 2 L M 1 V does not pull up to 2.5V, but 2.5V -V TN Threshold voltage loss causes static power consumption NMOS has higher threshold than PMOS (body effect) 56

29 NMOS Only Logic: Level Restoring Transistor Level Restorer M n M r X M 2 M 1 dvantage: Full Swing Restorer adds capacitance, takes away pull down current at X Ratio problem 57 Restorer Sizing Voltage [V] W/L r =1.75/0.25 W/L r =1.50/0.25 W/L r =1.0/0.25 W/L r =1.25/0.25 Upper limit on restorer size Pass-transistor pull-down can have several transistors in stack Time [ps] 58

30 Solution 2: Single Transistor Pass Gate with V T =0 0V 2.5V 0V 2.5V WTH OUT FOR LEKGE URRENTS 59 omplementary Pass Transistor Logic Pass-Transistor Network F (a) Inverse Pass-Transistor Network F F= F=+ F= ΒÝ (b) F= F=+ F= ΒÝ ND/NND OR/NOR EXOR/NEXOR 60

31 Solution 3: Transmission Gate = 2.5 V = 2.5 V L = 0 V 61 Resistance of Transmission Gate 30 R n 2.5 V Rn Resistance, ohms R p R n R p 2.5 V 0 V R p V ou t V ou t, V 62

32 Pass-Transistor ased Multiplexer S S S M 2 S F M 1 S GND In 1 S S In 2 63 Transmission Gate XOR M2 M1 F M3/M4 64

33 Delay in Transmission Gate Networks In V 1 V i-1 V i V i+1 V n-1 V n (a) In R eq R V eq R eq R 1 V i V i+1 V eq n-1 V n m (b) R eq R eq R eq R eq R eq R eq In (c) 65 Delay Optimization 66

34 Transmission Gate Full dder P P i i P S Sum Generation P P P o arry Generation i i Setup i P Similar delays for sum and carry 67 Dynamic Logic 68

35 Dynamic MOS In static circuits at every point in time (except when switching) the output is connected to either GND or via a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type) transistors 69 Dynamic Gate In 1 In 2 In 3 PDN M e L M e Two phase operation Precharge (LK = 0) Evaluate (LK = 1) 70

36 Dynamic Gate In 1 In 2 In 3 PDN M e L Two phase operation Precharge ( = 0) Evaluate ( = 1) M e off on off on 1 (()+) 71 onditions on put Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. put can be in the high impedance state during and after evaluation (PDN off), state is stored on L 72

37 Properties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary MOS) Full swing outputs (V OL = GND and V OH = ) Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance ( in ) reduced load capacitance due to smaller output loading (out) no I sc, so all the current provided by PDN goes into discharging L 73 Properties of Dynamic Gates Overall power dissipation usually higher than static MOS no static current path ever exists between and GND (including P sc ) no glitching higher transition probabilities extra load on PDN starts to work as soon as the input signals exceed V Tn, so V M, V IH and V IL equal to V Tn low noise margin (NM L ) Needs a precharge/evaluate clock 74

38 Issues in Dynamic Design 1: harge Leakage LK M e L V Evaluate Precharge Leakage sources Dominant component is subthreshold current 75 Solution to harge Leakage Keeper M kp L M e Same approach as level restorer for pass-transistor logic 76

39 Issues in Dynamic Design 2: harge Sharing L harge stored originally on L is redistributed (shared) over L and leading to reduced robustness =0 M e 77 harge Sharing Example L =50fF a =15fF! b =15fF c =15fF d =10fF 78

40 harge Sharing case 1) if V out < V Tn L = L V out ( t) + a ( V Tn ( V X )) M a X L V out or = V out ( t) = a V ( DD V Tn ( V X )) L = 0 M b a case 2) if V out > V Tn M e b a V out = a + L 79 Solution to harge Redistribution M kp M e Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power) 80

41 Issues in Dynamic Design 3: ackgate oupling =0 L1 1 =1 2 =0 L2 In =0 M e Dynamic NND Static NND 81 ackgate oupling Effect 3 Voltage In Time, ns

42 Voltage Issues in Dynamic Design 4: lock Feedthrough M e L oupling between and input of the precharge device due to the gate to drain capacitance. So voltage of can rise above. The fast rising (and falling edges) of the clock couple to. 83 lock Feedthrough 2.5 lock feedthrough In 1 In In 3 In In & Time, ns 1 lock feedthrough 84

43 Other Effects apacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce) 85 ascading Dynamic Gates V In 1 2 In M e M e 1 V Tn 2 V t Only 0 1 transitions allowed at inputs! 86

44 Domino Logic In 1 In PDN In 4 M kp PDN 2 In 3 In 5 M e M e 87 Why Domino? In i In j PDN In i PDN In i PDN In i PDN In j In j In j Like falling dominos! 88

45 Properties of Domino Logic Only non-inverting logic can be implemented Very high speed static inverter can be skewed, only L-H transition Input capacitance reduced smaller logical effort 89 Designing with Domino Logic 1 M r 2 In 1 In 2 PDN In 4 PDN In 3 an be eliminated! M e M e Inputs = 0 during precharge 90

46 Footless Domino 1 2 n In In In 3 In n The first gate in the chain needs a foot switch Precharge is rippling short-circuit current solution is to delay the clock for each stage 91 Differential (Dual Rail) Domino = off on M kp M kp !! = M e Solves the problem of non-inverting logic 92

47 np-mos In 1 In 2 In 3 PDN M e In 4 In 5 M e PUN (to PDN) Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN 93 NOR Logic In 1 In 2 In 3 PDN M e In 4 In 5 M e PUN (to PDN) to other PDN s to other PUN s WRNING: Very sensitive to noise! 94

Properties of CMOS Gates Snapshot

MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)

9/18/2008 GMU, ECE 680 Physical VLSI Design

ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design

Digital EE141 Integrated Circuits 2nd Combinational Circuits

Digital Integrated Circuits Designing i Combinational Logic Circuits 1 Combinational vs. Sequential Logic 2 Static CMOS Circuit t every point in time (except during the switching transients) each gate

-Spring 2004 Digital Integrated ircuits Lecture 15 Logical Effort Pass Transistor Logic 1 dministrative Stuff First (short) project to be launched next Th. Overall span: 1 week Hardware lab this week Hw

COMBINATIONAL LOGIC. Combinational Logic

COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-cmos Combinational vs. Sequential Logic In Logic

Digital Integrated Circuits A Design Perspective

igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational

EE141Microelettronica. CMOS Logic

Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit

Pass-Transistor Logic

-all 26 Digital tegrated ircuits nnouncements No new homework this week roject phase one due on Monday Midterm 2 next Thursday Review session on Tuesday Lecture 8 Logic Dynamic Logic EE4 EE4 2 lass Material

Based on slides/material by. Topic 3-4. Combinational Logic. Outline. The CMOS Inverter: A First Glance

ased on slides/material by Topic 3 J. Rabaey http://bwrc.eecs.berkeley.edu/lasses/icook/instructors.html Digital Integrated ircuits: Design Perspective, Prentice Hall D. Harris http://www.cmosvlsi.com/coursematerials.html

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Views / bstractions / Hierarchies ehavioral Structural

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits Design Perspective Jan M. Rabaey nantha Chandrakasan orivoje Nikolić Designing Combinational Logic Circuits November 2002. 1 Combinational vs. Sequential Logic In Combinational

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC Dynamic Logic Introduction Digital IC 2 EE141 Dynamic

COMP 103. Lecture 16. Dynamic Logic

COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03

EECS 141 F01 Lecture 17

EECS 4 F0 Lecture 7 With major inputs/improvements From Mary-Jane Irwin (Penn State) Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND

Static CMOS Circuits

Static MOS ircuits l onventional (ratio-less) static MOS» overed so far l Ratio-ed logic (depletion load, pseudo nmos) l ass transistor logic ombinational vs. Sequential Logic In Logic ircuit In Logic

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo

Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Dynamic Logic Introduction Digital IC EE141 2 Dynamic logic outline Dynamic logic principle Dynamic logic

CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic

CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411

CPE/EE 427, CPE 527 VLSI Design I Pass Transistor Logic. Review: CMOS Circuit Styles

PE/EE 427, PE 527 VLI Design I Pass Transistor Logic Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: MO ircuit

CPE/EE 427, CPE 527 VLSI Design I L07: CMOS Logic Gates, Pass Transistor Logic. Review: CMOS Circuit Styles

PE/EE 427, PE 527 VLI esign I L07: MO Logic Gates, Pass Transistor Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka

CMOS Digital Integrated Circuits Lec 10 Combinational CMOS Logic Circuits

Lec 10 Combinational CMOS Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic circuit Out In Combinational Logic circuit Out State Combinational The output is determined only by

CMOS logic gates. João Canas Ferreira. March University of Porto Faculty of Engineering

CMOS logic gates João Canas Ferreira University of Porto Faculty of Engineering March 2016 Topics 1 General structure 2 General properties 3 Cell layout João Canas Ferreira (FEUP) CMOS logic gates March

Miscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]

Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an N-Switch, the

Integrated Circuits & Systems

Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 16 CMOS Combinational Circuits - 2 guntzel@inf.ufsc.br

ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018

ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018 ΔΙΑΛΕΞΗ 11: Dynamic CMOS Circuits ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ttheocharides@ucy.ac.cy) (ack: Prof. Mary Jane Irwin and Vijay Narayanan) [Προσαρμογή από

Topics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut

Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance

B.Supmonchai August 1st, q In-depth discussion of CMOS logic families. q Optimizing gate metrics. q High Performance circuit-design techniques

ugust st, 4 Goals of This hapter hapter 6 Static MOS ircuits oonchuay Supmonchai Integrated esign pplication Research (IR) Laboratory ugust, 4; Revised - June 8, 5 In-depth discussion of MOS logic families

CPE/EE 427, CPE 527 VLSI Design I L18: Circuit Families. Outline

CPE/EE 47, CPE 57 VLI Design I L8: Circuit Families Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe57-05f

EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University

EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time

EEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this

VLSI Design I; A. Milenkovic 1

PE/EE 47, PE 57 VLI esign I L6: tatic MO Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka ) www. ece.uah.edu/~milenka/cpe57-3f

VLSI Design I; A. Milenkovic 1

ourse dministration PE/EE 47, PE 57 VLI esign I L6: omplementary MO Logic Gates epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka

VLSI Design I; A. Milenkovic 1

ourse dministration PE/EE 47, PE 57 VLI esign I L6: tatic MO Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka )

Static CMOS Circuits. Example 1

Static CMOS Circuits Conventional (ratio-less) static CMOS Covered so far Ratio-ed logic (depletion load, pseudo nmos) Pass transistor logic ECE 261 Krish Chakrabarty 1 Example 1 module mux(input s, d0,

CPE/EE 427, CPE 527 VLSI Design I Delay Estimation. Department of Electrical and Computer Engineering University of Alabama in Huntsville

CPE/EE 47, CPE 57 VLSI Design I Delay Estimation Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) Review: CMOS Circuit

EEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW

Dynamic Combinational Circuits. Dynamic Logic

Dynamic Combinational Circuits Dynamic circuits Charge sharing, charge redistribution Domino logic np-cmos (zipper CMOS) Krish Chakrabarty 1 Dynamic Logic Dynamic gates use a clocked pmos pullup Two modes:

ENEE 359a Digital VLSI Design

SLIDE 1 ENEE 359a Digital VLSI Design Prof. blj@eng.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay s CSE477 slides

5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1

5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design

THE INVERTER. Inverter

THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)

CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look

CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka )

Power Dissipation. Where Does Power Go in CMOS?

Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit

MOSFET and CMOS Gate. Copy Right by Wentai Liu

MOSFET and CMOS Gate CMOS Inverter DC Analysis - Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max

CMOS Inverter (static view)

Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN

EEE 421 VLSI Circuits

EEE 421 CMOS Properties Full rail-to-rail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady

CHAPTER 15 CMOS DIGITAL LOGIC CIRCUITS

CHAPTER 5 CMOS DIGITAL LOGIC CIRCUITS Chapter Outline 5. CMOS Logic Gate Circuits 5. Digital Logic Inverters 5.3 The CMOS Inverter 5.4 Dynamic Operation of the CMOS Inverter 5.5 Transistor Sizing 5.6 Power

CMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties.

CMOS Inverter: Steady State Response CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates R p V OL = V OH = V M = f(r n, R p ) epartment of Electrical and Computer Engineering University

EE141- Spring 2004 Digital Integrated Circuits

EE141- pring 2004 Digital Integrated ircuits Lecture 19 Dynamic Logic - Adders (that is wrap-up) 1 Administrative tuff Hw 6 due on Th No lab this week Midterm 2 next week Project 2 to be launched week

Dynamic Combinational Circuits. Dynamic Logic

Dynamic Combinational Circuits Dynamic circuits Charge sharing, charge redistribution Domino logic np-cmos (zipper CMOS) Krish Chakrabarty 1 Dynamic Logic Dynamic gates use a clocked pmos pullup Two modes:

2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering

007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits Deog-Kyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we

ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter

ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.

Digital Integrated Circuits A Design Perspective

Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures

The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V

ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002

CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)

ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]

EE115C Digital Electronic Circuits Homework #4

EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors

Homework #2 10/6/2016. C int = C g, where 1 t p = t p0 (1 + C ext / C g ) = t p0 (1 + f/ ) f = C ext /C g is the effective fanout

0/6/06 Homework # Lecture 8, 9: Sizing and Layout of omplex MOS Gates Reading: hapter 4, sections 4.3-4.5 October 3 & 5, 06 hapter, section.5.5 Prof. R. Iris ahar Weste & Harris vailable on course webpage

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Restore Output. Pass Transistor Logic. How compare.

ESE 570: igital Integrated ircuits and VLSI undamentals Lec 16: March 19, 2019 Euler Paths and Energy asics & Optimization Lecture Outline! Pass Transistor Logic! Logic omparison! Transmission Gates! Euler

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 18: March 27, 2018 Dynamic Logic, Charge Injection Lecture Outline! Sequential MOS Logic " D-Latch " Timing Constraints! Dynamic Logic " Domino

Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Designing Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL

Digital Microelectronic Circuits ( ) Ratioed Logic. Lecture 8: Presented by: Mr. Adam Teman

Digital Microelectronic ircuits (361-1-3021 ) Presented by: Mr. Adam Teman Lecture 8: atioed Logic 1 Motivation In the previous lecture, we learned about Standard MOS Digital Logic design. MOS is unquestionably

Lecture 6: Circuit design part 1

Lecture 6: Circuit design part 6. Combinational circuit design 6. Sequential circuit design 6.3 Circuit simulation 6.4. Hardware description language Combinational Circuit Design. Combinational circuit

ECE 342 Solid State Devices & Circuits 4. CMOS

ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model

- Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next

Digital Integrated Circuits 2nd Inverter

Digital Integrated Circuits The Inverter The CMOS Inverter V DD Analysis Inverter complex gate Cost V in V out complexity & Area Integrity and robustness C L Static behavior Performance Dynamic response

Where are we? Data Path Design

Where are we? Subsystem Design Registers and Register Files dders and LUs Simple ripple carry addition Transistor schematics Faster addition Logic generation How it fits into the datapath Data Path Design

Integrated Circuits & Systems

Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 14 The CMOS Inverter: dynamic behavior (sizing, inverter

EE213, Spr 2017 HW#3 Due: May 17 th, in class. Figure 1

RULES: Please try to work on your own. Discussion is permissible, but identical submissions are unacceptable! Please show all intermediate steps: a correct solution without an explanation will get zero

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance

CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis

Lecture 14: Circuit Families

Introduction to CMOS VLSI Design Lecture 4: Circuit Families David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Pseudo-nMOS Logic q Dynamic Logic q

Semiconductor Memories

Semiconductor References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey UCB Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian

Where are we? Data Path Design. Bit Slice Design. Bit Slice Design. Bit Slice Plan

Where are we? Data Path Design Subsystem Design Registers and Register Files dders and LUs Simple ripple carry addition Transistor schematics Faster addition Logic generation How it fits into the datapath

Digital Integrated Circuits A Design Perspective. Semiconductor. Memories. Memories

Digital Integrated Circuits A Design Perspective Semiconductor Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies Semiconductor Memory Classification

Spiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp

2-7.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 2-7.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance

MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences

MSSCHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences nalysis and Design of Digital Integrated Circuits (6.374) - Fall 2003 Quiz #1 Prof. nantha Chandrakasan Student

Topics to be Covered. capacitance inductance transmission lines

Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of

MODULE 5 Chapter 7. Clocked Storage Elements

MODULE 5 Chapter 7 Clocked Storage Elements 3/9/2015 1 Outline Background Clocked Storage Elements Timing, terminology, classification Static CSEs Latches Registers Dynamic CSEs Latches Registers 3/9/2015

EE 330 Lecture 39. Digital Circuits. Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates)

EE 330 Lecture 39 Digital ircuits Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates) Review from last lecture Other MOS Logic Families Enhancement Load NMOS Enhancement

Lecture 4: CMOS review & Dynamic Logic

Lecture 4: CMOS review & Dynamic Logic Reading: ch5, ch6 Overview CMOS basics Power and energy in CMOS Dynamic logic 1 CMOS Properties Full rail-to-rail swing high noise margins Logic levels not dependent

Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor

L2: Combinational Logic Design (Construction and Boolean Algebra)

L2: Combinational Logic Design (Construction and oolean lgebra) cknowledgements: Lecture material adapted from Chapter 2 of R. Katz, G. orriello, Contemporary Logic Design (second edition), Pearson Education,

Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003

6.12 - Microelectronic Devices and Circuits - Spring 23 Lecture 14-1 Lecture 14 - Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:

VLSI Design I; A. Milenkovic 1

Why Power Matters PE/EE 47, PE 57 VLSI Design I L5: Power and Designing for Low Power Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka

EE 330 Lecture 37. Digital Circuits. Other Logic Families. Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates)

EE 330 Lecture 37 Digital Circuits Other Logic Families Static Power Dissipation Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates) Review from Last Time Inverter

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: 1st Order RC Delay Models. Review: Two-Input NOR Gate (NOR2)

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 14: March 1, 2016 Combination Logic: Ratioed and Pass Logic Lecture Outline! CMOS Gates Review " CMOS Worst Case Analysis! Ratioed Logic Gates!

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: March 29, 2018 Memory Overview, Memory Core Cells Today! Charge Leakage/Charge Sharing " Domino Logic Design Considerations! Logic Comparisons!

Integrated Circuits & Systems

Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br

EE5311- Digital IC Design

EE5311- Digital IC Design Module 3 - The Inverter Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai September 3, 2018 Janakiraman, IITM

The CMOS Inverter: A First Glance

The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power

CMOS Digital Integrated Circuits Lec 13 Semiconductor Memories

Lec 13 Semiconductor Memories 1 Semiconductor Memory Types Semiconductor Memories Read/Write (R/W) Memory or Random Access Memory (RAM) Read-Only Memory (ROM) Dynamic RAM (DRAM) Static RAM (SRAM) 1. Mask

CMOS Comparators. Kyungpook National University. Integrated Systems Lab, Kyungpook National University. Comparators

IsLab Analog Integrated ircuit Design OMP-21 MOS omparators כ Kyungpook National University IsLab Analog Integrated ircuit Design OMP-1 omparators A comparator is used to detect whether a signal is greater

Lecture 5: DC & Transient Response

Lecture 5: DC & Transient Response Outline Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 2 Pass Transistors We have assumed source is grounded

Hw 6 due Thursday, Nov 3, 5pm No lab this week

EE141 Fall 2005 Lecture 18 dders nnouncements Hw 6 due Thursday, Nov 3, 5pm No lab this week Midterm 2 Review: Tue Nov 8, North Gate Hall, Room 105, 6:30-8:30pm Exam: Thu Nov 10, Morgan, Room 101, 6:30-8:00pm

! Charge Leakage/Charge Sharing. " Domino Logic Design Considerations. ! Logic Comparisons. ! Memory. " Classification. " ROM Memories.

ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 9, 8 Memory Overview, Memory Core Cells Today! Charge Leakage/ " Domino Logic Design Considerations! Logic Comparisons! Memory " Classification

Dynamic operation 20

Dynamic operation 20 A simple model for the propagation delay Symmetric inverter (rise and fall delays are identical) otal capacitance is linear t p Minimum length devices R W C L t = 0.69R C = p W L 0.69

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets

Midterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!