ESE 570: Digital Integrated Circuits and VLSI Fundamentals

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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 17: March 26, 2019 Energy Optimization & Design Space Exploration Penn ESE 570 Spring 2019 Khanna

2 Lecture Outline! Energy Optimization! Design Space Exploration " Example Penn ESE 570 Spring 2019 Khanna 3

3 Energy and Power Basics Review Penn ESE 570 Spring 2019 Khanna

4 Total Power! P tot P static + P dyn + P sc Penn ESE 570 Spring 2019 Khanna 5

5 Static Leakage Power Penn ESE 570 Spring 2019 Khanna 6

6 Operating Modes! Steady-State: V in =V dd " PMOS: subthreshold " NMOS: resistive $ I DSp = I S #& W % L ' ) e ( $ & % V GS V T nkt / q ' $ $ V DS ) & ( 1 e % & % ' ) kt / q ( ' ) 1 λv DS ( ( ) I DSn = µ n C OX! # " W L $ ( & ( V GS V T )V DS V 2 DS * %) 2 + -, Penn ESE 570 Spring 2019 Khanna 7

7 Static Power Ratioed Logic! I static?! Input low-output high? " I leak! Input high-output low? " I pmos_on " ~V dd /R p,on Penn ESE 570 Spring Khanna 8

8 Total Static Power! P statit p(v out =low)v 2 /R p,on +p(v out =high)vi s (W/L)e-Vt/(nkT/q) p(v out =low) probability the output is low p(v out =high) probability the output is high p(v out =high)=1-p(v out =low) Penn ESE 570 Spring Khanna 9

9 Switching Dynamic Power Penn ESE 570 Spring 2019 Khanna 10

10 Switching Currents! I switch (t) = I sc (t) + I dyn (t) I sw I dyn I sc Penn ESE 570 Spring Khanna 11

11 Switching Energy! Do we know what this is? Q = I dyn (t)dt! What is Q? I dyn E = P(t)dt Q = CV = I(t)dt = I(t)V dd dt = V dd I(t)dt E = CV dd 2 Capacitor charging energy Penn ESE 570 Spring 2019 Khanna 12

12 Switching Power! Every time output switches 0#1 pay: " E = CV 2! P dyn = (# 0#1 trans) CV 2 / time! # 0#1 trans = ½ # of transitions! P dyn = (# trans) ½CV 2 / time Penn ESE 570 Spring 2019 Khanna 13

13 Switching Short Circuit Power Penn ESE 570 Spring 2019 Khanna 14

14 Short Circuit Power! Between V TN and V dd - V TP " Both N and P devices conducting Penn ESE 570 Spring Khanna 15

15 Peak Current! I peak around V dd /2 " If V TN = V TP and sized equal rise/fall % I DS ν sat C OX W V GS V T V ( DSAT ' * & 2 ) I(t)dt I t % ' 1( peak sc & 2 * ) # E = V dd I peak t sc % 1& ( $ 2' Vin Vdd-Vthp Vthn Vdd Isc Vdd time Penn ESE 570 Spring 2019 Khanna Vout tsc tsc time 16

16 Short Circuit Energy! Make it look like a capacitance, C SC " Q=I t " Q=CV " " E = V dd I peak t sc 1 %% $ $ '' # # 2 && E = V dd Q SC E = V dd (C SC V dd ) = C SC V 2 dd Penn ESE 570 Spring Khanna 17

17 Short Circuit Energy! Every time switch " Also dissipate short-circuit energy: E = CV 2 " Different C = C sc " C cs fake capacitance (for accounting) Penn ESE 570 Spring Khanna 18

18 Short Circuit Energy! When transistors switch, both nmos and pmos networks may be nano-tarily ON at once! Leads to a blip of short circuit current! < 10% of dynamic power if rise/fall times are comparable for input and output! We will generally ignore this component in hand analysis, but simulated measured results include it Penn ESE 570 Spring Khanna 19

19 Switching Waveforms Penn ESE 570 Spring Khanna 20

20 Switching Power! Every time output switches 0#1 pay: " E = CV 2! P dyn = (# 0#1 trans) CV 2 / time! # 0#1 trans = ½ # of transitions! P dyn = (# trans) ½CV 2 / time Penn ESE 570 Spring 2019 Khanna 21

21 Charging Power! P dyn = (# trans) ½CV 2 / time! Often like to think about switching frequency! Useful to consider per clock cycle " Frequency f = 1/clock-period! P dyn = (#trans/clock) ½CV 2 f Penn ESE 570 Spring 2019 Khanna 22

22 Charging Power! P dyn = (# 0#1 trans) CV 2 / time! Often like to think about switching frequency! Useful to consider per clock cycle " Frequency f = 1/clock-period! P dyn = (# 0#1 trans/clock) CV 2 f Penn ESE 570 Spring 2019 Khanna 23

23 Switching Power! P dyn = (#0#1 trans/clock) CV 2 f! Let a = activity factor a = average #tran 0#1 /clock! P dyn = acv 2 f Penn ESE 570 Spring Khanna 24

24 Activity Factor! Let a = activity factor " a = average #tran 0#1 /clock a = p(out i = 0) p(out i+1 =1) a = N N N 2 = N 0 (2N N 0 ) N 2 2N Penn ESE 570 Spring Khanna 25

25 Activity Factor! Let a = activity factor " a = average #tran 0#1 /clock a = p(out i = 0)p(out i+1 =1) a = N 0 N 1 2 N 2 = N (2 N 0 N 0 ) N 2 2 N Penn ESE 570 Spring Khanna 26

26 Reduce Dynamic Power?! P dyn = acv 2 f! How do we reduce dynamic power? Penn ESE 570 Spring Khanna 27

27 Reduce Activity Factor Tree Chain A B O 1 A B O 1 C D O 2 F C D O 2 F a = p(out i = 0)p(out i+1 =1) a = N 0 N 1 2 N 2 = N (2 N 0 N 0 ) N 2 2 N Penn ESE 570 Spring Khanna 28

28 Reduce Activity Factor Tree Chain A B 3/16 O 1 A B O 1 C D O 2 3/16 F a = p(out i = 0)p(out i+1 =1) C D O 2 F a = N 0 N 1 2 N 2 = N (2 N 0 N 0 ) N 2 2 N Penn ESE 570 Spring Khanna 29

29 Reduce Activity Factor Tree Chain A B 3/16 O 1 15/256 A B O 1 C D O 2 3/16 F a = p(out i = 0)p(out i+1 =1) C D O 2 F a = N 0 N 1 2 N 2 = N (2 N 0 N 0 ) N 2 2 N Penn ESE 570 Spring Khanna 30

30 Reduce Activity Factor Tree Chain A B C D O 1 O 2 F A B C 3/16 O 1 D 7/64 O 2 15/256 F a = p(out i = 0)p(out i+1 =1) a = N 0 N 1 2 N 2 = N (2 N 0 N 0 ) N 2 2 N Penn ESE 570 Spring Khanna 31

31 Reduce Activity Factor Tree Chain A B C D 3/16 O 1 O 2 3/16 15/256 F A B C 3/16 O 1 a = p(out i = 0)p(out i+1 =1) D 7/64 O 2 15/256 F a = N 0 N 1 2 N 2 = N (2 N 0 N 0 ) N 2 2 N Penn ESE 570 Spring Khanna 32

32 Total Power Summary! P tot = P static + P sc + P dyn! P sw = P dyn + P sc a(c load V 2 f)! P tot a(c load V 2 f) + VI s (W/L)e-Vt/(nkT/q)! Let a = activity factor a = average #tran 0#1 /clock Penn ESE 570 Spring 2019 Khanna 33

33 Energy and Power Optimization Penn ESE 570 Spring 2019 Khanna

34 Power Sources Review: P tot = P static + P dyn + P sc Penn ESE 570 Spring 2019 Khanna

35 Worksheet Problem 1 V in I static I dynamic I sc 0V 140mV 400mV 500mV 600mV 860mV 1V Penn ESE 570 Spring 2019 Khanna 36

36 Worksheet Problem 1 V in I static I dynamic I sc 0V 180pA 126uA 140mV 6nA 100uA 400mV 36uA 18uA 500mV 36uA 600mV 36uA 18uA 860mV 6nA 100uA 1V 180pA 126uA Penn ESE 570 Spring 2019 Khanna 37

37 Reduce V dd (Worksheet #2)! V dd =520mV, V thn = V thp =300mV V in I static I dynamic I sc 0V 140mV 260mV 360mV 500mV Penn ESE 570 Spring 2019 Khanna 38

38 Reduce V dd (Worksheet #2)! V dd =520mV, V thn = V thp =300mV V in I static I dynamic I sc 0V 180pA 39.6uA 140mV 6nA 14.4uA 260mV 111nA 360mV 6nA 10.8uA 500mV 180pA 36uA Penn ESE 570 Spring 2019 Khanna 39

39 Design Tradeoffs Penn ESE 570 Spring 2019 Khanna

40 Reduce V dd! What happens as reduce V dd? " Energy? " Static " Switching " Delay? Penn ESE 570 Spring 2019 Khanna 41

41 Reduce V dd :! τ gd =Q/I=(CV)/I Penn ESE 570 Spring 2019 Khanna 42

42 Reduce V dd :! τ gd =Q/I=(CV)/I! I d =(µc OX /2)(W/L)(V gs -V TH ) 2! τ gd impact?! τ gd 1 V Penn ESE 570 Spring 2019 Khanna 43

43 Reduce V dd :! τ gd =Q/I=(CV)/I! I d =(µc OX /2)(W/L)(V gs -V TH ) 2! τ gd impact?! τ gd 1 V! Ignoring leakage: E V 2 Eτ 2 Const Penn ESE 570 Spring 2019 Khanna 44

44 Reduce V dd (Worksheet #3)! V thn = V thp =300mV, V in =V dd, estimate Eτ V dd I ds dd =1) E switch / (E dd =1) Eτ 2 1V 700mV 500mV 350mV 260mV Penn ESE 570 Spring 2019 Khanna 45

45 Reduce V dd (Worksheet #3)! V thn = V thp =300mV, V in =V dd, estimate Eτ V dd I ds dd =1) E switch / (E dd =1) Eτ 2 1V 126uA mV 72uA mV 36uA mV 9uA mV 111nA k Penn ESE 570 Spring 2019 Khanna 46

46 Increase V th (Worksheet #4)! What is impact of increasing threshold on " Delay? " Leakage?! V dd =1V, V in =V dd V thn = -V thp I ds th =300mV) I static (I th =300mV) I stat / 300mV 460mV 600mV Penn ESE 570 Spring 2019 Khanna 47

47 Increase V th (Worksheet #4)! What is impact of increasing threshold on " Delay? " Leakage?! V dd =1V, V in =V dd V thn = -V thp I ds th =300mV) I static (I th =300mV) I stat / 300mV 126uA 1 180pA 1 460mV 97uA pA mV 72uA fA Penn ESE 570 Spring 2019 Khanna 48

48 Idea! Tradeoff " Speed " Switching energy " Leakage energy! Energy-Delay tradeoff: Eτ 2 Penn ESE 570 Spring 2019 Khanna 49

49 Design Space Exploration Penn ESE 370 Fall Khanna 50

50 Design Problem! Function: Identify equivalence of two 32bit inputs! Optimize: Minimize total energy! Assumptions: Match case uncommon " Ie. Most of the time, the inputs won t be matched! Deliberately focus on Energy to complement project " but will still talk about delay Penn ESE 370 Fall Khanna 51

51 Idea: Design Space Explore! Identify options " All the knobs you can turn! Explore space systematically! Formulate continuum where possible " i.e. formulate trends and tradeoffs quantitatively Penn ESE 370 Fall Khanna 52

52 Problem Solvable! Is it feasible? " First, make sure we have a solution so we know our main goal is optimization! How do we decompose the problem? Penn ESE 370 Fall Khanna 53

53 Problem Solvable! Is it feasible? " First, make sure we have a solution so we know our main goal is optimization! How do we decompose the problem?! What look like built out of nand2 gates and inverters? Penn ESE 370 Fall Khanna 54

54 Single Gate Match Condition! Design a single gate for match comparison Penn ESE 370 Fall Khanna 55

55 Total Power! Static CMOS: " P tot a(c load +2C sc )V 2 f+vi s (W/L)e-Vt/(nkT/q)! Ratioed Logic: " P tot a(c load +2C sc )V 2 f +p(v out =low)v 2 /R pon +(1-p(V out =low))vi s (W/L)e-Vt/(nkT/q)! What can we do to reduce power? Penn ESE 370 Fall Khanna 56

56 Knobs! What are the options and knobs we can turn? Penn ESE 370 Fall Khanna 57

57 Design Space Dimensions! Topology " (A) Gate choice, logical optimization " (B) Fanin, fanout, (C) Serial vs. parallel! Gate style / logic family " (D) CMOS, Ratioed (N load, P load)! (E) Transistor Sizing! (F) Vdd! (G) Vth Penn ESE 370 Fall Khanna 58

58 Gate! (A) What gates might we build? Penn ESE 370 Fall Khanna 59

59 Gate! (B) High fanin? Penn ESE 370 Fall Khanna 60

60 Gate! (C) Serial-Parallel? Penn ESE 370 Fall Khanna 61

61 (D) Logic Family! Considerations for each logic family? Penn ESE 370 Fall Khanna 62

62 (D) Logic Family! Considerations for each logic family? " CMOS " Ratioed with PMOS load " Ratioed with NMOS load! Ratioed Logic " Reduced C loads result in lower switching power (P dyn $) " Increased static power Penn ESE 370 Fall Khanna 63

63 (E) Sizing! How do we want to size gates? Penn ESE 370 Fall Khanna 64

64 (E) Sizing! How do we want to size gates? " Sizing transistors up will reduce delay # " Reduces short circuit power # # E = V dd I peak t sc % 1& & % (( $ $ 2' ' " Increases dynamic power Penn ESE 370 Fall Khanna 65

65 (F) Reduce Vdd! What happens as reduce V? " Energy? " Dynamic $ " Static $ " Switching Delay? % & τ gd =Q/I=(CV)/I & I d =(µc OX /2)(W/L)(V gs -V TH ) 2 & τ gd impact? & τ gd α 1/V & Limit on Vdd? Penn ESE 370 Fall Khanna 66

66 (G) Increase V th?! What is impact of increasing threshold on " Dynamic Energy? $ " Leakage Energy? $ " Delay? % & τ gd =Q/I=(CV)/I & I ds =(ν sat C OX )(W)(V gs -V TH -V DSAT /2) Penn ESE 370 Fall Khanna 67

67 Ideas! Three components of power " P tot = P static + P dyn + P sc! We know many things we can do to our circuits! Design space is large! Systematically identify dimensions! Identify continuum (trends) tuning when possible! Watch tradeoffs " don t over-tune Penn ESE 570 Spring 2019 Khanna 68

68 Admin! HW 7 due 4/5 Penn ESE 570 Spring 2019 Khanna 69

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