Very Large Scale Integration (VLSI)

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1 Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Dr. Ahmed H. Madian-VLSI

2 Contents Delay estimation Simple RC model Penfield-Rubenstein Model Logical effort Delay minimization techniques Transistor sizing Wiring sizing Distributed drivers Large driver Wiring techniques Dr. Ahmed H. Madian-VLSI

3 Circuit characterization & performance Resistance estimation Capacitance estimation Inductance estimation Delay estimation Simple RC model Penfield-Rubenstein Model Delay minimization techniques Transistor sizing Distributed drivers Driving large loads Wiring techniques Dr. Ahmed H. Madian-VLSI 3

4 Delay Estimation How to estimate the delay for your layout? - use a simulator - Solve the differential equation to get the exact delay 3- model your circuit using one of the defined delay models like RC Dr. Ahmed H. Madian-VLSI 4

5 Signal Delay Time Signal delay time is composed as follows Gate delay time Interconnection delay time due to minimization the delay times decreases the output impedance of buffers increases, thus the importance of interconnection delays increases So, signal delay time becomes less dependent on gate delay but more dependent on interconnection delay time Dr. Ahmed H. Madian-VLSI 5

6 Elmore Delay ON transistors look like resistors Pull-up or pull-down network modeled as RC ladder Elmore delay of RC ladder t R C pd itosource i nodes i R C R R C R R R C R R R 3 R N N N C C C 3 C N 4: DC and Transient Response 6

7 Routing Delay estimation (cont.) W W Elmore Delay: R total = n R U R u R u R u R u R u R u R u C u C u C u C u C u C u C u C total = n C U total = n R U C U Dr. Ahmed H. Madian-VLSI 7

8 Delay Estimation For MOSFET transistor, transit Velocity = µ. L velocity Where µ = mobility and = electric filed = V DS /L transit For lower delay, L V L DS L V DD V DD may be increased but we have limit of break down S N+ N+ L may be decreased but there s a problem with technology and Resistance Dr. Ahmed H. Madian-VLSI 8 G L D

9 Delay estimation (cont.) Equivalent circuit used for MOSFET Ideal Switch + Capacitance and ON Resistance Unit NMOS has resistance R, Capacitance C Unit PMOS has resistance R, Capacitance C Capacitance proportional to width Resistance is inversely proportional to width Define a model for delay based on the unit delay Treat every MOSFET as resistance. Lump intermediate node capacitance with load capacitance. u = R S * C Gate of min size transistor V in R G Cg Dr. Ahmed H. Madian-VLSI 9

10 Simple RC model Assume all pull up /pull-down resistors are summed as R pu /R pd and all capacitance are summed in the output capacitance V DD V DD R P =.5R n V in u = R n C g R P R P inv = R P C g R n R n V in inv = 5 R n C g C g C g inv = R n C g Inverter pair delay = inv + inv = 7 R n C g Dr. Ahmed H. Madian-VLSI 0

11 Elmore Delay Model V DD Calculate the delays in generalized RC trees. For a group of transistors in series (as in NAND gate), t R d Where R i is the summed resistance from point i to power or ground and C i is the capacitance at point i. Ex.: for 4 input NAND gate the fall time will be, i i C i a b c d R R xc R R R xc R R R R tdf ( RN xccd ) N N bc N N N3 ab N N N3 N 4 Dr. Ahmed H. Madian-VLSI a b c d C ab C bc C cd xc C out out out

12 Delay Components Delay has two parts Parasitic delay 6 or 7 RC Independent of load Effort delay 4h RC Proportional to load capacitance Dr. Ahmed H. Madian-VLSI

13 Logical Effort Chip designers face a bewildering array of choices What is the best circuit topology for a function? How many stages of logic give least delay? How wide should the transistors be? Logical effort is a method to make these decisions Uses a simple model of delay Allows back-of-the-envelope calculations Helps make rapid comparisons between alternatives Emphasizes remarkable symmetries Dr. Ahmed H. Madian-VLSI 3

14 Normalized Delay: d Delay Plots d = f + p = gh + p input NAND Inverter g = p = d = h + g = 4/3 p = d = (4/3)h + Effort Delay: f 0 Parasitic Delay: p Electrical Effort: h = C out / C in Dr. Ahmed H. Madian-VLSI 4

15 Computing Logical Effort DEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current. Measure from delay vs. fanout plots Or estimate by counting transistor widths A Y A B Y A B 4 4 Y C in = 3 g = 3/3 C in = 4 g = 4/3 C in = 5 g = 5/3 Dr. Ahmed H. Madian-VLSI 5

16 Example: Ring Oscillator Estimate the frequency of an N-stage ring oscillator Logical Effort: g = Electrical Effort: h = Parasitic Delay: p = Stage Delay: d = Frequency: f osc = Dr. Ahmed H. Madian-VLSI 6

17 Example: Ring Oscillator Estimate the frequency of an N-stage ring oscillator Logical Effort: g = Electrical Effort: h = Parasitic Delay: p = Stage Delay: d = 3 stage ring oscillator in 0.6 m process has frequency of ~ 00 MHz Frequency: f osc = /(*N*d) = /4N Dr. Ahmed H. Madian-VLSI 7

18 Example: FO4 Inverter Estimate the delay of a fanout-of-4 (FO4) inverter d Logical Effort: g = Electrical Effort: h = Parasitic Delay: p = Stage Delay: d = Dr. Ahmed H. Madian-VLSI 8

19 Example: FO4 Inverter Estimate the delay of a fanout-of-4 (FO4) inverter d Logical Effort: g = Electrical Effort: h = 4 Parasitic Delay: p = Stage Delay: d = 5 The FO4 delay is about 00 ps in 0.6 m process 60 ps in a 80 nm process f/3 ns in an f m process Dr. Ahmed H. Madian-VLSI 9

20 Multistage Logic Networks Logical effort generalizes to multistage networks Path Logical Effort Path Electrical Effort Path Effort G g i H C C out-path in-path F f g h i i i 0 g = h = x/0 x g = 5/3 h = y/x y g 3 = 4/3 h 3 = z/y z g 4 = h 4 = 0/z 0 Dr. Ahmed H. Madian-VLSI 0

21 Multistage Logic Networks Logical effort generalizes to multistage networks Path Logical Effort Path Electrical Effort Path Effort Can we write F = GH? G g i H C out path C in path F f g h i i i Dr. Ahmed H. Madian-VLSI

22 Paths that Branch No! Consider paths that branch: G = H = GH = h = h = F = GH? Dr. Ahmed H. Madian-VLSI

23 Paths that Branch No! Consider paths that branch: G = H = 90 / 5 = 8 GH = 8 h = (5 +5) / 5 = 6 h = 90 / 5 = 6 F = g g h h = 36 = GH Dr. Ahmed H. Madian-VLSI 3

24 Designing Fast Circuits i F D d D P Delay is smallest when each stage bears same effort fˆ g h F i i Thus minimum delay of N stage path is N D NF P This is a key result of logical effort Find fastest possible delay Doesn t require calculating gate sizes N Dr. Ahmed H. Madian-VLSI 4

25 Gate Sizes How wide should the gates be for least delay? fˆ gh g C in i C C out in gc i fˆ Working backward, apply capacitance transformation to find input capacitance of each gate given load it drives. Check work by verifying input cap spec is met. out i Dr. Ahmed H. Madian-VLSI 5

26 Example: 3-stage path Select gate sizes x and y for least delay from A to B x x y 45 A 8 x y B 45 Dr. Ahmed H. Madian-VLSI 6

27 Example: 3-stage path x Logical Effort G = Electrical Effort H = Branching Effort B = Path Effort F = Best Stage Effort ˆf Parasitic Delay P = Delay D = A 8 x x y y 45 B 45 Dr. Ahmed H. Madian-VLSI 7

28 Example: 3-stage path Logical Effort G = (4/3)*(5/3)*(5/3) = 00/7 Electrical Effort H = 45/8 Branching Effort B = 3 * = 6 Path Effort F = GBH = 5 Best Stage Effort ˆ 3 F 5 x x A 8 x Parasitic Delay P = = 7 Delay D = 3*5 + 7 = = 4.4 FO4 f y y 45 B 45 Dr. Ahmed H. Madian-VLSI 8

29 Example: 3-stage path Work backward for sizes y = x = x x y 45 A 8 x y B 45 Dr. Ahmed H. Madian-VLSI 9

30 Example: 3-stage path Work backward for sizes y = 45 * (5/3) / 5 = 5 x = (5*) * (5/3) / 5 = 0 45 A P: 4 N: 4 P: 4 N: 6 P: N: 3 B 45 Dr. Ahmed H. Madian-VLSI 30

31 Best Number of Stages How many stages should a path use? Minimizing number of stages is not always fastest Example: drive 64-bit datapath with unit inverter Initial Driver D = Datapath Load N: f: D: 3 4 Dr. Ahmed H. Madian-VLSI 3

32 Best Number of Stages How many stages should a path use? Minimizing number of stages is not always fastest Example: drive 64-bit datapath with unit inverter Initial Driver D = NF /N + P = N(64) /N + N Datapath Load N: f: D: Fastest Dr. Ahmed H. Madian-VLSI 3

33 Example: -input NAND Estimate worst-case rising and falling delay of -input NAND driving h identical gates. Y A B x h copies Dr. Ahmed H. Madian-VLSI 33

34 Example: -input NAND Estimate rising and falling propagation delays of a -input NAND driving h identical gates. A B x 6C C Y 4hC h copies Dr. Ahmed H. Madian-VLSI 34

35 Example: -input NAND Estimate rising and falling propagation delays of a -input NAND driving h identical gates. A B x 6C C Y 4hC h copies R Y (6+4h)C tpdr Dr. Ahmed H. Madian-VLSI 35

36 Example: -input NAND Estimate rising and falling propagation delays of a -input NAND driving h identical gates. A B x 6C C Y 4hC h copies R Y (6+4h)C t pdr 64h RC Dr. Ahmed H. Madian-VLSI 36

37 Example: -input NAND Estimate rising and falling propagation delays of a -input NAND driving h identical gates. A B x 6C C Y 4hC h copies Dr. Ahmed H. Madian-VLSI 37

38 Example: -input NAND Estimate rising and falling propagation delays of a -input NAND driving h identical gates. A B x 6C C Y 4hC h copies R/ x R/ C Y (6+4h)C tpdf Dr. Ahmed H. Madian-VLSI 38

39 Example: -input NAND Estimate rising and falling propagation delays of a -input NAND driving h identical gates. A B x 6C C Y 4hC h copies R/ x R/ C Y (6+4h)C pdf R R R h RC t C h C Dr. Ahmed H. Madian-VLSI 39

40 Delay Estimation (cont.) 3 input NAND gate with it s gate and diffusion capacitances (assuming all nodes are contacted). Estimation at schematic levels will be different if you look at the layouts. Dr. Ahmed H. Madian-VLSI 40

41 Layout models Good layout minimizes the diffusion area. 3 input NAND shown here, shares one diffusion contact, thus lowering the output capacitance by C. Contact diffusions are assumed. Dr. Ahmed H. Madian-VLSI 4

42 Body effect & delay If A goes from 0 to while B, C and D are, then all the intermediate nodes in the pulldown chain have already been discharged and the top MOSFET sees only a small body effect. If D goes from 0 to while A, B and C are, then the intermediate nodes are all one V t below V dd and the upper MOSFETs see a larger body effect. Dr. Ahmed H. Madian-VLSI 4

43 Circuit characterization & performance Delay estimation Simple RC model Penfield-Rubenstein Model Delay minimization techniques Transistor sizing Wiring sizing Distributed drivers Driving large loads Wiring techniques Dr. Ahmed H. Madian-VLSI 43

44 Delay minimization techniques V DD V DD Transistor sizing / a b c d out a C out V in V out b C ab Transistor sizing for minimum delay / c C bc Each Series transistors has C cd (W/L) = 3(W/L) basic inverter. each parallel transistors has (W/L) = (W/L) basic inverter Basic inverter d Dr. Ahmed H. Madian-VLSI 44

45 Wire sizing Wire length is determined by layout architecture, but we can choose wire width to minimize delay. width can vary with distance from driver to adjust the resistance which drives downstream capacitance. Dr. Ahmed H. Madian-VLSI 45

46 Optimal wire sizing Widening the wire reduces the resistance, but increases its capacitance. Wire with minimum delay has an exponential taper. Optimal tapering improves delay by about 8%. Can approximate optimal tapering with a few rectangular segments. Dr. Ahmed H. Madian-VLSI 46

47 Tapering of wiring trees Different branches of tree can be set to different lengths to optimize delay. Dr. Ahmed H. Madian-VLSI 47

48 Spanning tree A spanning tree has segments that go directly between sources and sinks. Dr. Ahmed H. Madian-VLSI 48

49 Distributed driver Decrease output load capacitance Undistributed : C load = 8C g Distributed: C load = 6C g Dr. Ahmed H. Madian-VLSI 49

50 Driving large loads If large loads have to be driven, the delay may increase drastically. Large loads are output capacitances, clock trees, etc. t d = t inv (C L /C G ) Where t inv =is the average delay of a minimum-sized inverter driving another minimum sized inverter, C L = load capacitance& C G = gate capacitance C L = 000C G, then t d = 000.t inv A possibility to reduce the delay, is to use a sequence of n scaled inverters, but not the optimum delay: C Load t d = t inv (40/)+ t inv (00/40) + t inv (000/00)= 50t inv Dr. Ahmed H. Madian-VLSI 50

51 Driving large loads (cont.) We may decrease the delay by using larger transistors to decrease the resistance. Scaling transistors by factor S results in: R W L sca led sca led R S S sca led W L normal t r =.R scaled (C in + C load ) But scaling the transistor also affects the input capacitance of the transistor: C in,scaled = S. C in Dr. Ahmed H. Madian-VLSI 5

52 Driving large loads (cont.) reference... C in 3 N- N (W/L) S(W/L) S (W/L) S N- (W/L) S N- (W/L) C Load The problem is if input signal is placed at inverter what s the number of stages N and the scaling factor S that will minimize the time needed for the signal to reach C load Dr. Ahmed H. Madian-VLSI 5

53 Dr. Ahmed H. Madian-VLSI 53 Driving large loads (cont.) t d = t +t +t 3 + +t N C Load... C in 3 N- N (W/L) S(W/L) S (W/L) S N- (W/L) S N- (W/L) reference C = SC C 3 =S C C C 4 =S 3 C C N =s N- C R R =R /S R 3 =R /S R N-=R /S N- R N=R /S N- ) ( SR C N t C S S R C S S R C S S R C S S R C S S R R SC t d N N N N d t d = R C + R C 3 + R 3 C 4 + +R N- C N +R N C load C load = S N C

54 Driving large loads (cont.) t t d C N d Load N( SR C S N C ln C ln S C ln C ln C S Load Load ) reference R R =R /S R 3 =R /S R N- =R /S N- R N=R /S N-... C in 3 N- N ( SR C (W/L) S(W/L) S (W/L) S N- (W/L) S N- (W/L) C C = SC 3 =S C C C 4 =S 3 C C N =s N- C ) C Load For minimum delay, dt d /ds = 0; this yields, S = e =.7 Dr. Ahmed H. Madian-VLSI 54

55 Example we want to drive a load capacitor of value C L = 0pF. The input stage is defined as C =0fF and has k =00µA/V. calculate the number of stages N to minimize the delay. solution N C Load ln 0x0 ln( ) C 5 0x0 ln(500) ln( S) ln( e) 6. We will select N = 6 to obtain non-inverting chain Dr. Ahmed H. Madian-VLSI 55

56 nd assignment Check the web site for Assignment 3. Due date next Saturday. Dr. Ahmed H. Madian-VLSI 56

57 Refs. David Harris, Logical effort lecture notes, Hurvey mid college, 004. CMOS VLSI Design, 4 th edition Introduction to VLSI, nd edition Dr. Ahmed H. Madian-VLSI 57

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