Interconnect (2) Buffering Techniques.Transmission Lines. Lecture Fall 2003


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1 Interconnect (2) Buffering Techniques.Transmission Lines Lecture Fall 2003
2 A few announcements Partners Lab Due Times Midterm 1 is nearly here Date: 10/14/02, time: 3:004:20PM, place: in class (DH2210) Material required: Lec1 Lec13 (including Lec13) Closed books, closed notes! (Calculators OK) Review session: Monday 10/13/02, 4:306:00PM in DH2210 (To Be Confirmed!) Final Exam scheduled for 12/16/02 (8:30a.m.11:30a.m.)
3 Overview Electrical wire models Lumped RC model Distributed rc line Designing gates for performance Progressive sizing Input reordering Driving large capacitances Buffering techniques Addressing Coupling Capacitance, Resistance and Inductance 3
4 Overview Designing gates for performance Progressive sizing Input reordering Driving large capacitances Buffering techniques Addressing Coupling Capacitance, Resistance and Inductance 4
5 Design for Performance Reduce C L keep the drain diffusion as small as possible interconnect capacitance fanout Increase W/L ratio of the transistor the most effective performance optimization tool for the designer Increase V DD can tradeoff energy for performance increasing V DD above a certain level yields only minimal improvement reliability concerns enforce a firm upper bound on V DD Slope engineering keeping signal rise and fall times smaller than or equal to the gate propagation delays and of approximately equal values good for performance good for power consumption Irwin&Vijay, PSU, CSE 477, 2002
6 NMOS/PMOS Ratio So far we have sized the PMOS and NMOS so that the R eq s match symmetrical VTC equal hightolow and lowtohigh propagation delays If speed is the main concern Use minimum channel length (smallest possible L for all FETs) Finding the width W that minimizes delay is more difficult Reduce the width of the PMOS device Widening the PMOS degrades the t phl due to larger parasitic capacitances Widening both PMOS and NMOS by a factor S reduces Req by an identical factor (R eq = R ref /S), but raises the intrinsic capacitance by the same factor (C int = SC iref )
7 Driving Large Capacitances inv1 R line inv2 C line V DD V DD p. 204 in book V in P1 V out P2 C i N1 C L N2 β opt = r(1 + C w /(c dn + cdn)) If C W ~ 0; ε = 2.5 => α sqrt(2.5) = 1.6
8 Fast Complex Gates  Design Technique 1 Transistor Sizing: As long as Fanout Capacitance dominates Progressive Sizing: M1 > M2 > M3 > MN Out V DD In N MN C L In 3 In 2 M3 M2 C 3 C 2 Distributed RCline In 1 M1 C 1 Can Reduce Delay with more than 25%! In 1 In 2
9 Long NChains: Progressive Sizing In N (1) MN Out C L output voltage V DD In 3 (1) M3 C 3 T 1 (0.38RC) In 2 (1) M2 C 2 T 2 (0.69RC) In 1 (1) M1 C 1 T d time
10 Progressive Sizing (cont d) Out Out In N (1) MN C L C eq C L R X C L In 3 (1) M3 C 3 R 3 C 3 In 2 (1) M2 C 2 R 2 C 2 In 1 (1) M1 C 1 R 1 C 1 T d = R 1 C 1 + (R 1 +R 2 )C (R 1 +R R X )C L
11 Fast Complex Gates: Design Technique 2 Input reordering when not all inputs arrive at the same time critical path critical path In 3 1 In 2 1 In charged 0 1 M3 C In 1 L M3 C charged L In 1 M2 C 2 2 charged M2 C2 discharged M1 charged In 3 1 M1 C discharged 1 C 1 delay determined by time to discharge C L, C 1 and C 2 delay determined by time to discharge C L
12 Overview Designing gates for performance Progressive sizing Input reordering Driving large capacitances Buffering techniques Addressing Coupling Capacitance, Resistance and Inductance 12
13 Reducing Wire Delay L L/2 L/2 rc L 2 /2 t inv + 2rc/2 (L/2) 2 As long as t inv is smaller than half the wire delay, the total delay may be reduced by inserting an inverter! 1mm 1mm r = 20Ω/µm c = pf/µm t1 = L 2 (delay of a 1mm section) tp = (1000) 2 + t inv (1000) 2 = 5.6ns + t inv (< 11.2 ns when inv is missing)
14 Single Inverter Buffer V DD V DD β V in C i 1 β u u V out C L = xc i Q: what value of u minimizes the propagation delay through (inv + buffer)? buffer u = x t p,opt = 2t p0 x
15 Buffer Sizing 1 α 1 Rb Rb/α R αcb C/2 C/2 Cb α opt = sqrt(1 + C/C b )
16 Using Cascaded Buffers If C L is given How should the inverters be sized? How many stages are needed to minimize the delay? In 1 u u 2 u N Out C i C 1 C 2 C L u opt = e t p,opt = e t p0 ln(c L /C i )
17 t p as function of u and x 60.0 u/ln(u) 40.0 x=10,000 x= x=100 x= u
18 Overview Electrical wire models Lumped RC model Distributed rc line Designing gates for performance Progressive sizing Input reordering Driving large capacitances Buffering techniques Addressing Coupling Capacitance, Resistance and Inductance 18
19 Coupling C x C = C x C x C = 0 C x C = 2C x Very Difficult to Analyze
20 Ground Planes and Shields Reduce Coupling Capacitance Metal3 GND Metal2 Metal1 GND Does not reduce capacitance Can increase it Moves it to known value
21 Wire Spacing Increased wire spacing Decreases Capacitance Increases Area Double the space = Half the coupling
22 Wire Widening Wire Widening Resistance decreases Cap increases, but not enough to compensate Fringe remains constant Assume L >> W R(C p + C f ) R/2(2C p + C f )
23 Wire Tapering Elmore delay: Low R is more important near source Design for minimal wire delay Step approximation:
24 Power Distribution Three issues: Ohmic (IR) drop Supply current to VDD and GND Gates do not see full voltage Electromigration Electrons move metal ions
25 Ohmic Drop V IR What if V IR > V T? Narrow noise margins
26 Ohmic Drop Voltage drop increases gate delay Solutions: Resistance is the enemy Decrease length to supply Increase width Use thicker metal layers (top layer) Capacitance is actually GOOD! Averages out peaks in current
27 Power Distribution Schemes V DD GND Logic Logic V DD V DD GND (a) Fingershaped network GND (b) Network with multiple supply pins
28 IR drop Analysis
29 Electromigration Electrons move metal ions Directional (DC current) Not so bad Ions move back and forth Usually creates open, eventually Bad To avoid: keep current density below limit
30 Picture Break
31 Inductance Sources: Bonding wires PCB strip lines Onchip lines with very fast rise/fall times Impact: Power distribution, IOs Transmission line behavior
32 Inductance: L di/dt Resistance to change of current Overshoot Ringing
33 L di/dt effects Overshoot 5 V out (V) RC RLC Time (ns)
34 Damping 5 Overdamped: (R/2L) 2 > 1/LC R 2 > 4L/C V out (V) RC RLC Underdamped: (R/2L) 2 < 1/LC R 2 < 4L/C V out (V) RC RLC Time (ns)
35 Underdamped Response: Ringing 5 V out (V) RC RLC What if this is low enough to turn on PMOS again? Time (ns)
36 L di/dt Solutions Reduce Package Lead Inductance 1 Power pin pair for each 510 output drivers Improved packaging Decoupling capacitors Local supply Low pass filter, remove high frequency noise
37 Packaging Options Wire Bonding Substrate Die Pad Lead Frame
38 Flipchip Bonding Die Solder bumps Interconnect layers Substrate
39 Transmission Lines ICs obey the laws of physics: Signals do take time to propagate Lossy: Lossless:
40 Lossless TLines v prop = 1/sqrt( l c ) = 1/sqrt( εµ) Vacuum : 30 cm/ns SiO 2 : 15 cm/ns PC board: 13 cm/ns
41 Reflections
42 More Reflections V V Dest V Source R S = 5Z 0 (a) V R S = Z 0 (b) V R S = Z 0 / t (in t lightf ) (c)
43 When to consider TL?
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