Homework Assignment #5 EE 477 Spring 2017 Professor Parker

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1 Homework Assignment #5 EE 477 Spring 2017 Professor Parker Question 1: (15%) Compute the worst-case rising and falling RC time constants at point B of the circuit below using the Elmore delay method. Assume all transistors are unit sized and wire capacitance is lumped. Assume Rchn = 2000 ohms. Cg(n+p) = 20 ff, Cd(n+p) = 20ff, and Cint = 10 ff. Rint for interconnect1 is 10 ohms, interconnect2 is 5 ohms, and interconnect3 is 7 ohms. Recall that channel resistance is inversely proportional to beta. So: R "#$ = β % R "#% β $ Since all transistors are unit sized, W/L is same. => R "#$ = = 8604 Ω 51 Note that interconnect capacitance is lumped at the beginning, so we don t need to consider it separately for the 3 wires. Following is the circuit for falling delay at B: Falling Elmore delay at B = = ns For rising delay at B, the circuit is the same except that Rchn is replaced with Rchp and the leftmost Gnd symbol is replaced with Vdd. Rising Elmore delay at B = = ns

2 Question 2: a) (15%) Is CBADEFGHIBACAGD an Euler path for the PMOS transistors shown in the circuit below. If so, mark it. If not, mark where it fails. No, it fails as shown. Note: If we start from the other C PMOS transistor, it fails immediately because there is no B connected to C. b) (5%) What information does an Euler path tell you about transistor placement when laying out a compound gate? Transistors should be laid out from left-to-right in the order of the Euler path. This allows maximum possible sharing of diffusion regions.

3 c) (10%) Circle all the diffusion capacitance locations that could contribute to fall time, even if some do not when the longest path is on for discharge. To get worst case discharging path, we must have B = 1, C = 1, A = 0, G = 0. The other inputs are flexible. For example, any 1 NMOS out of D, E, F should be on, any 1 NMOS out of H, I should be on, etc. So, all the diffusion capacitances could possibly contribute to fall time: Note: As an exercise, try to compute the input combinations for A to I which give the worst case fall time.

4 Question 3: (10%) Assume you have the following wires to place in a layout. The numbers give starting and ending x positions of the wires. Place them using the Left Edge algorithm. Two wires in the same track can start and end at the same point. So a wire can end at 4 and another can start at 4. 3,7 4,6 1,5 2,4 5,7 3,8 1,6 6,8 Track 1: 1,6 6,8 Track 2: 1,5 5,7 Track 3: 2,4 4,6 Track 4: 3,8 Track 5: 3,7 Question 4: (8%) Compute the gate capacitance for an NMOS transistor in linear and saturation region. The NMOS transistor dimensions are: W=9 lambda, L= 3 lambda. Assume L D =0.0 nm Since lambda = 100 nm, we get W = 900 nm, L = 300 nm. C? = ε ABWL t AB = GHI GJ GJ GH? = 1.63 ff Note: In this case, t ox is thickness of thin oxide because that is the material under the gate. Also, SI units have been used everywhere in the above equation, that s why the power of 10 in ε? is -12, not -14. In linear region, C NOPQ = C? = ff. In saturation, C NOPQ = 2 3 C? = ff. Question 5: (8%) Use the fringing field figure on p. 274 of the text. Assume w/l = 0.2, and w/h = 0.5. Estimate the fringing field factor if t/h = 1. As shown by the maroon lines in the figure below, fringing field factor is 10. Note: For meanings of the terms w, l, h, t, please refer to the textbook or watch the discussion on Apr 7 th.

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6 Question 6: (8%) Assume electrons in a wire on a CMOS chip move at v m/sec and the rise/fall time on the wire is 0.01ns. Assuming wire length is 1 cm, what electron velocity would require us to consider inductance? Inductance should be considered when: τ XYZQ, τ \O]] < 2.5l v 2.5l => v < τ XYZQ, τ \O]] => v < GJ => v < J m/s Note: Speed of light is 3 10 d m/s, so we should definitely consider inductance here! Question 7: (8%) Ernie Engineer decides to separate the first and second latches of a negative edge-triggered flip flop by a long wire so he can fit the flip flop into little spaces in a complicated layout. Now he finds he needs to increase his clock period. Explain what timing of the flip flop is affected by the long wire? t hold is the hold time, t setup is the setup time, t q is the clock-to-q time, t L2prop is the propagation delay in the feedback path of the second latch, and t comb is the propagation delay of the feedback combinational logic.

7 If a long wire is placed between the latches, t setup increases, and so clock period also increases. This is because clock period = t setup + t q + max(t comb,t L2prop ). The way to get a better feel for this is to look at the inverter in the first latch with output NOTQ. That inverter sees not only the inverter in the feedback path to the first mux, but sees the C int and R int. The Elmore delay to the input of the second latch includes C int and R int. So the delay to the feedback inverter in the first latch is increased, increasing setup time. Question 8: (8%) Compute the C dp for the source diffusion sidewall that faces the channel of a unit size PMOS transistor. Use diffusion capacitances given above: C jbsp = 18.8 x 10-4 pf/ μm 2 and C jbswp = 3.17 x 10-4 pf/ μm. The sidewall facing the channel has capacitance per unit area, so we need to compute area of the sidewall. Since width of diffusion is not explicitly specified, assume it s equal to the width of the channel, i.e. 0.4 μm. Depth of diffusion is given as x j. C e$ = C fgz$ W x f = Gi = ff Question 9: (5%) Calculate the resistance of a wire.03 cm long and 6 lambda wide that has resistance.4 ohms/square. Wire Length = 0.03 cm = 3000λ. Square size can be anything as long as the entire wire surface can be filled with an integral number of squares. Let s take square side = 6λ. Total resistance = = 200 Ω Note: If you instead took squares of side 3λ, there would be 1000 squares along the length and 2 along the width. So total resistance would still be = = = 200 Ω.