Problem Set 9 Solutions

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1 CSE 26 Digital Computers: Organization and Logical Design - 27 Jon Turner Problem Set 9 Solutions. For each of the sequential circuits shown below, draw in the missing parts of the timing diagrams. You may assume that the propagation delays of all components are zero. X clk Clk D >C Q S Y S X Y clk D >C Q S U S Clk D >C Q S V S U V - -

2 2. If a sequential circuit is operated using a clock that has a frequency of 5 MHz, what is the time between consecutive rising clock edges? The time between rising clock edges (that is, the clock period) is /(5 6 ) seconds which is.2 μs or equivalently, 2 ns. For a clock with a period of 3 ns, what is the clock frequency? /(3-9 ) Hz which is.33 GHz or equivalently, 33 MHz. 3. For each of the circuits shown below, fill in the timing diagrams to show when each of the inputs must be stable and when each the outputs could potentially be changing (your diagrams should be similar to the one on page 9.6 of the lecture notes). ssume that the flip flop setup time is 2 ns, the hold time is ns, the flip flop propagation delay is between ns and 2 ns and the propagation delay for each gate is between.5 ns and ns. X CLK Clk D >C Q S Y X + +2 Y D E Clk D Q >C D Q >C S S U CLK D V E U V Suppose output V of the second circuit is connected to input of the first circuit. Show that if the circuits are driven from the same 2 MHz clock that setup time violations can occur in the second circuit. How large does the clock period have to be in order to avoid setup time violations? What is the clock frequency corresponding to this period? With a 2 MHz clock, the clock period is 5 ns. The timing conditions imply that input must be stable 4 ns before a rising clock edge and that output V can be changing 4 ns after the previous clock - 2 -

3 edge. So if the clock period is 5 ns, output V can be changing during the period when input must be stable. If these two signals are connected, the setup conditions for the flip flop in the first circuit will be violated. To eliminate the setup violation, we must increase the clock period to 8 ns. This corresponds to a clock frequency of 25 MHz. 4. For each of the state diagrams shown below, construct the corresponding state tables. / / / inputs outputs XY state variables S S / / inputs/outputs /XY / / / / / / / / / state / variables S S S S XY D D S S XY D D - 3 -

4 5. For each of the state tables shown below, construct the corresponding state diagrams. S S XY D D S S XY D D / / / / / / / / / / / / / / / - 4 -

5 6. For each of the state diagrams shown below, complete the timing diagram at right. You may assume that all propagation delays are zero. inputs outputs XY / / C S S state variables S S / X Y / / / input/outputs /XY state variables S S / / / / / / / / / C S S X Y - 5 -

6 7. Given the timing diagram shown below, create a state transition diagram that includes all the transitions that are implied by the timing diagram. C S S / / / / / X Y 8. For each of the sequential circuits shown below, write the next state and output equations, then create a state transition table and a state transition diagram for the circuit. e sure to use the correct format for your transition diagrams (Mealy vs. Moore). Output equations: X = S + Y = + S Next state equation: D = + S S D XY / / / / / / / / - 6 -

7 Output equations: X = S + S Y = S Next state equation: D = S + S S + S D = + S + S + S S S S D D XY / / / - 7 -

8 Output equations: X = S + S Next state equation: D = + S S + S S + S S D = (S S ) + (S + ) S S D D X / / / / / / / / / / / / / / / / - 8 -

9 Output equations: X = S 2 + S S Y = S S Next state equation: D 2 = S 2 S S +S (S 2 + S ) D = S 2 S S +S S (S 2 + ) D = S 2 S S +S 2 (S + S (S + )) S 2 S S D 2 D D XY / / / / / - 9 -

10 9. For each of the state transition diagrams show below, create a transition table, then derive the next state and output equations. Finally, draw a sequential circuit that implements the state diagram. / / / / / / / / S D XY S D = S + + S S X= S + ( + S ) S Y= S + S ( + ) - -

11 / / / S S D D XY S S x x x x D =S + + S S S x x x x X =S Y =S D =S S + S + S + S - -

12 / / / / / / / / / / / / / S S / / / S S D =S + S D =S + S S + S + S S + S + S S S S X =S + S S + S S D D X - 2 -

13 . For each of the circuits in Problem 8, draw a timing diagram like the one on page 9.6 of the lecture notes showing the time periods during which the inputs must be stable. For each of the Moore model circuits, also show the time periods during which the outputs may be changing. ssume that the flip flop setup time is 2 ns, the hold time is ns, that gate delays for simple gates can range from.4 ns to.5 ns, that gates with 3 or 4 inputs have the same delay as two simple gates and that the flip flop propagation delay can range from ns to 4 ns. (a) There are 3 gate delays between a change in and a change at a flip flop input. So must be stable starting at ( ) = 6.5 ns before the clock changes and must stay stable until ( ) =.2 ns before the clock changes. Input is also delayed by 3 gate delays, hence has the same timing requirements. The timing diagram appears below CLK (b) There can be 4 or 5 gate delays between a change in and a change at a flip flop input. So must be stable starting at ( ) = 9.5 ns before the clock changes and must stay stable until ( ) =.6 ns before the clock changes. Input can also be delayed by either 4 or 5 gate delays, hence has the same timing requirements. Output X can be delayed by either or 2 gate delays, which means it can change from ( +.4) =.4 ns after the clock changes until ( ) = 7 ns after the clock changes. Output Y is delayed by gate delays, which means it can change from ns after the clock changes until 4 ns after the clock changes CLK X Y

14 (c) There can be 2 to 4 gate delays between a change in and a change at a flip flop input. So must be stable starting at ( ) = 8 ns before the clock changes and must stay stable until ( - 2.4) =.2 ns after the clock changes. Input can be delayed by either 4 or 5 gate delays, so must be stable starting at ( ) = 9.5 ns before the clock changes and must stay stable until ( ) =.6 ns before the clock changes CLK (d) There can be 3 to 5 gate delays between a change in and a change at a flip flop input. So must be stable starting at ( ) = 9.5 ns before the clock changes and must stay stable until ( ) =.2 ns before the clock changes. Output X can be delayed by either or 2 gate delays, which means it can change from ( +.4) =.4 ns after the clock changes until ( ) = 7 ns after the clock changes. Output Y can also be delayed by or 2 gate delays CLK X Y

15 . For each of the circuits in Problem 8, determine if the circuit is subject to internal hold time violations. If so, show how to modify the circuit to eliminate the hold time violations. If not, explain why not. ssume that the flip flop setup time is 2 ns, the hold time is ns, that gate delays for simple gates can range from.3 ns to.5 ns, that gates with 3 or 4 inputs have twice as much delay as simple gates, that the flip flop propagation delay can range from ns to 4 ns and that the clock skew is ns. (a) In the first sequential circuit there is a path from the flip flop output to the flip flop input with just two gate delays. Since < +, we would normally conclude that this does have an internal hold-time violation. However, since we are going from the output to the input of the same flip flop, we can omit the clock skew from the right side of the inequality, allowing us to conclude that there is no hold-time violation. (b) In this circuit, the shortest path from a flip flop output to a flip flop input contains 3 gate delays and since < +, we would normally conclude that it is subject to internal hold time violations. However, this shortest path goes from the output of the bottom flip flop back to its input, and so we need not include the clock skew on the right side of the inequality, allowing us to conclude that there is no hold-time violation. ll other feedback paths have at least 4 gate delays. (c) In this circuit, the shortest path from a flip flop output to a flip flop input contains 3 gate delays and since < +, we would normally conclude that it is subject to internal hold time violations. However, this shortest path goes from the output of the bottom flip flop back to its input, and so we need not include the clock skew on the right side of the inequality, allowing us to conclude that there is no hold-time violation. ll other feedback paths have at least 4 gate delays and since > +, these do not cause hold time violations. (d) In this circuit, the shortest path from a flip flop output to a flip flop input contains 3 gate delays. There are three such paths that cause hold time violations, one from the output of the bottom flip flop, to the input of the middle flip flop (through the 3 input ND gate), a second from the output of the middle flip flop to the input of the bottom flip flop (through the 4 input ND gate), and the third, from the output of the middle flip flop to the input of the top flip flop. Since < +, all three of these paths cause hold time violations. They can all be corrected by adding inverter pairs at the inputs to the ND gates on the feedback paths. There is another path with 3 gate delays from the output of the middle flip flop to its input (through the 4 input ND gate), but this one does not cause a hold time violation. ll other feedback paths have at least 4 gate delays and since > +, these do not cause hold time violations

16 2. For each of the circuits in Problem 8, determine the shortest clock period that can be used without causing any internal setup time violations. What maximum clock frequency does this correspond to? ssume that the flip flop setup time is 2 ns, the hold time is ns, that gate delays for simple gates can range from.4 ns to.5 ns, that gates with 3 or 4 inputs have twice as much delay as simple gates, that the flip flop propagation delay can range from ns to 4 ns and that the clock skew is ns. (a) Here the longest path from a flip flop output to a flip flop input has 2 gate delays, so the minimum period is = ns, corresponding to a clock frequency of MHz. In this case, we could actually neglect the ns for clock skew, since there is just one flip flop. This would give 9 ns or MHz. (b) The longest path from a flip flop output to a flip flop input has 5 gate delays, so the minimum period is = 4.5 ns, corresponding to a clock frequency of 69 MHz. (c) The longest path from a flip flop output to a flip flop input has 5 gate delays, so the minimum period is = 4.5 ns, corresponding to a clock frequency of 69 MHz. (d) The longest path from a flip flop output to a flip flop input has 6 gate delays, but this path is from the output of the bottom flip flop back to its input, so we can omit the clock skew term, giving a the minimum period is = 5 ns, corresponding to a clock frequency of 66.7 MHz. 3. In each of the block diagrams shown below, the blocks are Moore-model sequential circuits. The numeric intervals adjacent to the signal names specify the timing characteristics of each circuit. So for example, the interval [ 5,+.5] at input of the right hand block in the first diagram means that input must be stable starting 5 ns before a rising clock transition and continuing until.5 ns after the rising clock transition. Similarly, the interval [+.5,+8] at output X of the left hand block means that this output may be changing at any time during the interval from.5 ns after a rising clock transition to 8 ns after a rising clock transition. For each diagram, determine if there are situations that can cause timing violations no matter how large the clock period is (this may happen if an output of one block can start changing shortly after the clock changes, but the corresponding input on the other block requires that the output remains stable following the clock transition). If the circuit can have such a timing violation, explain how it can be eliminated. Then, for each circuit, determine the shortest clock period for which we can guarantee that the circuit operates correctly (after any needed modifications are made). What is the corresponding clock frequency? ssume that there is no clock skew between the different circuit components and that a single inverter has a minimum delay of.5 ns and a maximum delay of 2 ns. X [+.5,+8] Y [+.75,+5] [-5,+.5] [-8,-] Z [-2,+] C [+.5,+2] - 6 -

17 In this circuit, output C of the right hand block can change.5 ns after the clock transition, while the input Z of the left hand block requires that it be stable until ns after the clock changes. This problem can be corrected by adding a pair of inverters on the interconnecting signal to add some delay. Once this change is made, the timing specifications on signal X require a minimum period of 3 ns, the timing specifications on signal Y also require a minimum period of 3 ns and the timing specifications on signal C Z require a minimum period of 8 ns (accounting for the maximum of 4 ns of delay that was added). So the minimum clock period is 3 ns, which corresponds to a frequency of 77 MHz. W [+2,+] X [+.75,+5] [-5,+.5] [-8,-] Y [-6,+.4] Z [-5,+.6] C [+,+6] D [+3,+] In this circuit, there are no timing violations that occur for all clock periods, so we don t need to modify the circuit. Signal W requires a minimum period of 5 ns, X requires a minimum period of 3 ns, C Y requires a minimum period of 2 ns and D Z requires a minimum period of 5 ns. So, the minimum clock period is 5 ns, which corresponds to a frequency of 67 MHz. W [+.5,+8] X [-8,-] Y [-6,+.4] [-5,+.5] [+.75,+5] C [+,+6] F [+2,+8] G [-7,+.2] In this circuit, there are no timing violations that occur for all clock periods, so we don t need to modify the circuit. Signal W requires a minimum period of 3 ns, X requires a minimum period of 3 ns, C G requires a minimum period of 3 ns and F Y requires a minimum period of 4 ns. So, the minimum clock period is 4 ns, which corresponds to a frequency of 7 MHz

18 4. Repeat the previous problem, but this time, assume that there can be as much as ns of clock skew between different blocks. That is, assume that the clock can arrive up to ns earlier (or later) at one block relative to another. In the first circuit, the C Z signal is still the only one that causes a problem at all clock periods. ecause of the clock skew, we need additional delay on this signal. With two inverter pairs on this signal, we get a minimum of 2 ns of delay which enough to eliminate the timing violation. This adds up to 4 ns of delay to this signal which means that it requires a clock period of at least ns if there is no clock skew and 2 ns if there is ns of clock skew. The other two signals both require a clock period of at least 4 ns with the clock skew included, so the minimum clock period is 4 ns and the corresponding frequency is 7 MHz. In the second circuit, signal C Y can change ns after the clock changes and is required to be stable until.4 ns after the clock changes. If the clock arrives at the left-hand block ns later than at the right-hand block, we can get a timing violation. This can be corrected by adding an inverter pair to this signal. This is the only modification we need to make. With the inverter pair on C Y, the minimum clock period required for this signal is 7 ns, assuming ns of clock skew. This is the worst-case requirement, so the minimum clock period is 7 ns. The corresponding clock frequency is 59 MHz. In the third circuit, the signal C G can change ns after the clock changes and is required to be stable until.2 ns after the clock changes. If the clock arrives at the bottom block ns later than at the right-hand block, we can get a timing violation. This can be corrected by adding an inverter pair to this signal. This is the only modification we need to make. With the inverter pair on C G, the minimum clock period required for this signal is 8 ns, assuming ns of clock skew. This is the worst-case requirement, so the minimum clock period is 8 ns. The corresponding clock frequency is 56 MHz

19 5. Consider the simple SR latch on page 9.2 of the lecture notes. Suppose that at time, both inputs are high and then at time, both inputs go low. Draw a timing diagram that shows how the two outputs change, assuming that each of the gates has a propagation delay of exactly 4 time units. Draw a second timing diagram assuming that the top gate has a delay of 4 time units and the bottom gate has a delay of 5 time units. S R Q Q S R Q Q - 9 -

20 6. The diagram shown below shows a negative edge-triggered D flip flop and an SR masterslave flip flop with labels added to some intermediate signals. Complete the timing diagram shown below, assuming that every gate has a delay equal to half of one time unit. Explain how the behavior of the SR flip flop is similar to the behavior of the D flip flop and how it is different. D Q C S R C Q C D Q S R Q 2 The behavior of the two flip flops is similar in the sense that the outputs of both flip flops change when the clock goes from high to low. They are different in that the SR flip flop responds to changes that occur while the clock is high, while the D flip flop responds only to the value of the input at the time the clock drops. For example, when the clock drops at time 6, we see that the output of the SR flip flop changes, even though both of the inputs are low when the clock drops. This happens because during the period the clock is high, the S input went high, causing the master latch to become set. This new value then appears at the output when the clock drops. On the other hand, we see that even though the D input is high at time 2 (causing signal to also be high), the value of the flip flop output is not affected by this

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