EE371 - Advanced VLSI Circuit Design
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1 EE371 - Advanced VLSI Circuit Design Midterm Examination May 1999 Name: No. Points Score TOTAL / 90 In recognition of and in the spirit of the Stanford University Honor Code, I certify that I will neither give nor receive unpermitted aid on this examination. Signature: Although your answers are important, your REASONS for giving those answers are even more important. Please, please, please, explain what you are doing and why. This will make it a whole lot easier for me to judge your mastery of the material. 1
2 INSTRUCTIONS 90 minutes, closed book. One 8.5x11 double-sided page of handwritten notes allowed. The TAs will be around if you need them. 1. Wire Design (20 pts) Assume that you have are working in a 0.35µ process (λ = 0.2µ). You find the following entries in a cap table for this technology: Ctotal Cgnd Cadj air / m2 / sub inf x n/a air / m2 / sub inf x n/a air / m2 / sub inf x n/a air / m2 / sub inf x n/a air / m2 / sub inf x n/a air / m2 / sub inf x n/a air / m2 / sub inf x n/a air / m2 / sub inf x n/a air / m2 / sub x air / m2 / sub x air / m2 / sub x air / m2 / sub x air / m2 / sub x air / m2 / sub x air / m2 / sub x air / m2 / sub x air / m2 / sub x air / m2 / sub x air / m2 / sub x air / m2 / sub x air / m2 / sub x air / m2 / sub x The resistance of the wire is 0.04 Ω/sq. The numbers in the table are good to about 10%. There is no need for high-precision answers, so if you can find the data you need, estimate it from the data you have. The first set of questions will look at adding repeaters to minimize the delay of a 4λ wire with 4λ spacing in bus configuration a) (4pt) The effective capacitance per micron of the wire is data dependent. What is the min and max effective capacitance of a wire? What is the max/min capacitance ratio? 2
3 b) (6pt) As part a) showed, for a wire in a bus, the effective cap per unit length is data dependent. If you are trying to optimize the delay of the wire, which capacitance value (min, typ, max or something else) do you use when solving for the optimal repeater spacing? Explain your answer. c) (6pt) Assume that you designed the repeaters to drive the maximum capacitance (Note: this might not be the correct answer to part b). For some data patterns the actual capacitance on the wire will be much smaller than the designed value. What is the ratio of delay for this case compared to max delay of the wire. d) (4pts) Does placing inverters driving a capacitor to cancel the noise coupling improve delay performance? Explain 3
4 2. Transistors (24 pts) a) (6pts) Shown below is a simple design of a differential pair in CMOS. To improve the matching of M1, M2 would you first try to increase W or L? Which would you increase for M3, M4? Please explain your answers M3 M4 M1 M2 b) (6pts) You want to create binary sized currents (1x 2x 4x). There are three approaches shown below. All transistors are W wide unless marked, and all gate terminals are connected to the same bias voltage. Please indicate which circuit will give the best matching, and which will give the worst. Also indicate if two circuits will have similar performance. Give you reasons for your ranking. 4W 2W W 4
5 c)(6pts) A 0.35µ chip(vth = 0.5V) has a number of current sources which use a common bias generator. Through probing the chip, we notice that one current is 40% less than the other. Other probing results indicate that the current source bias line is at 0.8V. What size of Gnd drop would be needed to cause this error? Use a quadratic model of a transistor. Why is that the right 1st order model to use? d)(6pts) If you look at the formula for a MOS differential pair, it would seem like you could make the current gain (gm=io/(vgs-vth)) go to infinity, as the width of the input transistors goes to infinity (since the gate overdrive, Vgs-Vth, goes to zero). But this is not true. For very wide devices the gain of the differential pair staturates. Why? 5
6 3. Circuits and Simulation Corners (26pts) a)(6pts) In the homework, we created a NOR gate by shorting two inverters together. We can use the same topology to create a NAND gate simply by resizing the transistors. If the pmos current is 1/2 the nmos current per unit width, how would you size the transistors to form a NAND gate? (try to keep the rising and falling delays the same) Out In b)(4pts) If you were trying to check the margins of the circuit in part a) what input combination(s) and processing corner(s) would you simulate. c)(4pts)often you need to calculate power dissipation of a chip because you are worried about how hot the chip will get. For generating this data, what simulation corner should you use? Explain. 6
7 d)(6pts)the dynamic gate shown below seems marginal in some simulation runs because of a charge sharing problem. Please explain what is causing the problem and show what input combination (sequence) can trigger it. How would you set up a simulation to measure it? What corner(s) would you use to simulate this circuit? A C small B 2w w/4 All transistor are w wide unless marked e)(6pts) Show a dual rail dynamic gate that produces a mux (ab+ac)? 7
8 4. Logical Effort (20pts) a) (6pts) In domino gates, sometimes the inverter following a dynamic gate is replaced by a NAND or NOR gate. Shown below is the same function implemented as either a single complex gate plus an inverter, or two dynamic gates and a NAND gate. 2w 2w F1 F2 w/2 F1 F2 w/2 w/2 Is the logical effort different?is the second gate ever faster than the first? Why? b) (6pts) Size this circuit so the logical effort for the SelA input and the A input are as close as possible. Please give the sizes for the transistors in the inverters as well as the labeled transistors. SelA SelA M1 A M2 Out B M3 M4 8
9 c)(8pts) Shown below is the schematic for a tristate buffer. The input capacitance of the buffer must be 40fF, and the buffer must drive a 0.6pF load. Ignoring diffusion capacitance, please size the transistors to optimize the delay of this circuit. Assume that the gate cap is 1.8fF/µm. Please how you are going to find the sizes, before you solve for them so we can give partial credit. If you don t explain your method, you will not get full credit. M2 M1 9
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