EE115C Digital Electronic Circuits Homework #5

Transcription

1 EE115C Digital Electronic Circuits Homework #5 Due Thursday, May 13, E EIV Problem 1 Elmore Delay Analysis Calculate the Elmore delay from node A to node B using the values for the resistors and capacitors given in the table below. Verify your answers with simulation using SPECTRE. Resistor Value (Ohms) Capacitor Value (ff) R C1 60 R C2 180 R C3 60 R4 25 C4 60 R C5 250 R C6 60 R C7 120 R8 250 C8 60 Shared resistance between selected node and resistance between A and B R AC AB R 1 = 0.06 R AD AB R 1 = 0.06 R AE AB R 1 + R 3 = 0.18 R AF AB R 1 = 0.06 R AG AB R 1 + R 3 = 0.18 R AH AB R 1 +R 3 +R 6 = 0.43 R AI AB R 1 +R 3 = 0.18 R AB R 1 +R 3 +R 6 +R 8 =

2 For each node, we find common resistance between the node and path from node A to node B, as shown in the table above. Using Eq. (4.13) from the textbook, we obtain τ= ps. The propagation delay is given by: t p = 0.69 τ = ps For Spectre simulation, we first construct the schematics as in the following figure: A Transient Analysis is ran with a pulse input source having the pulse-width of ~50ps. The simulation result is shown below: The propagation delay from Simulation is ps (very close to ps )

3 Problem 2 Wire Length and its Capacitance Electrical Engineering Department Spring 2010 A standard CMOS inverter drives an aluminum metal-1 wire. Assume R n =1KΩ, R p =1.5KΩ. Also, assume that the output capacitance of the unloaded gate is negligible compared to the wire we are driving. The wire is 0.2μm wide with the resistivity of 0.05 Ω/. Use the lumped RC model in your analysis. a) What is the "critical length" of the wire? (Hint: see Chapter 4, page 158) (Note: Eq uses the distributed RC model) R s = (1kΩ + 1.5kΩ)/2 = 1.25 kω t p_gate = k (C wire ) t p_wire = 0.69 R wire (C wire ) (lumped RC model) In order to make t p_gate = t p_wire R wire = 1.25k Also R wire = 0.05 L critical / 0.2μm L critical = R wire / R W wire = 1.25k / μm L critical = 5 mm b) What is the equivalent capacitance of a wire of this length? For the wire capacitance calculation, assume C pp = 20aF/μm 2, C fringe = 30aF/μm. C pp = 0.02fF/μm 2 (0.2 μm) (5000 μm) = 20 ff C fringe = F/μm 5000 μm = 300 ff C wire = C pp + C fringe = 320 ff Problem 3 Propagation Delay & Gate Sizing Consider the circuit in Fig. 3. At the output of the first stage, fanout is b 1 = 2 identically sized (x) inverters. At the output of the third stage, fanout is b 2 = 4 identically sized (z) inverters. Hint: Since there are so many inverters, you may use the hierarchical design methods. (Tutorial 2) b 1 =2 b 2 =4 V in 1 x y z V out 256 Fig. 3 a) Determine scaling factors x, y, z to minimize the delay. Path branching effort is the product of per-stage branching factors

4 B = =8 Electrical Engineering Department Spring 2010 The ratio of the external load of input capacitance is F = 256 / 1 = 256 The overall logical effort is G = = 1 To minimize the delay, all stages should have the same effort f. Stage Effort = f = = 4 * x f = 6.73 =, x = 6.73 / 2 = y f = 6.73 =, y = = x 4z f = 6.73 =, z = /4 = y x =3.36, y = 22.65, z =38.11 b) Calculate the delay assuming t p0 =7ps and C int = C gate (γ = 1). Verify your results in SPECTRE and comment on the differences. In SPECTRE validation, assume unit-sized inverter with following transistor parameters: W p = 480nm, W n = 240nm, L n = L p = 100nm. Hint: Since there are so many inverters, you may use the hierarchical design methods. (Tutorial 2) Hand calculation: t p = t p0 4 ( ) = 7ps = ps Simulation: The delay is simulated using the schematic below (extra capacitances, representing load to the load, may be used to suppress Miller kick-back). t p = (t plh + t phl )/2 = ( )/2 = ps

5

6 Comparison: Hand calculation 216.4ps, Simulation 219.2ps (1) The difference between the two values is about 2%, which is quite close. (2) t p0 can be calibrated more precisely (γ 1). (3) We assume the inverters with W p = 2W n to have the same pull-up and pull-down capability, which is not quite true. It may contribute a few percent. Problem 4 Logic and Logical Effort a) A three-input XNORT gate (see insert above) works like a two-input NOR as long as input A is high; otherwise, the output is stuck high. Implement the XNORT gate in complementary CMOS, and size all transistors such that the worst-case delay is equal to that of a minimum sized 2/1 inverter. Find the logical effort associated with each input. 1.5fF 54fF Fig 4: XNORT path. The complementary CMOS implementation is to the left. Logical effort is defined as the ratio of input capacitance of a gate (considering only one input) to the input capacitance of an inverter with the same output current. This gives us: g A = (2+2)/(2+1) = 4/3 g B = (4+2)/(2+1) = 2 g C = (4+2)/(2+1) = 2

7 b) Assuming all input combinations are equally likely, what is the transition activity (probability) of a XNORT gate? Averaged over many cycles, will a XNORT gate typically consume more or less power than a two-input NOR gate, if they both drive equally large output loads? What about a two-input XOR? The transition probability of the gate is P(F:0 1) = P(F=0)P(F=1) = 3/8 5/8 = 15/64 = 0.23 The transition probability of a two-input NOR (again with all inputs assumed equally likely) is 3/ , lower than the XNORT. With the simplifying assumption that the output load is large (which lets us forget about differences in intrinsic capacitance), we can confidently assert that the XNORT will on average consume more dynamic power. The transition probability of a two-input XOR is 0.25, which is slightly more than the XNORT. Therefore, we would expect the XNORT to consume less power, on average. P(F:0 1) = 0.23 c) For the logic path from node (1) to node (2) shown in the Fig. 4, find the path branching effort, path electrical effort, path logical effort, and total path effort. What is the optimum effort per stage for minimizing delay? The path branching effort (product of stage branching efforts, which are the ratios of total driven capacitance to capacitance driven on the path) is: B path = = 6 The path electrical effort (ratio of output capacitance to input capacitance) is: H path = C L /C in = 54fF/1.5fF = 36 The path logical effort (product of stage logical efforts), using results from both the lectures and earlier in this problem, is: G path = g inv g xnort,a g nand g xnort,b g nor = 1 4/3 4/3 2 5/3 = 160/27 The total path effort is then F= G path B path H path = 160/ = 1280 The optimum effort per stage for this five-stage path is f* = F 1/5 = 4.18

8 d) Find the input capacitances {w, x, y, z} necessary for each of the gates in the path in order to achieve the optimum effort per stage. The effort for the stage is f = b g h C in = g C out b / f Input capacitance of the NOR gate (last gate in the path) is: z = b g nor C L / f = 1 (5/3) 54fF / 4.18 = 21.5fF The stage effort for the second XNORT is: f = 2 g xnort,b 21.5fF / y y = b 21.5fF g xnort,b / f = fF 2 / 4.18 = 20.6fF. Fanout of the NAND gate is: h = 20.6fF / x x = b 20.6fF g nand / f = fF (4/3) / 4.18 = 6.6fF Fanout (electrical effort) for the first XNORT is: h = 6.6fF / w w = ff g xnort,a / f = 3 6.6fF (4/3) / 4.18 = 6.3fF As a check, we see that the first stage effort is f = b g inv h = fF / 1.5fF = 4.2, which closely matches our calculated optimum effort per stage. z = 21.5 ff, y = 20.6 ff, x = 6.6 ff, w = 6.3 ff