EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS. Kenneth R. Laker, University of Pennsylvania

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1 1 EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS

2 2 -> ESD PROTECTION CIRCUITS (INPUT PADS) -> ON-CHIP CLOCK GENERATION & DISTRIBUTION -> OUTPUT PADS -> ON-CHIP NOISE DUE TO PARASITIC INDUCTANCE -> SUPER BUFFER CIRCUIT DESIGN -> LATCH-UP PHENOMENON

3 ESD PROTECTION 3 HUMAN BODY MODEL 1 MΩ 1.5 kω MACHINE MODEL 1 MΩ V esd pf DUT V esd pf DUT ESD TESTERS: LUMPED ELEMENT MODEL C C L S C S I Component HBM MM R DUT + C C (pf) S C t V R S (Ω) L S (µη) C S (pf) 1 0 C t (pf) 10 10

4 input pin V A PROTECTION NETWORK (PN) to circuits on die V < V A < V

5 INPUT SERIES TRANSMISSION GATE CIRCUIT 5 X A TG X A PN E E A -> EXTERNAL (OFF-CHIP) input signal E -> INTERNAL (ON-CHIP) enable signal X -> INTERNAL (ON-CHIP) output signal X = A, when E = 0 X = HIGH-IMPEDANCE STATE when E = 1 NOTE: ANY UNUSED INPUT TERMINALS SHOULD BE TIED TO OR GND USING PULL-UP OR PULL-DOWN RESISTORS RATHER THAN FLOAT

6 INVERTING INPUT CIRCUIT 6 A X A PN X X = A LEVEL SHIFTING FROM TTL TO CMOS V out = X V in = A V OH = V OH = 2.0 V NM H V IH V out = V in V OL = 0.8 V TTL V th V NM IL L CMOS V OL = 0 DESIGN FOR V th = 1.4 V 0.8 V IL V IH 2.0 V th V in = A

7 VARIATIONS IN LEVEL SHIFT VTC DUE TO PRCESS VARIATIONS 7 V out = X V OH = PM-NM PL-NH PH-NL V OL = V IL V IH 2.0 V th V in = A PM-NM => nominal processing PH-NL => strong pmos, weak nmos process corner PL-NH => weak pmos, strong nmos process corner

8 8 NON-INVERTING TTL LEVEL-SHIFTING CIRCUIT A TTL X X X = A A PN Schmitt Trigger

9 OUTPUT CIRCUITS AND L(di/dt) NOISE 9 TRISTABLE OUTPUT CIRCUIT CK D 12 transistors Large W/L D Z CK Z CK Z = D for CK = 1 Z = HIGH IMP for CK = 0 D LARGE W/L -> Sufficent current sink, source -> Reduce delay times CK 6 transistors Large W/L Z

10 LARGE W/L -> Sufficent current sink, source -> Reduce delay times V OH => LARGE di/dt L (di/dt) VOLTAGE DROP ACROSS BONDING WIRE CONNECTING PAD TO PACKAGE PIN t I s max 2 C load V in, V out I max i C (t) 10 I max 2 C load t s V OL t i T/2 T C nmos nmos t 0 t ON ON s /2 t s t pmos di ON I max dt max t s / 2 = 2I max t s 4C load ( t s ) 2

11 11 di 4C load dt max ( ) 2 t s LET C load = 100 pf, L = 2 nh, = 5 V and t s = 5 ns ( 12) 5 di 4 100x10 dt max 5x10 9 di L 160mV dt max HIGH-END MICROPROCESSOR CHIPS WITH 32 BITS OR 64 BIT DATA BUS LINES - ALL OTPUT DRIVERS SWITCHING AT THE SAME TIME! ( ) ( ) 2 =80 ma ns

12 12 REDUCE L(di/dt) NOISE D CK Z PRECHARGES INVERTER OUTPUT Z TO /2 WHEN ST = 1 AND CK = 0 (JUST PRIOR TO CK -> 1) ST

13 BIDRECTIONAL BUFFER CIRCUIT WITH TTL INPUT CAPABILITY 13 D Reduce di/dt Noise E E Z D TS E Z PN DI TTL DI Level Shift

14 ON-CHIP CLOCK GENERATION AND DISTRIBUTION 14 SIMPLE ON-CHIP CLOCK CIRCUIT RING OSCILLATOR CK CK CK FREQUENCY -> PROCESS DEPENDENT -> UNSTABLE R bias PIERCE CRYSTAL OSCILLATOR CIRCUIT C 1 C Crystal 2 -> GOOD FREQUENCY STABILITY

15 TWO-PHASE CLOCKING SCHEMES 15 T c phi 1 phi 2 clk phi 1 phi 2 PRIMARY CLOCKS FROM XTAL CONTROLLED OSCILLATOR CLOCK DECODER CK1 CK2 CK3 CK4

16 GENERAL LAYOUT OF H-TREE CLOCK DISTRIBUTION NETWORK FOR UNIFORM CLOCK DISTRIBUTION 16 CLOCK GEN C AD Techniques to automate the generation of optimum clock distribution networks.

17 SUPER BUFFER 17 C LOAD PROBLEM: GIVEN the task of driving a large capacitive load C LOAD, how can a SUPER BUFFER comprised of chain of N inverters be scaled to minimize the buffer s delay time? Equiv INV a 1 1 a 2 a 3 C g C C d ac g ac d a 2 C g a 2 C d a 3 C g a 3 C LOAD d N = 3 N -> number of inverter stages a -> optimal stage scale factor let C LOAD = a 4 C g In General: C LOAD = a N+1 C g

18 18 Equiv INV a 1 1 a 2 a 3 C g C C d ac g ac d a 2 C g a 2 C d a 3 C g a 3 C LOAD d t d t d t d t d N -> number of inverter stages a -> optimal stage scale factor N = 3 let C LOAD = a4 C g In General: C LOAD = a N+1 C g CONSIDER N stages and C LOAD = a N+1 C g ALL INVERTERS HAVE SAME DELAY t d = τ 0 C d + ac g C d + C g τ 0 is per gate delay for Equiv INV in ring oscillator circuit with load capacitance = C g + C d. C d + ac g t total = ( N+1)τ 0 C d + C g where C LOAD = a N+1 C g => Choose N and a to MINIMIZE t total ( ) N+1= ln C LOAD /C g ln( a)

19 C d + ac g t total = ( N+1)τ 0 C d + C g ( ) N+1= ln C LOAD /C g ln( a) TO MINIMIZE t total : => ( ) t total = ln C LOAD /C g ln( a) τ 0 C d + ac g C d + C g 19 dt total da = τ 0 ln C LOAD C g 1/a ln( a) C d + ac g ( ) 2 C d + C g + 1 C g ln( a) C d + C g = 0 = 0 a opt ln a opt ( ) 1 [ ] = C d C g For the SPECIAL CASE C d = 0 => ln (a opt ) = 1 or a opt = e 1 = 2.718

20 20 EXAMPLE: For C d = 0.5 ff, C g = 10 ff, determine a opt and N for C LOAD = 50 pf. a opt [ln(a opt ) - 1] = 0.5 => a opt = 3.18 ( ) N+1= ln C LOAD /C g ln( a) N = [ln(c LOAD /C g )/ln(a)] - 1 = [ln(50 x /1 x )/ln(3.18)] - 1 = [ln(5000)/ln(3.18)] - 1 = 6.36 The SUPER BUFFER DESIGN which MINIMIZES t total for C LOAD = 50 pf is N = 7 Equiv INV stages a opt = 3.18

21 chip clk PLL CLOCKING SCHEMES clk pad buffer chip PLL clk clk pad 21 R output C clk-out register output pad clk d clk = d clk-buf + d RC +d out-reg + d pad d clk clk-out data out clk Phase Detector WHY USE PLL IN SYSTEM CLOCKS? Filter n VCO clk dclk clk-out data out + To syncronize the internal clock of a chip to an external clock. R C clk-out output pad d clk = d out-reg + d pad output - clk + To operate an internal clock at a higher rate than the external clock input.

22 chip PLL clk clk pad 22 4 C R Generates an internal fclk-out = 4 fclk synchronized to clk clk clk-out output pad sychronizes the out-put enables of two chips bus (high speed - tristate) chip1 d clk = d out-reg + d pad chip2 system clk clock PLL PLL clock

23 LATCHUP IN CMOS CIRCUITS V in 23 latch-up susceptability α 1/[NSUB (spacing) 2 ] p + V out n + n + p + p + n + I Rwell R well V B-pnp Q2 (NPN) I E2 I + I E1 Q1 (PNP) V B-npn R sub I Rsub I V R sub p-sub 2.0 ma NPN PNP I H R well R well n-well I slope = 1/R T trigger point V 0 V H = 1.5 V R T I H V H SCR EQIV CKT in Latch-up

24 I Rwell R well V B-pnp Q2 (NPN) I E2 I I E1 Q1 (PNP) V B-npn R sub I Rsub I + V 2.0 ma I H I slope = 1/R T trigger point V 0 V H = 1.5 V R T I H V H SCR EQIV CKT in Latch-up 24 At the on-set of latch-up I > I H = ( - V H )/R T LATCH-UP CONDITION

25 LATCH-UP PREVENTION make large 25 make small Reduce α npn, α pnp ; Reduce R sub, R well Latchup Prevention LAYOUT Guidelines: A. Latchup resistant CMOS processes (thin epi layer on highly doped substrate). B. Layout n and p channel transistors such that all nmos transistors are placed close to GND and. Physically separate n and p transistors (i.e. with the bonding pad). C. Use p + guard rings connected to GND around nmos transistors and n + quard rings connected to around the pmos transistors to reduce R well and R sub and to weaken BJTs. D. Place sub, well contacts close to the nmos, pmos source connections to supply rails (i.e. GND for nmos, for pmos). CONSERVATIVE RULE: One sub contact per source connection to a supply LESS CONSERVATIVE: One sub contact per 5-10 devices.

26 I/O CELL LAYOUT USING LATCH-UP GUIDELINES 26 p-tub edge spaced far from p + sources to n + nmos OUT BOND PAD GND p + pmos p + guard ring to GND n + guard ring to

Topics to be Covered. capacitance inductance transmission lines

Topics to be Covered. capacitance inductance transmission lines Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of