GMU, ECE 680 Physical VLSI Design
|
|
- Justina Clarke
- 6 years ago
- Views:
Transcription
1 ECE680: Physical VLSI esign Chapter IV esigning Sequential Logic Circuits (Chapter 7) 1
2 Sequential Logic Inputs Current State COMBINATIONAL LOGIC Registers Outputs Next state 2 storage mechanisms positive feedback charge based 2
3 In our text: Naming Conventions a latch is level sensitive a register is edge triggered gg There are many different naming conventions For instance, many books call edge triggered elements flip flops This leads to confusion however 3
4 Latch versus Register Latch stores data when clock is low Register stores data when clock rises Clk Clk Clk Clk 4
5 Latches Positive Latch Negative Latch In G Out In Out G clk In Out clk In Out Out stable Out follows In Out stable Out follows In 5
6 Latch Based esign N latch is transparent Pl latch his transparent when = 0 when = 1 N Latch Logic P Latch Logic 6
7 Flip Flops Flops vs Latches 7
8 Timing efinitions t su t hold t Register ATA STABLE t t c 2 q ATA STABLE t 8
9 Characterizing Timing t 2 Clk Clk Register t C 2 t C 2 Latch 9
10 Maximum Clock Frequency FF s LOGIC t p,comb t clk- + t p,comb + t setup = T Also: t cdreg + t cdlogic > t hold t cd : contamination delay = minimum delay 10
11 Positive Feedback: Bi Stability V i1 V o1 =V i2 V o2 V o1 V i2 V o2 =V i1 V i1 V o2 A V i2 =V o1 C B V i1 =V o2 11
12 Meta Stability V i1 V o1 =V i2 V o2 o1 V i2 5V o A V o2 =V i1 o1 V i2 5V o A C C B B d V i1 5 V o2 V d i1 5 V o2 Gain should be larger than 1 in the transition region 12
13 Writing into a Static Latch Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states Converting into a MUX (positive) Forcing the state (can implement as NMOS-only) 13
14 Mux Based Latches Negative latch (transparent when = 0) Positive latch (transparent when = 1) Clk Clk In Clk Clk In 14
15 Mux Based Latch 15
16 Mux Based Latch M M NMOS only Non-overlapping clocks 16
17 Master Slave (Edge Triggered) Register Master Slave M 1 M Two opposite latches trigger on edge Also called master-slave latch pair 17
18 Master Slave Register Multiplexer-based l latch pair I 2 T 2 I 3 I 5 T 4 I 6 M I 1 T 1 I 4 T 3 18
19 Clk elay 2.5 Volts t c 2 q(lh) t c 2 q(hl) time, nsec 19
20 Setup Time M 2.0 I 2 2 T 2 Volts I 2 2 T 2 Volts M time (nsec) time (nsec) (a) T setup nsec (b) T setup nsec 20
21 Reduced Clock Load Master Slave Register T 1 I 1 T 2 I 3 I 2 I 4 better power dissipation but need to overpowering the feedback I2 21
22 Avoiding Clock Overlap X A B (a) Schematic diagram (b) Overlapping clock pairs 22
23 Overpowering the Feedback Loop NOR-based set-reset Cross Coupled Pairs S S S R 0 0 R R Forbidden State 23
24 Cross Coupled NAN Cross-coupled NANs Added clock V S M 2 M 4 M R 6 M 8 M 1 M 3 S M 5 M 7 R This is not used in datapaths any more, but is a basic building memory cell 24
25 Sizing Issues S W = 0.5 m (V Volts) W/L 5 and Vo olts 1 0 W = 1 m W = 0.6 m W = 0.7 m W = 0.8 m W = 0.9 m time (ns) (a) (b) Output voltage dependence on transistor t width Transient response 25
26 Storage Mechanisms Static ynamic (charge-based) 26
27 Making a ynamic Latch Pseudo Static 27
28 More Precise Setup Time Clk t t (a) t 1.05t C 2 t C 2 t Su t 2 C t H (b) 28
29 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay Inv1 CP T Clk- ata Clock T Setup-1 Time T Setup-1 t=0 Time 29
30 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay Inv1 CP T Clk- ata Clock T Setup-1 Time T Setup-1 t=0 Time 30
31 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay Inv1 CP T Clk- ata Clock T Setup-1 Time T Setup-1 t=0 Time 31
32 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay Inv1 T Clk- CP ata Clock T Setup-1 Time T Setup-1 t=0 Time 32
33 Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 M Clk- elay T Clk- Inv1 CP ata Clock T Setup-1 Time T Setup-1 t=0 Time 33
34 Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk- elay Inv1 CP 0 T Clk- Clock ata T Hold-1 Time T Hold-1 t=0 Time 34
35 Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk- elay Inv1 CP 0 T Clk- Clock ata T Hold-1 Time T Hold-1 t=0 Time 35
36 Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk- elay Inv1 CP 0 T Clk- T Hold-1 Time Clock ata T Hold-1 t=0 Time 36
37 Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M Clk- elay Inv1 T Clk- CP 0 Clock ata T Hold-1 T Hold-1 Time t=0 Time 37
38 Setup/Hold Time Illustrations Hold-1 case CN TG1 1 S M Inv2 M T Clk- Clk- elay Inv1 CP 0 Clock ata T Hold-1 T Hold-1 Time t=0 Time 38
39 Other Latches/Registers: C 2 MOS V V M 2 M 6 M 4 M 8 X C M L1 3 M 7 C L2 M 1 M 5 Master Stage Slave Stage Clock CMOS Keepers can be added d to make circuit it pseudo-static ti 39
40 Insensitive to Clock Overlap V V V V M 2 M 6 M 2 M 6 0 M 4 0 X M 8 X 1 M 3 1 M 7 M 1 M 5 M 1 M 5 (a) (0 0) overlap (b) (1 1) overlap 40
41 Pipelining a RE EG a RE EG log REG Out REG REG log REG Out b RE EG b RE EG Rf Reference Pipelined 41
42 Other Latches/Registers: TSPC V V V V In In Out Out Positive latch (transparent when = 1) Negative latch (transparent when = 0) 42
43 Including Logic in TSPC V V V V PUN In 1 In 2 In PN In 1 In 2 Example: logic inside the latch AN latch 43
44 TSPC Register V V V M 3 M 6 M 9 Y M 2 X M 5 M 8 M 1 M 4 M 7 44
45 Pulse Triggered Latches An Alternative Approach Ways to design an edge-triggered dsequential cell: Master Slave SlaveLatches Pulse Triggered Latch ata L1 L2 L ata Clk Clk Clk Clk Clk 45
46 Pulsed Latches V V M 3 M 6 V G M 2 G M5 M P X G M M1 M N 4 M M (a) register (b) glitch generation G (c) glitch clock 46
47 Pulsed Latches Hybrid Latch Flip-flop (HLFF), AM K-6 and K-7 : P 1 P 3 x M 3 M 6 M 2 P 2 M 5 M 1 M 4 47
48 Hybrid Latch FF Timing lts Vo time (ns) 48
49 Latch Based Pipeline In F G Out C 1 C 2 C 3 Compute F compute G 49
50 Non Bistable Sequential Circuits Schmitt Trigger In Out V ou t V OH VTC with hysteresis V OL Restores signal slopes V M V M+ V in 50
51 Noise Suppression using Schmitt Trigger V in V out V M V M t 0 t t 0 + t p t 51
52 CMOS Schmitt Trigger V M 2 M 4 V in X V out M 1 M 3 Moves switching threshold of the first inverter 52
53 Schmitt Trigger Simulated VTC V M1 1.5 V X(V) 1.0 V M2 1.0 V x(v) k= 1 k= 2 k= k= V in (V) V in (V) Vlt Voltage-transfer t characteristics ti with hysteresis. The effect of varying the ratio of fthe PMOS device M 4. The width is k* 0.5 m m. 53
54 CMOS Schmitt Trigger (2) V M 4 M 6 M 3 M 6 In Out M 2 X M 5 V M 1 54
55 Multivibrator Circuits R S Bistable Multivibrator flip-flop, Schmitt Trigger T Monostable Multivibrator one-shot Astable Multivibrator oscillator 55
56 Transition Triggered Monostable In ELAY t d Out t d 56
57 Monostable Trigger (RC based) V In A R B Out C (a) Trigger circuit. In B V M (b) Waveforms. Out t t 1 t 2 57
58 Astable Multivibrators (Oscillators) N V 1 V 3 V 5 Ring Oscillator 2.0 Volts time (ns) simulated response of 5 stage oscillator 58
59 Relaxation Oscillator Out 1 Out 2 I1 I2 R C Int T = 2 (log3) RC 59
60 Voltage Controller Oscillator (VCO) V M6 V M4 Schmitt Trigger restores signal slopes In M2 I ref M1 I ref V contr M5 M3 Current starved inverter 6 t ph L (nsec) V contr (V) propagation delay as a function of control voltage 60
61 ifferential elay Element and VCO in1 V o 2 V o 1 in2 v 1 v 3 1 v 2 v 4 V ctrl delay cell 3.0 two stage VCO 2.5 V 1 V 2 V 3 V time (ns) simulated waveforms of 2 stage VCO 61
9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI esign Chapter IV esigning Sequential Logic Circuits (Chapter 7) 1 Sequential Logic Inputs Current State COMBINATIONAL LOGIC Registers Outputs Next state 2 storage mechanisms positive
More informationJan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. November Digital Integrated Circuits 2nd Sequential Circuits
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic esigning i Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL
More informationDigital Integrated Circuits A Design Perspective
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic esigning Sequential Logic Circuits November 2002 Naming Conventions In our text: a latch is level sensitive
More informationDigital Integrated Circuits A Design Perspective
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic esigning Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL LOGIC
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Designing Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL
More informationEE141- Spring 2007 Digital Integrated Circuits
EE141- Spring 27 igital Integrated Circuits Lecture 19 Sequential Circuits 1 Administrative Stuff Project Ph. 2 due Tu. 5pm 24 Cory box + email ee141- project@bwrc.eecs.berkeley.edu Hw 8 Posts this Fr.,
More informationLecture 9: Sequential Logic Circuits. Reading: CH 7
Lecture 9: Sequential Logic Circuits Reading: CH 7 Sequential Logic FSM (Finite-state machine) Inputs Current State COMBINATIONAL LOGIC Registers Outputs = f(current, inputs) Next state 2 storage mechanisms
More informationHold Time Illustrations
Hold Time Illustrations EE213-L09-Sequential Logic.1 Pingqiang, ShanghaiTech, 2018 Hold Time Illustrations EE213-L09-Sequential Logic.2 Pingqiang, ShanghaiTech, 2018 Hold Time Illustrations EE213-L09-Sequential
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 18 CMOS Sequential Circuits - 1 guntzel@inf.ufsc.br
More informationΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018
ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018 ΔΙΑΛΕΞΕΙΣ 12-13: esigning ynamic and Static CMOS Sequential Circuits ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ttheocharides@ucy.ac.cy) (ack: Prof. Mary Jane Irwin and
More informationSequential Logic. Digital Integrated Circuits A Design Perspective. Latch versus Register. Naming Conventions. Designing Sequential Logic Circuits
esigning Sequenial Logic Circuis Adaped from Chaper 7 of igial egraed Circuis A esign Perspecive Jan M. Rabaey e al. Copyrigh 23 Prenice Hall/Pearson Sequenial Logic pus Curren Sae COMBINATIONAL LOGIC
More informationMODULE 5 Chapter 7. Clocked Storage Elements
MODULE 5 Chapter 7 Clocked Storage Elements 3/9/2015 1 Outline Background Clocked Storage Elements Timing, terminology, classification Static CSEs Latches Registers Dynamic CSEs Latches Registers 3/9/2015
More informationCMPEN 411. Spring Lecture 18: Static Sequential Circuits
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 18: Static Sequential Circuits [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11
More informationY. Tsiatouhas. VLSI Systems and Computer Architecture Lab
CMOS INTEGRATE CIRCUIT ESIGN TECHNIUES University of Ioannina Memory Elements and other Circuits ept. of Computer Science and Engineering Y. Tsiatouhas CMOS Integrated Circuit esign Techniques Overview.
More informationTopics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance
More informationEECS 427 Lecture 15: Timing, Latches, and Registers Reading: Chapter 7. EECS 427 F09 Lecture Reminders
EECS 427 Lecture 15: Timing, Latches, and Registers Reading: Chapter 7 1 Reminders CA assignments CA7 is due Thursday at noon ECE Graduate Symposium Poster session in ECE Atrium on Friday HW4 (detailed
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationDesigning Sequential Logic Circuits
igital Integrated Circuits (83-313) Lecture 5: esigning Sequential Logic Circuits Semester B, 2016-17 Lecturer: r. Adam Teman TAs: Itamar Levi, Robert Giterman 26 April 2017 isclaimer: This course was
More informationEE141. Lecture 28 Multipliers. Lecture #20. Project Phase 2 Posted. Sign up for one of three project goals today
EE141-pring 2008 igital Integrated ircuits Lecture 28 Multipliers 1 Announcements Project Phase 2 Posted ign up for one of three project goals today Graded Phase 1 and Midterm 2 will be returned next Fr
More informationL4: Sequential Building Blocks (Flip-flops, Latches and Registers)
L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements: Lecture material adapted from R. Katz, G. Borriello, Contemporary Logic esign (second edition), Prentice-Hall/Pearson
More informationClock Strategy. VLSI System Design NCKUEE-KJLEE
Clock Strategy Clocked Systems Latch and Flip-flops System timing Clock skew High speed latch design Phase locked loop ynamic logic Multiple phase Clock distribution Clocked Systems Most VLSI systems are
More information5. Sequential Logic x Computation Structures Part 1 Digital Circuits. Copyright 2015 MIT EECS
5. Sequential Logic 6.004x Computation Structures Part 1 igital Circuits Copyright 2015 MIT EECS 6.004 Computation Structures L5: Sequential Logic, Slide #1 Something We Can t Build (Yet) What if you were
More informationL4: Sequential Building Blocks (Flip-flops, Latches and Registers)
L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements:., Materials in this lecture are courtesy of the following people and used with permission. - Randy H. Katz (University
More informationCMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues
CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan,
More informationTopics. CMOS Design Multi-input delay analysis. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics CMO Design Multi-input delay analysis pring 25 Transmission Gate OUT Z OUT Z pring 25 Transmission Gate OUT When is low, the output is at high impedance When is high, the output follows However,
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 18: March 27, 2018 Dynamic Logic, Charge Injection Lecture Outline! Sequential MOS Logic " D-Latch " Timing Constraints! Dynamic Logic " Domino
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 17: March 23, 2017 Energy and Power Optimization, Design Space Exploration, Synchronous MOS Logic Lecture Outline! Energy and Power Optimization
More informationChapter 13. Clocked Circuits SEQUENTIAL VS. COMBINATIONAL CMOS TG LATCHES, FLIP FLOPS. Baker Ch. 13 Clocked Circuits. Introduction to VLSI
Chapter 13 Clocked Circuits SEQUENTIAL VS. COMBINATIONAL CMOS TG LATCHES, FLIP FLOPS SET-RESET (SR) ARBITER LATCHES FLIP FLOPS EDGE TRIGGERED DFF FF TIMING Joseph A. Elias, Ph.D. Adjunct Professor, University
More informationSequential vs. Combinational
Sequential Circuits Sequential vs. Combinational Combinational Logic: Output depends only on current input TV channel selector (-9) inputs system outputs Sequential Logic: Output depends not only on current
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
More informationDigital Integrated Circuits A Design Perspective
igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1 Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational
More informationLecture 4: Implementing Logic in CMOS
Lecture 4: Implementing Logic in CMOS Mark Mcermott Electrical and Computer Engineering The University of Texas at ustin Review of emorgan s Theorem Recall that: () = + and = ( + ) (+) = and + = ( ) ()
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Total Power. Energy and Power Optimization. Worksheet Problem 1
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 20, 2018 Energy and Power Optimization, Design Space Exploration Lecture Outline! Energy and Power Optimization " Tradeoffs! Design
More informationEECS 427 Lecture 14: Timing Readings: EECS 427 F09 Lecture Reminders
EECS 427 Lecture 14: Timing Readings: 10.1-10.3 EECS 427 F09 Lecture 14 1 Reminders CA assignments Please submit CA6 by tomorrow noon CA7 is due in a week Seminar by Prof. Bora Nikolic SRAM variability
More informationJin-Fu Li Advanced Reliable Systems (ARES) Lab. Department of Electrical Engineering. Jungli, Taiwan
Chapter 7 Sequential Circuits Jin-Fu Li Advanced Reliable Systems (ARES) Lab. epartment of Electrical Engineering National Central University it Jungli, Taiwan Outline Latches & Registers Sequencing Timing
More informationMemory, Latches, & Registers
Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) How to save a few bucks at toll booths 5) Edge-triggered Registers L13 Memory 1 General Table Lookup Synthesis
More informationProperties of CMOS Gates Snapshot
MOS logic 1 Properties of MOS Gates Snapshot High noise margins: V OH and V OL are at V DD and GND, respectively. No static power consumption: There never exists a direct path between V DD and V SS (GND)
More informationDigital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo
Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Dynamic Logic Introduction Digital IC EE141 2 Dynamic logic outline Dynamic logic principle Dynamic logic
More informationLecture 9: Digital Electronics
Introduction: We can classify the building blocks of a circuit or system as being either analog or digital in nature. If we focus on voltage as the circuit parameter of interest: nalog: The voltage can
More informationGMU, ECE 680 Physical VLSI Design 1
ECE680: Physical VLSI Design Chapter VII Timing Issues in Digital Circuits (chapter 10 in textbook) GMU, ECE 680 Physical VLSI Design 1 Synchronous Timing (Fig. 10 1) CLK In R Combinational 1 R Logic 2
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistor-transistor
More informationEE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS. Kenneth R. Laker, University of Pennsylvania
1 EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS 2 -> ESD PROTECTION CIRCUITS (INPUT PADS) -> ON-CHIP CLOCK GENERATION & DISTRIBUTION -> OUTPUT PADS -> ON-CHIP NOISE DUE TO PARASITIC INDUCTANCE -> SUPER BUFFER
More informationVidyalankar S.E. Sem. III [EXTC] Digital Electronics Prelim Question Paper Solution ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD = B
. (a). (b). (c) S.E. Sem. III [EXTC] igital Electronics Prelim Question Paper Solution ABC ABC ABC ABC ABC ABC ABC ABC = B LHS = ABC ABC ABC ABC ABC ABC ABC ABC But ( ) = = ABC( ) ABC( ) ABC( ) ABC( )
More informationTime Allowed 3:00 hrs. April, pages
IGITAL ESIGN COEN 32 Prof. r. A. J. Al-Khalili Time Allowed 3: hrs. April, 998 2 pages Answer All uestions No materials are allowed uestion a) esign a half subtractor b) esign a full subtractor c) Using
More informationCOMBINATIONAL LOGIC. Combinational Logic
COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-cmos Combinational vs. Sequential Logic In Logic
More informationClock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements.
1 2 Introduction Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements. Defines the precise instants when the circuit is allowed to change
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More informationFundamentals of Computer Systems
Fundamentals of Computer Systems Sequential Logic Stephen A. Edwards Columbia University Summer 2017 State-Holding Elements Bistable Elements S Latch Latch Positive-Edge-Triggered Flip-Flop Flip-Flop with
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Combinational logic circuits Output
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC Dynamic Logic Introduction Digital IC 2 EE141 Dynamic
More informationINTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS
More informationTiming Issues. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić. January 2003
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić Timing Issues January 2003 1 Synchronous Timing CLK In R Combinational 1 R Logic 2 C in C out Out 2
More informationIssues on Timing and Clocking
ECE152B TC 1 Issues on Timing and Clocking X Combinational Logic Z... clock clock clock period ECE152B TC 2 Latch and Flip-Flop L CK CK 1 L1 1 L2 2 CK CK CK ECE152B TC 3 Clocking X Combinational Logic...
More informationF14 Memory Circuits. Lars Ohlsson
Lars Ohlsson 2018-10-18 F14 Memory Circuits Outline Combinatorial vs. sequential logic circuits Analogue multivibrator circuits Noise in digital circuits CMOS latch CMOS SR flip flop 6T SRAM cell 1T DRAM
More informationDigital EE141 Integrated Circuits 2nd Combinational Circuits
Digital Integrated Circuits Designing i Combinational Logic Circuits 1 Combinational vs. Sequential Logic 2 Static CMOS Circuit t every point in time (except during the switching transients) each gate
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationP2 (10 points): Given the circuit below, answer the following questions:
P1 (10 points): Given the function f(a, b, c, d) = m(3,4,5,10,14) + D(6,7): A: Fill in the timing diagram for f. B: Implement f using only 2-1 MUXes. Your circuit should not include more than four 2-1
More informationSequential Logic. Rab Nawaz Khan Jadoon DCS. Lecturer COMSATS Lahore Pakistan. Department of Computer Science
Sequential Logic Rab Nawaz Khan Jadoon DCS COMSATS Institute of Information Technology Lecturer COMSATS Lahore Pakistan Digital Logic and Computer Design Sequential Logic Combinational circuits with memory
More informationLecture 9: Clocking, Clock Skew, Clock Jitter, Clock Distribution and some FM
Lecture 9: Clocking, Clock Skew, Clock Jitter, Clock Distribution and some FM Mark McDermott Electrical and Computer Engineering The University of Texas at Austin 9/27/18 VLSI-1 Class Notes Why Clocking?
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2016 Final Friday, May 6 5 Problems with point weightings shown.
More informationDigital Electronics. Delay Max. FF Rate Power/Gate High Low (ns) (MHz) (mw) (V) (V) Standard TTL (7400)
P57/67 Lec9, P Digital Electronics Introduction: In electronics we can classify the building blocks of a circuit or system as being either analog or digital in nature. If we focus on voltage as the circuit
More informationSequential Logic Worksheet
Sequential Logic Worksheet Concept Inventory: Notes: D-latch & the Dynamic Discipline D-register Timing constraints for sequential circuits Set-up and hold times for sequential circuits 6.004 Worksheet
More informationLecture 5. MOS Inverter: Switching Characteristics and Interconnection Effects
Lecture 5 MOS Inverter: Switching Characteristics and Interconnection Effects Introduction C load = (C gd,n + C gd,p + C db,n + C db,p ) + (C int + C g ) Lumped linear capacitance intrinsic cap. extrinsic
More informationUNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences Elad Alon Homework #9 EECS141 PROBLEM 1: TIMING Consider the simple state machine shown
More informationChapter 4. Sequential Logic Circuits
Chapter 4 Sequential Logic Circuits 1 2 Chapter 4 4 1 The defining characteristic of a combinational circuit is that its output depends only on the current inputs applied to the circuit. The output of
More informationTopic 8: Sequential Circuits
Topic 8: Sequential Circuits Readings : Patterson & Hennesy, Appendix B.4 - B.6 Goals Basic Principles behind Memory Elements Clocks Applications of sequential circuits Introduction to the concept of the
More informationSequential Logic. Road Traveled So Far
Comp 2 Spring 25 2/ Lecture page Sequential Logic These must be the slings and arrows of outrageous fortune ) Synchronous as an implementation of Sequential 2) Synchronous Timing Analysis 3) Single synchronous
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.
More informationALU, Latches and Flip-Flops
CSE14: Components and Design Techniques for Digital Systems ALU, Latches and Flip-Flops Tajana Simunic Rosing Where we are. Last time: ALUs Plan for today: ALU example, latches and flip flops Exam #1 grades
More informationDual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS
TECHNICAL DATA IN74ACT74 Dual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74ACT74 is identical in pinout to the LS/ALS74, HC/HCT74. The IN74ACT74 may be used as a level converter
More informationCMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411
More informationThe Linear-Feedback Shift Register
EECS 141 S02 Timing Project 2: A Random Number Generator R R R S 0 S 1 S 2 1 0 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 0 0 1 1 0 0 The Linear-Feedback Shift Register 1 Project Goal Design a 4-bit LFSR SPEED, SPEED,
More informationINTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS
More informationUnit 7 Sequential Circuits (Flip Flop, Registers)
College of Computer and Information Sciences Department of Computer Science CSC 220: Computer Organization Unit 7 Sequential Circuits (Flip Flop, Registers) 2 SR Flip-Flop The SR flip-flop, also known
More informationLecture 1: Circuits & Layout
Lecture 1: Circuits & Layout Outline q A Brief History q CMOS Gate esign q Pass Transistors q CMOS Latches & Flip-Flops q Standard Cell Layouts q Stick iagrams 2 A Brief History q 1958: First integrated
More informationChapter 7 Sequential Logic
Chapter 7 Sequential Logic SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} March 28, 2016 Table of Contents 1 Intro 2 Bistable Circuits 3 FF Characteristics
More informationChapter #6: Sequential Logic Design
Chapter #6: equential Logic esign Contemporary Logic esign No. 6- Cross-Coupled NO Gates ust like cascaded inverters, with capability to force output to (reset) or (set) \ eset Hold et eset et ace \ Forbidden
More informationSequential Logic Circuits
Chapter 4 Sequential Logic Circuits 4 1 The defining characteristic of a combinational circuit is that its output depends only on the current inputs applied to the circuit. The output of a sequential circuit,
More informationCPE/EE 427, CPE 527 VLSI Design I L07: CMOS Logic Gates, Pass Transistor Logic. Review: CMOS Circuit Styles
PE/EE 427, PE 527 VLI esign I L07: MO Logic Gates, Pass Transistor Logic epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka
More informationCircuit A. Circuit B
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on November 19, 2006 by Karl Skucha (kskucha@eecs) Borivoje Nikolić Homework #9
More informationCPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Inverter: A First Look
CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates epartment of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka )
More informationVidyalankar S.E. Sem. III [ETRX] Digital Circuits and Design Prelim Question Paper Solution
S.E. Sem. III [ETRX] Digital Circuits and Design Prelim uestion Paper Solution. (a) Static Hazard Static hazards have two cases: static and static. static- hazard exists when the output variable should
More informationLecture 320 Improved Open-Loop Comparators and Latches (3/28/10) Page 320-1
Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 321 LECTURE 32 IMPROVED OPENLOOP COMPARATORS AND LATCHES LECTURE ORGANIZATION Outline Autozeroing Hysteresis Simple es Summary CMOS Analog
More informationNTE4035B Integrated Circuit CMOS, 4 Bit Parallel In/Parallel Out Shift Register
NTE4035B Integrated Circuit CMOS, 4 Bit Parallel In/Parallel Out Shift Register Description: The NTE4035B is a 4 bit shift register in a 16 Lead DIP type package constructed with MOS P Channel an N Channel
More informationEEE 421 VLSI Circuits
EEE 421 CMOS Properties Full rail-to-rail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady
More informationDigital Integrated Circuits A Design Perspective
Designing ombinational Logic ircuits dapted from hapter 6 of Digital Integrated ircuits Design Perspective Jan M. Rabaey et al. opyright 2003 Prentice Hall/Pearson 1 ombinational vs. Sequential Logic In
More informationCMOS Inverter: CPE/EE 427, CPE 527 VLSI Design I L06: CMOS Inverter, CMOS Logic Gates. Course Administration. CMOS Properties.
CMOS Inverter: Steady State Response CPE/EE 47, CPE 57 VLSI esign I L6: CMOS Inverter, CMOS Logic Gates R p V OL = V OH = V M = f(r n, R p ) epartment of Electrical and Computer Engineering University
More informationECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering SEQUENTIAL CIRCUITS: LATCHES Overview Circuits require memory to store intermediate
More informationCMOS Inverter. Performance Scaling
Announcements Exam #2 regrade requests due today. Homework #8 due today. Final Exam: Th June 12, 8:30 10:20am, CMU 120 (extension to 11:20am requested). Grades available for viewing via Catalyst. CMOS
More informationCombinatorial and Sequential CMOS Circuits Dr. Lynn Fuller Webpage:
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Combinatorial and Sequential CMOS Circuits Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585)
More informationS.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques
S.Y. Diploma : Sem. III [DE/ED/EI/EJ/EN/ET/EV/EX/IC/IE/IS/IU/MU] Principles of Digital Techniques Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 100 Q.1(a) Attempt any SIX of the following : [12]
More informationEEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this
More informationClocking Issues: Distribution, Energy
EE M216A.:. Fall 2010 Lecture 12 Clocking Issues: istribution, Energy Prof. ejan Marković ee216a@gmail.com Clock istribution Goals: eliver clock to all memory elements with acceptable skew eliver clock
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2018 Final Monday, Apr 0 5 Problems with point weightings shown.
More informationChapter 5 CMOS Logic Gate Design
Chapter 5 CMOS Logic Gate Design Section 5. -To achieve correct operation of integrated logic gates, we need to satisfy 1. Functional specification. Temporal (timing) constraint. (1) In CMOS, incorrect
More informationA Guide. Logic Library
Logic A Guide To The Logic Library SystemView by ELANIX Copyright 1994-2005, Eagleware Corporation All rights reserved. Eagleware-Elanix Corporation 3585 Engineering Drive, Suite 150 Norcross, GA 30092
More informationSkew-Tolerant Circuit Design
Skew-Tolerant Circuit Design David Harris David_Harris@hmc.edu December, 2000 Harvey Mudd College Claremont, CA Outline Introduction Skew-Tolerant Circuits Traditional Domino Circuits Skew-Tolerant Domino
More informationUniversity of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering
University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering Final Examination ECE 241F - Digital Systems Examiners: J. Rose and
More informationDistributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download:
More informationSequential Logic. Handouts: Lecture Slides Spring /27/01. L06 Sequential Logic 1
Sequential Logic Handouts: Lecture Slides 6.4 - Spring 2 2/27/ L6 Sequential Logic Roadmap so far Fets & voltages Logic gates Combinational logic circuits Sequential Logic Voltage-based encoding V OL,
More information