! Crosstalk. ! Repeaters in Wiring. ! Transmission Lines. " Where transmission lines arise? " Lossless Transmission Line.
|
|
- Verity Hampton
- 5 years ago
- Views:
Transcription
1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission lines arise? " Lossless Transmission Line " Termination " Lossy Transmission Line 2 Capacitance Crosstalk! There are capacitors everywhere! Already talked about " Wires modeled as a distributed RC network " Parasitic capacitances between terminals on transistor 3 4 Capacitance Everywhere Capacitance! Potentially a capacitor between any two conductors " On the chip " On the package " On the board! decrease with conductor separation! increase with size! depends on dielectric! All wires " Package pins " PCB traces " Cable wires " Bit/word lines C = ε r ε 0 A d 5 6 1
2 Wire Capacitance Crosstalk! Changes in voltage on one wire may couple through parasitic capacitance to an adjacent wire! A capacitor does not like to change its voltage instantaneously! A wire has high capacitance to its neighbor. " When the neighbor switches from 1-> 0 or 0->1, the wire tends to switch too. " Called capacitive coupling or crosstalk.! Crosstalk effects " Noise on nonswitching wires " Increased delay on switching wires 7 Slide 8 Driven Wire Qualitative! What happens to a driven neighbor wire? " One wire switches " Neighbors driven but not switch " What happens to neighbors? 10 Driven Wire Undriven Wire! Can this be a problem?! What if neighbor is:! What happens to undriven wire?! Where do we have undriven wires? " Clock line " Asynchronous control " Non-clock used in synchronous system " Outputs sampled at clock edge
3 Clocked Logic! CMOS driven lines! Clocked logic " Willing to wait to settle Quantitative! Impact is on delay " May increase delay of transitions 13 Wire step response Undriven Adjacent Wire! Step response for isolated wire?! V 1 transitions from 0 to V " How big is the noise on V 2? Undriven Adjacent Wire Undriven Adjacent Wire! V 1 transitions from 0 to V " How big is the noise on V 2? I(t) = C dv(t) dt! V 1 transitions from 0 to V " How big is the noise on V 2? I(t) = C dv(t) dt d(v C 1 (t) V 2 (t)) dv 1 = C 2 (t) 2 dt dt dv C 1 (t) 1 = (C 1 + C 2 ) dv (t) 2 dt dt C 1 V 1 (t) = (C 1 + C 2 )V 2 (t) V 2 (t) = V 1 (t) C 1 + C C 1 3
4 SPICE C 1 =10pF, C 2 =20pF Good (?) Capacitance! High capacitance to ground plane " Limits node swing from adjacent conductors " C V 2 = 1 $ ' V # C 1 + C 1 2 & Driven Adjacent Wire Driven Adjacent Wire! What happens when neighbor line is driven?! What happens when neighbor line is driven? " Recovers with time constant: R 2 (C 1 +C 2 ) Spice: R 2 =1K, C 1 =10pF, C 2 =20pF Magnitude of Noise on Driven Line! Magnitude of diversion depends on relative time constants " τ 1 << τ 2 " full diversion, then recover " τ 1 >> τ 2 " Drive capacitor faster than line 1 can change diversion " τ 1 ~= τ 2 " little noise " Somewhere in between
5 Spice: C 1 =1pF, C 2 =2pF Switching Line with Finite Drive! What impact does the presence of the non switching line have on the switching line? " All previous questions were about non-switching " Note R on switching Simultaneous Transition Simultaneous Transition! What happens if lines transition in opposite directions?! What happens if transition in opposite directions? " Must charge C 1 by 2V " Or looks like 2C 1 between wires Simultaneous Transition Simulation! What happens if lines transition in same direction?! V 2 switching at ¼ frequency of V 1! No crosstalk reference case where no V
6 Simulation Setup Crosstalk Simulation V1 V2 C1 C2 C2 1.3ns 1.8ns 2.8ns Crosstalk Simulation Crosstalk Simulation 1.3ns 1.8ns 2.8ns 1.3ns 1.8ns 2.8ns Cables and PCB Wires Where Does it Arise? Source;
7 Printed Circuit Board Interconnect Cross Section Source: 37 Standard Cell Area Noise Implications!! All cells uniform height Penn ESE 570 Spring Khanna Width of channel determined by routing! "! 39 But glitches cause extra delay Also cause extra power from false transitions Dynamic logic never recovers from glitches "! Wire Engineering! " Can t correct mid-cycle, need precharge Memories and other sensitive circuits also can produce the wrong result (i.e faults) Slide 40 Wire Engineering Goal: achieve delay, area, power goals with acceptable noise Degrees of freedom:!! Goal: achieve delay, area, power goals with acceptable noise Degrees of freedom: " " " Width Spacing Layer Coupling:2Cadj / (2C adj+cgnd) Cell area! So what if we have noise? If the noise is less than the noise margin, nothing happens Static CMOS logic will eventually settle to correct output even if disturbed by large noise spikes Delay (ns):rc/2 inv nand w s Pitch (nm) WireSpacing (nm) Pitch (nm) l t h Slide 41 Slide 42 7
8 Wire Engineering! Goal: achieve delay, area, power goals with acceptable noise! Degrees of freedom: " Width " Spacing " Layer " Shielding Delay (ns): RC/ Pitch (nm) Coupling: 2C adj / (2C adj +nd ) Pitch (nm) Wire Spacing (nm) Repeaters in Wiring vdd a 0 a 1 gnd a 2 vdd a 0 a 1 gnd a 2 a 3 vdd gnd a 0 b 1 vdd b 0 a 1 a 2 b 2 Slide 43 Reminder: Wire Delay Interconnect Buffering! Wire N units long: =R unit *C unit *N 2 /2! With " R unit =1kΩ " C unit =1pF R wire = N R unit = N C unit! RC (on-chip) Interconnect Buffering Penn ESE 570 Spring Khanna Delay of Wire Formulate Delay! Long Wire: 1mm! R u = 60K Ω per 1mm of wire! C u = 0.16 pf per 1mm of wire! Driven by buffer " = 25K Ω " C self = 0.02 ff " = 0.01fF! Loaded by identical buffer Delay of buffer driving wire?
9 Formulate Delay Calculate Delay! C load =! =! C self =! =! R wire = Delay of buffer driving wire? + + C load ) + 0.5R wire C load + + C load ) + 0.5R wire C load Calculate Delay Calculate Delay! C load = 2 =.02fF! = 25K Ω! C self = 0.02fF! = L*C u =.16pF! R wire = L*R u = 60K Ω! C load = 2 =.02fF! = 25K Ω! C self = 0.02fF! = L*C u =.16pF! R wire = L*R u = 60K Ω 8.8ns + + C load ) + 0.5R wire C load + + C load ) + 0.5R wire C load 4ns + 4.8ns +1.2ps Buffering Wire Buffering Wire: L/2! C load =! =! C self =! =! R wire =
10 Buffering Wire: L/2! C load = 2 =.02fF! = 25K Ω! C self =.02fF! = L/2*C u =.08pF! R wire = L/2*R u = 30K Ω Buffering Wire: L/2! C load = 2 =.02fF! = 25K Ω! C self =.02fF! = L/2*C u =.08pF! R wire = L/2*R u = 30K Ω + + C load ) + 0.5R wire C load 2ns +1.2ns +.6ps = 3.2ns Buffering Wire: L/2 Buffering Wire: L/N! C load = 2 =.02fF! = 25K Ω! C self =.02fF! = L/2*C u =.08pF! R wire = L/2*R u = 30K Ω 6.4ns Wire of Length Delay (ns) Number in 1mm Total Delay for 1mm (ns) 1 mm 8.8ns 1 8.8ns 0.5mm 3.2ns 2 6.4ns 0.1mm C load ) + 0.5R wire C load 2ns +1.2ns +.6ps = 3.2ns 0.01 mm mm C load ) + 0.5R wire C load Buffering Wire: L/N N Buffers! Delay Equation for N buffers? Wire of Length Delay (ns) Number in 1mm (N) Total Delay for 1mm (ns) 1 mm 8.8ns 1 8.8ns 0.5mm 3.2ns 2 6.4ns N C self + N +C load R wire N N N C load 0.1mm 0.45ns ns 0.01 mm.041ns ns mm.005ns ns + + C load ) + 0.5R wire C load
11 Minimize Delay! Minimize delay! Derivative with respect to N and solve for 0 N ( C self +C load ) R N wire C load 0 = ( C self +C load ) R N 2 wire Minimize Delay Equalizes delay in buffer and wire N = 0.5R wire C self + C load ( ) N R ( buf C self + C ) + R C + 0.5! 1 $ load # buf wire " N &R wire C load N = 0.5R wire ( C self +C load ) Delay with Optimal N Segment Length 0.5R wire C self + C load ( ) ( C self + C load ) ! # # " C self + C $ ( load ) & 0.5R wire & R C + R wire wire load 0.5R wire ( ( C self + C load )) R wire ( ( C self + C load )) C load 2 0.5R wire ( ( C self + C load )) + C load 63! R wire = L R unit! = L C unit * L seg * L seg = L N # & R N = 0.5 wire ( $ + C load )( ' # & R N = L 0.5 u C u ( $ + C load )( ' ( ) = L " N = 2 C self + C load $ # R u C ' u & 64 Optimal Segment Length! Delay scales linearly with distance once optimally buffered * L seg ( ) = L # N = 2 C self + C & load ( R u C $ u ( ' # & R N = L 0.5 u C u ( $ + C load )( ' Buffer Size?! How big should buffer be? " = R un /W " C self = 2 W C dff = 2 W γ " C load = 2 W
12 Buffer Size? Implication on Buffer Size - W! How big should buffer be? " = R un /W! R wire = L R unit! = L C unit " C self = 2 W C dff = 2 W γ " C load = 2 W 2 0.5R wire ( ( C self + C load )) + C load! R 2 0.5R wire C un wire W 2WC $ # ( g ( 1+γ) )& + R un " W 2W 2 0.5R wire ( 2R un ( 1+γ) ) + R un W 2W 0 = 2R wire R un 1 W 2 W = R un 2R wire = R un C unit 2R unit 2 0.5R wire ( 2R un ( 1+γ) ) + R un W 2W! # W independent of Length " Depends on technology Delay at Optimum W Delay at Optimum W 2 0.5R wire ( 2R un ( 1+γ) ) + R un W 2W 2 0.5R wire ( 2R un ( 1+γ) ) + R un R un 2R wire 2 R un 2R wire 2 0.5R wire ( 2R un ( 1+γ) ) + R un 2R wire + R un 2R wire 2 0.5R wire ( 2R un ( 1+γ) ) + 2 2R un R wire! If γ=1 2 R wire ( R un ( 1+1) ) + 2 2R un R wire 2 2R un R wire + 2 2R un R wire 4 2R un R wire! Optimal design equalizes all delays! Transmission Lines Where Transmission Lines Arise! Cable: coaxial! PCB " Strip line " Microstrip line! Twisted Pair (Cat5)
13 Transmission Lines! This is what wires/cables look like " Aren t an ideal equipotential Wire Formulation " Signals do take time to propagate " Maintain shape of input signal " Within limits " Shape and topology of wiring effects how signals propagate! Need theory/model to support design " Reason about behavior " Understand what can cause noise " Engineer high performance/speed communication Wires RC Wire! In general, our wires have distributed R, L, C components! When R dominates L " We have the distributed RC Wires " Typical of on-chip wires in ICs Lossless Transmission Line Intuitive: Lossless! When resistance is negligible! Pulses travel as waves without distortion " Have L = Lossless Transmission Line " (up to a characteristic frequency) " No energy dissipation (loss) through R s " More typical of Printed Circuit Board wires and bond wires
14 SPICE Simulation Step Response SPICE Pulse Response SPICE Contrast RC Wire Contrast Model! Now voltage is a function of time and position " Position along wire distance from source! Want to get V(x,t) " And I(x,t)
15 Implication Propagation Rate in Example " Wave equation: " Solution: 2 V x = LC 2 V t V(x,t) = A + Be x wt! L=1uH! C=1pF! What is w? w = 1 LC " What is w? Be x wt = LCw 2 Be x wt w = 1 LC w is the rate of propogation Signal Propagation Signal Propagation Delay linear in length Contrast RC Wire Impedance R delay quadratic in length.5r un C un N 2! Transmission lines have a characteristic impedance Z 0 = L C
16 Infinite Lossless Transmission Line! Transmission line looks like resistive load Z 0 = L C Termination Z 0! Input waveform travels down line at velocity " Without distortion w = 1 LC 91 End of Line! What happens at the end of the transmission line? Analyze End of Line! Incident Wave, Reflected Wave, Transverse Wave End of Line! What happens at the end of the transmission line? " Short Circuit, R=0 " Hint: what must happen in steady state? " Terminate with R=Z 0 " Open Circuit, R= Reflection Reflection coefficient # R Z V 0 & i ( = V $ R + Z r 0 '
17 Analyze End of Line Open! V i +V r =V t " R Z V 0 i $ ' = V r # R + Z 0 & " R Z V 0 i $ ' = V t V i # R + Z 0 & " R Z V 0 i $ +1' = V t # R + Z 0 & " 2R Transmission coefficient V i $ ' = V t # R + Z 0 & # R Z V 0 & i ( = V $ R + Z r 0 ' Terminate R=Z 0 Short # R Z V 0 & i ( = V $ R + Z r 0 ' # R Z V 0 & i ( = V $ R + Z r 0 ' Longer LC (open) Pulse Travel RC! 40 Stages! L=100nH! C=1pF w = 1 LC = c 0 ε r µ r Stage delay? How long to propogate?! V1,V3,V4,V5,V6 about 10 stages apart! Drive with 2ns Pulse! No termination (open circuit) " What reflection do we expect?
18 Visualization! Back to Source Matched Open Short Back at Source? R Z 0! What happens at source?! What happens? " Depends on how it s terminated " 75 Ω termination on 50 Ω line Transmission Line Symbol Simulation! Specify delay of full Tline and characteristic impedance! Need reference! For these, with direct drive from voltage source " Source looks like short circuit (not typical of CMOS) " Source cannot be changed
19 50Ω line, 75Ω termination Source Series Termination! What happens here? # R Z V r = V 0 & # 75 50& i ( = V $ R + Z i ( = 0.2V 0 ' $ ' i Simulation Series Termination! R series = Z 0! Initial voltage divider " Half voltage pulse propogates down Tline! End of line open circuit " Sees single transition to full voltage (full reflection)! Reflection returns to source and sees termination R series = Z 0! No further reflections CMOS Driver / Receiver CMOS Driver! Driver: What does a CMOS driver look like at the source? " I d,sat 45nm, V dd =1V! Receiver: What does a CMOS inverter look like at the sink?! Driver: What does a CMOS driver look like at the source? " I d,sat 45nm, V dd =1V " Min size: " I drive =1200µA/µm*45nm=54µA " R out =V dd /I drive =18kΩ
20 CMOS Driver CMOS Receiver! Driver: What does a CMOS driver look like at the source? " I d,sat 45nm, V dd =1V " Min size: " I drive =1200µA/µm*45nm=54µA " R out =V dd /I drive =18kΩ " W=370 " I drive =1200µA/µm*45nm*370=20mA " R out =V dd /I drive =50Ω! Receiver: What does a CMOS inverter look like at the sink? Lossy Transmission Line Lossy Transmission Line! How do addition of R s change? " Concretely, discretely think about R=0.2Ω every meter on Z 0 =100Ω " what does each R do?! Each R is a mismatched termination! Each R is a voltage divider " 2(R + Z V t = V 0 ) i $ ' #(R + Z 0 ) + Z 0 & " Z V i+1 = V 0 t $ ' # R + Z 0 & Lossy Transmission Line Lossy Transmission Line " 2(R + Z V i+1 = V 0 ) " Z 0 i $ ' $ ' #(R + Z 0 ) + Z 0 &# R + Z 0 & "" 2(R + Z V snk = V 0 ) " Z 0 src $ $ ' $ '' ##(R + Z 0 ) + Z 0 &# R + Z 0 && N! How long before drop voltage by half? R=0.2Ω every meter on Z 0 =100Ω "" 2(R + Z V snk = V 0 ) " Z 0 src $ $ ' $ '' ##(R + Z 0 ) + Z 0 &# R + Z 0 && N
21 Idea! Capacitance is everywhere, especially between adjacent wires, and will get noise from crosstalk " Clocked and driven wires " Slow down transitions " Undriven wires voltage changed " Can cause spurious/false transitions! Wire delay linear once buffered optimally " Optimal buffering equalizes delays " Buffer delay, Delay on wire between buffers, Delay of wire driving buffer! Transmission lines " high-speed " high throughput " long-distance signaling! Termination Admin! Tania extra office hours " Monday 1-3pm! Tuesday (last) lecture " Details about final exam " Review for final exam
ESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission
More informationInterconnects. Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters. ECE 261 James Morizio 1
Interconnects Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters ECE 261 James Morizio 1 Introduction Chips are mostly made of wires called interconnect In stick diagram,
More informationInterconnects. Introduction
Interconnects Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters ECE 261 Krish Chakrabarty 1 Introduction Chips are mostly made of ires called interconnect In stick diagram,
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 17, 2018 I/O Circuits, Inductive Noise, CLK Generation Lecture Outline! Packaging! Variation and Testing! I/O Circuits! Inductive
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 13, 2017 Variation; I/O Circuits, Inductive Noise Lecture Outline! Design Quality " Variation! Packaging! Variation and Testing!
More informationAnnouncements. EE141- Fall 2002 Lecture 25. Interconnect Effects I/O, Power Distribution
- Fall 2002 Lecture 25 Interconnect Effects I/O, Power Distribution Announcements Homework 9 due next Tuesday Hardware lab this week Project phase 2 due in two weeks 1 Today s Lecture Impact of interconnects»
More informationDigital Integrated Circuits. The Wire * Fuyuzhuo. *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk. Digital IC.
Digital Integrated Circuits The Wire * Fuyuzhuo *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk Introduction The Wire transmitters receivers schematics physical 2 Interconnect Impact
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler
More informationLecture 23. Dealing with Interconnect. Impact of Interconnect Parasitics
Lecture 23 Dealing with Interconnect Impact of Interconnect Parasitics Reduce Reliability Affect Performance Classes of Parasitics Capacitive Resistive Inductive 1 INTERCONNECT Dealing with Capacitance
More informationMidterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: 1st Order RC Delay Models. Review: Two-Input NOR Gate (NOR2)
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 14: March 1, 2016 Combination Logic: Ratioed and Pass Logic Lecture Outline! CMOS Gates Review " CMOS Worst Case Analysis! Ratioed Logic Gates!
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 3, 2016 Combination Logic: Ratioed & Pass Logic, and Performance Lecture Outline! CMOS NOR2 Worst Case Analysis! Pass Transistor
More informationInterconnect (2) Buffering Techniques.Transmission Lines. Lecture Fall 2003
Interconnect (2) Buffering Techniques.Transmission Lines Lecture 12 18-322 Fall 2003 A few announcements Partners Lab Due Times Midterm 1 is nearly here Date: 10/14/02, time: 3:00-4:20PM, place: in class
More informationName: Answers. Mean: 83, Standard Deviation: 12 Q1 Q2 Q3 Q4 Q5 Q6 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Final Tuesday, December 15 Problem weightings
More informationVLSI GATE LEVEL DESIGN UNIT - III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
VLSI UNIT - III GATE LEVEL DESIGN P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Time Delays, Driving large
More informationECE 497 JS Lecture - 18 Noise in Digital Circuits
ECE 497 JS Lecture - 18 Noise in Digital Circuits Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 Announcements Thursday April 15 th Speaker:
More informationE40M Capacitors. M. Horowitz, J. Plummer, R. Howe
E40M Capacitors 1 Reading Reader: Chapter 6 Capacitance A & L: 9.1.1, 9.2.1 2 Why Are Capacitors Useful/Important? How do we design circuits that respond to certain frequencies? What determines how fast
More informationSRAM System Design Guidelines
Introduction This application note examines some of the important system design considerations an engineer should keep in mind when designing with Cypress SRAMs. It is important to note that while they
More information! Memory. " RAM Memory. ! Cell size accounts for most of memory array size. ! 6T SRAM Cell. " Used in most commercial chips
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec : April 3, 8 Memory: Core Cells Today! Memory " RAM Memory " Architecture " Memory core " SRAM " DRAM " Periphery Penn ESE 57 Spring 8 - Khanna
More informationName: Answers. Mean: 38, Standard Deviation: 15. ESE370 Fall 2012
University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2012 Final Friday, December 14 Problem weightings
More informationEE115C Digital Electronic Circuits Homework #5
EE115C Digital Electronic Circuits Homework #5 Due Thursday, May 13, 6pm @ 56-147E EIV Problem 1 Elmore Delay Analysis Calculate the Elmore delay from node A to node B using the values for the resistors
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 18: March 27, 2018 Dynamic Logic, Charge Injection Lecture Outline! Sequential MOS Logic " D-Latch " Timing Constraints! Dynamic Logic " Domino
More informationTopics to be Covered. capacitance inductance transmission lines
Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of
More information! Delay when A=1, B=0? ! CMOS Gates. " Dual pull-down and pull-up networks, only one enabled at a time
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Pass Transistor XOR Delay when A, B0? Start with equivalent RC circuit Lec : October 9, 08 Driving Large Capacitive Loads 3
More informationECE414/514 Electronics Packaging Spring 2012 Lecture 6 Electrical D: Transmission lines (Crosstalk) Lecture topics
ECE414/514 Electronics Packaging Spring 2012 Lecture 6 Electrical D: Transmission lines (Crosstalk) James E. Morris Dept of Electrical & Computer Engineering Portland State University 1 Lecture topics
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationVery Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI Contents Delay estimation Simple RC model Penfield-Rubenstein Model Logical effort Delay
More informationEE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS. Kenneth R. Laker, University of Pennsylvania
1 EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS 2 -> ESD PROTECTION CIRCUITS (INPUT PADS) -> ON-CHIP CLOCK GENERATION & DISTRIBUTION -> OUTPUT PADS -> ON-CHIP NOISE DUE TO PARASITIC INDUCTANCE -> SUPER BUFFER
More informationEE241 - Spring 2000 Advanced Digital Integrated Circuits. Announcements
EE241 - Spring 2000 Advanced Digital Integrated Circuits Lecture 3 Circuit Optimization for Speed Announcements Tu 2/8/00 class will be pre-taped on Friday, 2/4, 4-5:30 203 McLaughlin Class notes are available
More informationCARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002
CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed
More informationDigital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo
Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Dynamic Logic Introduction Digital IC EE141 2 Dynamic logic outline Dynamic logic principle Dynamic logic
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: March 29, 2018 Memory Overview, Memory Core Cells Today! Charge Leakage/Charge Sharing " Domino Logic Design Considerations! Logic Comparisons!
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More informationEE141-Spring 2008 Digital Integrated Circuits EE141. Announcements EECS141 EE141. Lecture 24: Wires
EE141-Spring 2008 Digital Integrated Circuits Lecture 24: Wires 1 Announcements Hw 8 posted last graded homework Project phase II feedback to be expected anytime 2 Material Last Lecture: Wire capacitance
More informationNon-Sinusoidal Waves on (Mostly Lossless)Transmission Lines
Non-Sinusoidal Waves on (Mostly Lossless)Transmission Lines Don Estreich Salazar 21C Adjunct Professor Engineering Science October 212 https://www.iol.unh.edu/services/testing/sas/tools.php 1 Outline of
More informationLecture 16: Circuit Pitfalls
Introduction to CMOS VLSI Design Lecture 16: Circuit Pitfalls David Harris Harvey Mudd College Spring 2004 Outline Pitfalls Detective puzzle Given circuit and symptom, diagnose cause and recommend solution
More informationInterconnect (2) Buffering Techniques. Logical Effort
Interconnect (2) Buffering Techniques. Logical Effort Lecture 14 18-322 Fall 2002 Textbook: [Sections 4.2.1, 8.2.3] A few announcements! M1 is almost over: The check-off is due today (by 9:30PM) Students
More informationCMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues
CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 17: Dynamic Sequential Circuits And Timing Issues [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan,
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationLecture 7 Circuit Delay, Area and Power
Lecture 7 Circuit Delay, Area and Power lecture notes from S. Mitra Intro VLSI System course (EE271) Introduction to VLSI Systems 1 Circuits and Delay Introduction to VLSI Systems 2 Power, Delay and Area:
More informationLecture 4: DC & Transient Response
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide
More informationLecture 21: Packaging, Power, & Clock
Lecture 21: Packaging, Power, & Clock Outline Packaging Power Distribution Clock Distribution 2 Packages Package functions Electrical connection of signals and power from chip to board Little delay or
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2018 Final Monday, Apr 0 5 Problems with point weightings shown.
More informationDigital Integrated Circuits (83-313) Lecture 5: Interconnect. Semester B, Lecturer: Adam Teman TAs: Itamar Levi, Robert Giterman 1
Digital Integrated Circuits (83-313) Lecture 5: Interconnect Semester B, 2015-16 Lecturer: Adam Teman TAs: Itamar Levi, Robert Giterman 1 What will we learn today? 1 A First Glance at Interconnect 2 3
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC Dynamic Logic Introduction Digital IC 2 EE141 Dynamic
More information! Charge Leakage/Charge Sharing. " Domino Logic Design Considerations. ! Logic Comparisons. ! Memory. " Classification. " ROM Memories.
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 9, 8 Memory Overview, Memory Core Cells Today! Charge Leakage/ " Domino Logic Design Considerations! Logic Comparisons! Memory " Classification
More informationLecture 9: Clocking, Clock Skew, Clock Jitter, Clock Distribution and some FM
Lecture 9: Clocking, Clock Skew, Clock Jitter, Clock Distribution and some FM Mark McDermott Electrical and Computer Engineering The University of Texas at Austin 9/27/18 VLSI-1 Class Notes Why Clocking?
More informationInterconnect s Role in Deep Submicron. Second class to first class
Interconnect s Role in Deep Submicron Dennis Sylvester EE 219 November 3, 1998 Second class to first class Interconnect effects are no longer secondary # of wires # of devices More metal levels RC delay
More informationDistributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. DS0026 Dual High-Speed MOS Driver General Description DS0026 is a low cost
More informationCPE/EE 427, CPE 527 VLSI Design I L13: Wires, Design for Speed. Course Administration
CPE/EE 427, CPE 527 VLSI Design I L3: Wires, Design for Speed Department of Electrical and Computer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe527-05f
More informationCMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07: Pass Transistor Logic [dapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey,. Chandrakasan,. Nikolic] Sp11 CMPEN 411
More informationCOMP 103. Lecture 16. Dynamic Logic
COMP 03 Lecture 6 Dynamic Logic Reading: 6.3, 6.4 [ll lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP03
More informationMM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer
MM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer General Description The MM74C150 and MM82C19 multiplex 16 digital lines to 1 output. A 4-bit address code determines
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 15, 2018 MOS Inverter: Dynamic Characteristics Penn ESE 570 Spring 2018 Khanna Lecture Outline! Inverter Power! Dynamic Characteristics
More informationTransmission Line Basics
Transmission Line Basics Prof. Tzong-Lin Wu NTUEE 1 Outlines Transmission Lines in Planar structure. Key Parameters for Transmission Lines. Transmission Line Equations. Analysis Approach for Z and T d
More informationSCSI Connector and Cable Modeling from TDR Measurements
SCSI Connector and Cable Modeling from TDR Measurements Dima Smolyansky TDA Systems, Inc. http://www.tdasystems.com Presented at SCSI Signal Modeling Study Group Rochester, MN, December 1, 1999 Outline
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationECE321 Electronics I
ECE31 Electronics Lecture 1: CMOS nverter: Noise Margin & Delay Model Payman Zarkesh-Ha Office: ECE Bldg. 30B Office hours: Tuesday :00-3:00PM or by appointment E-mail: payman@ece.unm.edu Slide: 1 CMOS
More informationEECS 151/251A Homework 5
EECS 151/251A Homework 5 Due Monday, March 5 th, 2018 Problem 1: Timing The data-path shown below is used in a simple processor. clk rd1 rd2 0 wr regfile 1 0 ALU REG 1 The elements used in the design have
More informationMODULE III PHYSICAL DESIGN ISSUES
VLSI Digital Design MODULE III PHYSICAL DESIGN ISSUES 3.2 Power-supply and clock distribution EE - VDD -P2006 3:1 3.1.1 Power dissipation in CMOS gates Power dissipation importance Package Cost. Power
More informationClock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements.
1 2 Introduction Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements. Defines the precise instants when the circuit is allowed to change
More informationEE213, Spr 2017 HW#3 Due: May 17 th, in class. Figure 1
RULES: Please try to work on your own. Discussion is permissible, but identical submissions are unacceptable! Please show all intermediate steps: a correct solution without an explanation will get zero
More informationLecture 9: Interconnect
Digital Integrated Circuits (83-313) Lecture 9: Interconnect Semester B, 2016-17 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 23 May 2017 Disclaimer: This course was prepared, in its entirety,
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More informationEE115C Digital Electronic Circuits Homework #4
EE115 Digital Electronic ircuits Homework #4 Problem 1 Power Dissipation Solution Vdd =1.0V onsider the source follower circuit used to drive a load L =20fF shown above. M1 and M2 are both NMOS transistors
More informationA capacitor is a device that stores electric charge (memory devices). A capacitor is a device that stores energy E = Q2 2C = CV 2
Capacitance: Lecture 2: Resistors and Capacitors Capacitance (C) is defined as the ratio of charge (Q) to voltage (V) on an object: C = Q/V = Coulombs/Volt = Farad Capacitance of an object depends on geometry
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 17: March 26, 2019 Energy Optimization & Design Space Exploration Penn ESE 570 Spring 2019 Khanna Lecture Outline! Energy Optimization! Design
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 16, 2016 MOS Inverter: Dynamic Characteristics Lecture Outline! Review: Symmetric CMOS Inverter Design! Inverter Power! Dynamic
More informationCMPEN 411 VLSI Digital Circuits Spring 2012
CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 09: Resistance & Inverter Dynamic View [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic]
More informationDS0026 Dual High-Speed MOS Driver
Dual High-Speed MOS Driver General Description DS0026 is a low cost monolithic high speed two phase MOS clock driver and interface circuit. Unique circuit design provides both very high speed operation
More informationLecture 12 CMOS Delay & Transient Response
EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology
More informationSpiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp
2-7.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 2-7.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 16 CMOS Combinational Circuits - 2 guntzel@inf.ufsc.br
More informationECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model
ECE 34 Electronic Circuits Lecture 35 CMOS Delay Model Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
More informationUniversity of Toronto. Final Exam
University of Toronto Final Exam Date - Apr 18, 011 Duration:.5 hrs ECE334 Digital Electronics Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
More informationand V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationMiscellaneous Lecture topics. Mary Jane Irwin [Adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]
Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] MOS Switches MOS transistors can be viewed as simple switches. In an N-Switch, the
More informationCSE241 VLSI Digital Circuits Winter Lecture 07: Timing II
CSE241 VLSI Digital Circuits Winter 2003 Lecture 07: Timing II CSE241 L3 ASICs.1 Delay Calculation Cell Fall Cap\Tr 0.05 0.2 0.5 0.01 0.02 0.16 0.30 0.5 2.0 0.04 0.32 0.178 0.08 0.64 0.60 1.20 0.1ns 0.147ns
More informationDesignConEast 2005 Track 4: Power and Packaging (4-WA1)
DesignConEast 2005 Track 4: Power and Packaging (4-WA1) Design of a Low-Power Differential Repeater Using Low-Voltage Swing and Charge Recycling Authors: Brock J. LaMeres, University of Colorado / Sunil
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar
More informationSwitched-Capacitor Circuits David Johns and Ken Martin University of Toronto
Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually
More informationIssues on Timing and Clocking
ECE152B TC 1 Issues on Timing and Clocking X Combinational Logic Z... clock clock clock period ECE152B TC 2 Latch and Flip-Flop L CK CK 1 L1 1 L2 2 CK CK CK ECE152B TC 3 Clocking X Combinational Logic...
More informationNTE74HC299 Integrated Circuit TTL High Speed CMOS, 8 Bit Universal Shift Register with 3 State Output
NTE74HC299 Integrated Circuit TTL High Speed CMOS, 8 Bit Universal Shift Register with 3 State Output Description: The NTE74HC299 is an 8 bit shift/storage register with three state bus interface capability
More information5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1
5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design
More informationEEE 421 VLSI Circuits
EEE 421 CMOS Properties Full rail-to-rail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady
More informationEEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture. Rajeevan Amirtharajah University of California, Davis
EEC 216 Lecture #3: Power Estimation, Interconnect, & Architecture Rajeevan Amirtharajah University of California, Davis Outline Announcements Review: PDP, EDP, Intersignal Correlations, Glitching, Top
More informationCMPEN 411 VLSI Digital Circuits Spring Lecture 14: Designing for Low Power
CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 14: Designing for Low Power [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp12 CMPEN
More informationTransmission Line Basics II - Class 6
Transmission Line Basics II - Class 6 Prerequisite Reading assignment: CH2 Acknowledgements: Intel Bus Boot Camp: Michael Leddige Agenda 2 The Transmission Line Concept Transmission line equivalent circuits
More informationCMOS Transistors, Gates, and Wires
CMOS Transistors, Gates, and Wires Should the hardware abstraction layers make today s lecture irrelevant? pplication R P C W / R W C W / 6.375 Complex Digital Systems Christopher atten February 5, 006
More informationLecture 6: DC & Transient Response
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline Pass Transistors DC Response Logic Levels and Noise Margins
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 14 The CMOS Inverter: dynamic behavior (sizing, inverter
More informationEECS 151/251A Spring 2018 Digital Design and Integrated Circuits. Instructors: Nick Weaver & John Wawrzynek. Lecture 12 EE141
EECS 151/251A Spring 2018 Digital Design and Integrated Circuits Instructors: Nick Weaver & John Wawrzynek Lecture 12 1 Wire Models All-inclusive model Capacitance-only 2 Capacitance Capacitance: The Parallel
More informationLecture 6: Time-Dependent Behaviour of Digital Circuits
Lecture 6: Time-Dependent Behaviour of Digital Circuits Two rather different quasi-physical models of an inverter gate were discussed in the previous lecture. The first one was a simple delay model. This
More informationEE141-Spring 2007 Digital Integrated Circuits. Administrative Stuff. Last Lecture. Wires. Interconnect Impact on Chip. The Wire
EE141-Spring 2007 Digital Integrated Circuits ecture 10 Administrative Stuff No ab this week Midterm 1 on Tu! HW5 to be posted by next Friday Due Fr. March 2 5pm Introduction to wires 1 2 ast ecture ast
More informationTransient Response of Transmission Lines and TDR/TDT
Transient Response of Transmission Lines and TDR/TDT Tzong-Lin Wu, Ph.D. EMC Lab. Department of Electrical Engineering National Sun Yat-sen University Outlines Why do we learn the transient response of
More informationTopics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance
More information