Circuit A. Circuit B

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1 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on November 19, 2006 by Karl Skucha Borivoje Nikolić Homework #9 EE 141 Problem #1: Power in CMOS A B G1 G2 C G3 G4 D G5 G6 50 ff Circuit A A B C G1 G2 D 50 ff Circuit B Let s evaluate the effect of logic choice on power dissipation. Circuit A is an AND4 implemented as a NAND2 chain while Circuit B implements the same function using a 4 input gate. a) Size circuit A and circuit B for minimum delay with Cin of 3fF and Cout of 50fF. Report your answer in terms of the input capacitance seen at each gate. Circuit A H=50/3 * (4/3) 3 =39.51 h=h 1/6 =1.845 G1 G2 G3 G4 G5 G6 3fF 4.15fF 7.66fF 10.60fF 19.55fF 27.06fF

2 Circuit B H=50/3 * (6/3) = H=H 1/2 =5.77 G1=3fF G2=8.66fF b) Given that P(A=1) = P(B=1) = P(C=0) = P(D=0) = 0.25, calculate the probability of energy consuming transitions P(0 1) at the outputs of the gates in both circuits. Circuit A P(0 1) = P(0) * P(1) = (1-P(0)) * P(0) In1 In2 Out 0 (x) 0 (y) 1 (xy) 0 (x) 1 (1-y) 1 (x-xy) 1 (1-x) 0 (y) 1 (y-xy) 1 (1-x) 1 (1-y) 0 (1-y-x+xy) NAND2 Truth Table with Probabilities P(0) = 1-y-x+xy P(1) = x+y-xy For G1, P(In1=0) =.75 and P(In2=0) =.75 so P(0) =.0625 For G2, P(0) =.9375 For G3, P(In1=0) = P(G2=0) =.9375, while P(In2=0) = P(C=0)=.25. Therefore P(G3=0) =.0469 For G4, P(0) =.9531 For G5, P(In1=0) = P(G4=0) =.9531, while P(In2=0) = P(D=0)=.25. Therefore P(G5=0) =.0352 For G6, P(0) =.9648 G1 G2 G3 G4 G5 G6 P(0) P(0 1)

3 Circuit B P(NAND4=0) = P(In1=1, In2=1, In3=1, In4=1) = 3/4 2 *1/4 2 = G1 G2 P(0) P(0 1) c) Assuming both circuits are operating at 1 GHz, calculate the dynamic power consumption of the circuit. Assume γ = 1, Vdd = 2.5V, and only consider capacitances at the inputs and output of the gates. Circuit A At primary inputs, P(0 1)=1/4*3/4=3/16 For a NAND2 gate, the capacitance at the output node is 6 γ /4 times bigger than the capacitance at the gate. There are 2 2x PMOS and 1 2x NMOS devices at the output node while the capacitance at each input is 4 units. That gives us 6/4. We need to add gamma to skew it for the technology. A quick way to figure it out is pγ /g for simpler logic gates like NAND s NOR s. It might not be accurate for AOI (and-or-invert) since the topology is not unique. P dyn = V dd 2 f ((2* )fF*3/16 + (4.15+3*3γ/2)fF*α G1 + ( γ)fF*α G2 + ( *3γ/2)fF*α G3 + ( γ)fF*α G4 + ( *3γ/2)fF*α G5 + ( γ)fF*α G6 ) = = 89.37µW Circuit B For a NAND4 gate, the capacitance at the output node is 12 γ/6. P dyn = V dd 2 f (4*3fF*3/16 + (3*12 γ/6+8.66)ff*α G1 + ( )fF*α G2 ) = = 29.65µW Shorter logic depth reduces power consumption. Problem #2: Schmitt Trigger The circuit on the following page is a pseudo-nmos Schmitt trigger. Assume that the PMOS transistor remains in saturation over entire range of operation. Vdd = 1.5V, Vtn = Vtp = 0.4V, kn =115uA/V 2, kp=30ua/v 2

4 a) Compute V OH and V OL. b) Compute the switching points V M+ (for input making low-to-high transition) and V M- (for the input making a high-to-low transition).

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6 c) Sketch the VTC. Compare results with SPICE simulations. In particular, you should obtain different VTC curves for high-to-low transitions and low-to-high transitions. Perform a transient analysis with the following as input:- Vtest vin 0 PWL n 0 100n Vdd 150n Vdd 200n 0

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8 Problem #3: Pulse-triggered latch X Clkd Figure above shows a practical implementation of a pulse-triggered latch. Clock Clk is ideal with 50% duty cycle. Data : t p,inv = 200ps, Clkd = 10fF, Cx = 10fF, CQ = CQ = 20fF a) Draw the waveforms at nodes Clk, Clkd, X and Q for two clock cycles, with D equals 0 in one cycle and 1 in the other. b) Are the setup and hold times positive, negative, or approximately zero? T setup is negative. D can switch slightly after the clock switches because switching delay to pull down node X will be significantly less that 600ps (many of your full-blown decoders had delays less than this)

9 T hold is positive. D needs to be held stable for a correct value to settle at node X and node Q. c) If the probability that D will change its logic value in one clock cycle is α, with equal probability of being 0 or 1, what is the power consumption of this circuit? (excluding the power consumption in the clock line) Assume fclk = 100 MHz. P = CV dd 2 f 0 1 = C x V dd 2 f clk (0.5) + (C Q + C Q ) V dd 2 f clk (0.5)α+ C clkb V dd 2 f clk = 10 f V dd 2 (100 M)(0.5) + (20 f +20 f) V dd 2 (100 M)(0.5)( α)+(10 f ) V dd 2 (100 M) P= (1.5 V dd αv dd 2 ) µw