ESE 570: Digital Integrated Circuits and VLSI Fundamentals


 Blaise Ford
 2 years ago
 Views:
Transcription
1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 17: March 23, 2017 Energy and Power Optimization, Design Space Exploration, Synchronous MOS Logic
2 Lecture Outline! Energy and Power Optimization " Tradeoffs! Design Space Exploration " Design Problem Example: Match Circuit 2
3 Total Power! P tot = P static + P sc + P dyn! P sw = P dyn + P sc = a(c load V 2 f) + C sc V 2 f! P tot a(c load V 2 f) + C sc V 2 f + VI s (W/L)eVt/(nkT/q)! Let a = activity factor a = average #tran 0#1 /clock 3
4 Energy and Power Optimization
5 Power Sources Review: P tot = P static + P dyn + P sc
6 Worksheet Problem 1 V in I static I dynamic I sc 0V 140mV 400mV 500mV 600mV 860mV 1V 6
7 Worksheet Problem 1 V in I static I dynamic I sc 0V 180pA 126uA 140mV 6nA 100uA 400mV 36uA 18uA 500mV 36uA 600mV 36uA 18uA 860mV 6nA 100uA 1V 180pA 126uA 7
8 Energy and Power Optimization
9 Reminder: Worksheet Problem 1 V in I static I dynamic I sc 0V 180pA 126uA 140mV 6nA 100uA 400mV 36uA 18uA 500mV 36uA 600mV 36uA 18uA 860mV 6nA 100uA 1V 180pA 126uA 9
10 Reduce V dd (Worksheet #2)! V dd =520mV, V thn = V thp =300mV V in I static I dynamic I sc 0V 140mV 260mV 360mV 500mV 10
11 Reduce V dd (Worksheet #2)! V dd =520mV, V thn = V thp =300mV V in I static I dynamic I sc 0V 180pA 39.6uA 140mV 6nA 14.4uA 260mV 111nA 360mV 6nA 10.8uA 500mV 180pA 36uA 11
12 Design Tradeoffs
13 Reduce V dd! What happens as reduce V? " Energy? " Static " Switching " Delay? 13
14 Reduce V dd :! τ gd =Q/I=(CV)/I! I d =(µc OX /2)(W/L)(V gs V TH ) 2! τ gd impact?! τ gd 1 V 14
15 Reduce V dd :! τ gd =Q/I=(CV)/I! I d =(µc OX /2)(W/L)(V gs V TH ) 2! τ gd impact?! τ gd 1 V! Ignoring leakage: E V 2 Eτ 2 Const 15
16 Reduce V dd (Worksheet #3)! V thn = V thp =300mV, V in =V dd, estimate Eτ V dd I ds dd =1) E switch / (E dd =1) Eτ 1V 700mV 500mV 350mV 260mV 16
17 Reduce V dd (Worksheet #3)! V thn = V thp =300mV, V in =V dd, estimate Eτ V dd I ds dd =1) E switch / (E dd =1) Eτ 1V 126uA mV 72uA mV 36uA mV 9uA mV 111nA
18 Reduce ShortCircuit Power?! P sc = ac sc V 2 f # # E = V dd I peak t sc % 1& & % (( $ $ 2' ' Vin VddVthp Vthn time Vdd Vdd Isc Vout tsc tsc time 18
19 Increase V th (Worksheet #4)! What is impact of increasing threshold on " Delay? " Leakage?! V dd =1V, V in =V dd V thn = V thp I ds th =300mV) I static (I th =300mV) I stat / 300mV 460mV 600mV 19
20 Increase V th (Worksheet #4)! What is impact of increasing threshold on " Delay? " Leakage?! V dd =1V, V in =V dd V thn = V thp I ds th =300mV) I static (I th =300mV) I stat / 300mV 126uA 1 180pA 1 460mV 97uA pA mV 72uA fA
21 Idea! Tradeoff " Speed " Switching energy " Leakage energy! EnergyDelay tradeoff: Eτ 2 21
22 Design Space Exploration 22
23 Design Problem! Function: Identify equivalence of two 32bit inputs! Optimize: Minimize total energy! Assumptions: Match case uncommon " Ie. Most of the time, the inputs won t be matched! Deliberately focus on Energy to complement project " but will still talk about delay 23
24 Idea: Design Space Explore! Identify options " All the knobs you can turn! Explore space systematically! Formulate continuum where possible " i.e. formulate trends 24
25 Problem Solvable! Is it feasible? " First, make sure we have a solution so we know our main goal is optimization! How do we decompose the problem? 25
26 Problem Solvable! Is it feasible? " First, make sure we have a solution so we know our main goal is optimization! How do we decompose the problem?! What look like built out of nand2 gates and inverters? 26
27 Total Power! Static CMOS: " P tot a(½c load +C sc )V 2 f+vi s (W/L)eVt/(nkT/q)! What can we do to reduce power? 27
28 Knobs! What are the options and knobs we can turn? 28
29 Design Space Dimensions! Vdd! Topology " Gate choice, logical optimization " Fanin, fanout, Serial vs. parallel! Gate style / logic family " CMOS, Ratioed (N load, P load)! Transistor Sizing! Vth! The choices you make impact area, speed (delay), power 29
30 How Reduce ShortCircuit Power?! P sc = ac sc V 2 f # # E = V I t % 1& & dd % ( peak sc ( $ $ 2' ' 30
31 Gate! What gates might we build?! High fanin?! SerialParallel? 31
32 Logic Family! Considerations for each logic family? " CMOS " Ratioed with PMOS load " Ratioed with NMOS load 32
33 Sizing! How do we want to size gates? 33
34 Reduce Vdd! What happens as reduce V? " Energy? " Dynamic " Static " Switching Delay?! How low can we push Vdd? 34
35 Reduce V dd $ τ gd =Q/I=(CV)/I $ I d =(µc OX /2)(W/L)(V gs V TH ) 2 $ τ gd impact? $ τ gd α 1/V 35
36 Increase V th?! What is impact of increasing threshold on " Dynamic Energy? " Leakage Energy? " Delay? 36
37 Design Problem! Function: Identify equivalence of two 32bit inputs! Optimize: Minimize total energy! Assumptions: Match case uncommon " Ie. Most of the time, the inputs won t be matched! Deliberately focus on Energy to complement project " but will still talk about delay 37
38 Design Space Dimensions! Vdd! Topology " Gate choice, logical optimization " Fanin, fanout, Serial vs. parallel! Gate style / logic family " CMOS, Ratioed (N load, P load)! Transistor Sizing! Vth! The choices you make impact area, speed (delay), power 38
39 Ideas! Three components of power " P tot = P static + P dyn + P sc! We know many things we can do to our circuits! Design space is large! Systematically identify dimensions! Identify continuum (trends) tuning when possible! Watch tradeoffs " don t overtune 39
40 Sequential MOS Logic
41 Classes of Logic Circuits two stable op. pts. Latch level triggered. FlipFlop edge triggered. one stable op. pt. Oneshot single pulse output no stable op. pt. Ring Oscillator Combinational Circuits: a. Current Output(s) depend ONLY on Current Inputs. b. Suited to problems that can be solved using truth tables. Sequential Circuits or State Machines: a. Current Output(s) depend on Current Inputs and Past Inputs via State(s). b. Suited to problems that are solved by completing several steps using current inputs and past outputs in a specific order or a sequential manner. 41
42 Functions Using Sequential Operations 42
43 Sequential Circuit (or State Machine) Construct Inputs Outputs V o1 Vo2.... V o3 Present State > Register is used to Store Past Values of State(s) and Output(s) > Synchronous Sequential Circuit clock, outputs change with clock event > Asynchronous Sequential Circuit no clock, outputs change after inputs change REGISTER.... Next State Clock 43
44 Static Bistable Sequential Circuits Basic Crosscoupled Inverter pair Q Q 44
45 Static Bistable Sequential Circuits Basic Crosscoupled Inverter pair Q Q 45
46 Static Bistable Sequential Circuits Basic Crosscoupled Inverter pair Q Q 46
47 Static Bistable Sequential Circuits Basic Crosscoupled Inverter pair Q V OH = V DD Q V OL = 0 maintain stable state. STATIC: V DD and GND are required to maintain a stable state. Basic Bistable Crosscoupled Inverter Pair has no means to apply input(s) to change the circuit's State. 47
48 Basic Sequential Circuits (Cells)! Latches! Registers 48
49 Latch! Levelsensitive device! Positive Latch " Output follows input if CLK high! Negative Latch " Output follows input if CLK low Q = CLK Q + CLK In 49
50 Register! Edgetriggered storage element! Positive edgetriggered " Input sampled on rising CLK edge! Negative edgetriggered " Input sampled on falling CLK edge 50
51 Shift Register! How do you make a shift register out of latches? 51
52 Two Phase NonOverlapping Clocks! Build masterslave register from pair of latches! Control with nonoverlapping clocks 52
53 Two Phase NonOverlapping Clocks! Build masterslave register from pair of latches! Control with nonoverlapping clocks 53
54 Two Phase NonOverlapping Clocks! Build masterslave register from pair of latches! Control with nonoverlapping clocks 54
55 Two Phase NonOverlapping Clocks! What could go wrong if the overlap? 55
56 Clocking Discipline! Follow discipline of combinational logic broken by registers! Compute " From state elements " Through combinational logic " To new values for state elements! As long as clock cycle long enough, " Will get correct behavior 56
57 CMOS SR Latch NOR2 * * 57
58 CMOS SR Latch NOR2 basic crosscoupled inverter pair 58
59 CMOS SR Latch NOR2 basic crosscoupled inverter pair 59
60 CMOS SR Latch NOR2 SET OP: S = 1, R = 0 basic crosscoupled inverter pair 60
61 CMOS SR Latch NOR2 RESET OP: R = 1, S = 0 basic crosscoupled inverter pair 61
62 CMOS SR Latch NOR2 HOLD OP: S = 0, R = 0 basic crosscoupled inverter pair 62
63 CMOS SR Latch NOR2 HOLD OP: S = 0, R = 0 basic crosscoupled inverter pair 63
64 CMOS SR Latch NOR2 ACTIVE HIGH * * 64
65 CMOS SR Latch NAND2 basic crosscoupled inverter pair 65
66 CMOS SR Latch NAND2 ACTIVE LOW * * * * 66
67 Synchronous Latches NAND SR SR Latch LATCH NOTE: S and R are asynchronous. S/R S /R' CK 67
68 Synchronous Latches NAND SR SR Latch LATCH NOTE: S and R are asynchronous. S/R S /R' CK SET STATE: CK = 1, S = 1, R = 0 => S' = 0, R' = 1 => Q n+1 = 1, Q n+1 = 0 RESET STATE: CK = 1, S = 0, R = 1 => S' = 1, R' = 0 => Q n+1 = 0, Q n+1 = 1 NOT ALLOWED: CK = 1, S = 1, R = 1 => S' = 0, R' = 0 IS CK = 1, S = 0, R = 0 a HOLD STATE? 68
69 Synchronous Latches HOLD STATE: CK = 1, S = 0, R = 0 T glitch Q error due to glitch on S R 69
70 Latch! Levelsensitive device! Positive Latch " Output follows input if CLK high! Negative Latch " Output follows input if CLK low Q = CLK Q + CLK In 70
71 Static CMOS DLatch S If CK = 1 R LATCH If CK = 0, HOLD 71
72 Static CMOS DLatch S If CK = 1 R LATCH If CK = 0, HOLD 18 Transistors CK D S' R' Q n+1 Q n SRSet SRReset 0 x 0 0 Q n Q n SRHold + NO TOGGLE + NO NOTALLOWED INPUTS 72
73 Static CMOS TG DLATCH 8 Transistors 8 Transistors **Transistor level implementation using transmission gates requires fewer transistors 73
74 Static CMOS TG DLATCH CK D CK Q CK Q CK 74
75 Static CMOS TG DLATCH When CK = 1 output Q = D, and tracks D until CK = 0, the DLatch is referred to positive level triggered. When CK 1 to 0, the Q = D is captured, held (or stored) in the Latch. 75
76 DLATCH Timing Requirements 76
77 Ideas! Synchronize circuits " to external events (eg. Clk) " disciplined reuse of circuitry! Leads to clocked circuit discipline " Uses state holding element (eg. Latches and registers) " Prevents " Timing assumptions " (More) complex reasoning about all possible timings 77
78 Admin! HW 6 due midnight 78
Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Total Power. Energy and Power Optimization. Worksheet Problem 1
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 20, 2018 Energy and Power Optimization, Design Space Exploration Lecture Outline! Energy and Power Optimization " Tradeoffs! Design
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 17: March 26, 2019 Energy Optimization & Design Space Exploration Penn ESE 570 Spring 2019 Khanna Lecture Outline! Energy Optimization! Design
More information! Energy Optimization. ! Design Space Exploration. " Example. ! P tot P static + P dyn + P sc. ! SteadyState: V in =V dd. " PMOS: subthreshold
ESE 570: igital Integrated ircuits and VLSI undamentals Lec 17: March 26, 2019 Energy Optimization & esign Space Exploration Lecture Outline! Energy Optimization! esign Space Exploration " Example 3 Energy
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler
More informationMidterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 18: March 27, 2018 Dynamic Logic, Charge Injection Lecture Outline! Sequential MOS Logic " DLatch " Timing Constraints! Dynamic Logic " Domino
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 15, 2018 MOS Inverter: Dynamic Characteristics Penn ESE 570 Spring 2018 Khanna Lecture Outline! Inverter Power! Dynamic Characteristics
More informationHold Time Illustrations
Hold Time Illustrations EE213L09Sequential Logic.1 Pingqiang, ShanghaiTech, 2018 Hold Time Illustrations EE213L09Sequential Logic.2 Pingqiang, ShanghaiTech, 2018 Hold Time Illustrations EE213L09Sequential
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Restore Output. Pass Transistor Logic. How compare.
ESE 570: igital Integrated ircuits and VLSI undamentals Lec 16: March 19, 2019 Euler Paths and Energy asics & Optimization Lecture Outline! Pass Transistor Logic! Logic omparison! Transmission Gates! Euler
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Designing Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL
More informationName: Answers. Mean: 83, Standard Deviation: 12 Q1 Q2 Q3 Q4 Q5 Q6 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering CircuitLevel Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Final Tuesday, December 15 Problem weightings
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 18 CMOS Sequential Circuits  1 guntzel@inf.ufsc.br
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics. Ho Kyung Kim, Ph.D.
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Digital IC packages TTL (transistortransistor
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: CMOS Inverter: Visual VTC. Review: CMOS Inverter: Visual VTC
ESE 570: Digital Integrated Circuits and LSI Fundamentals Lec 0: February 4, 207 MOS Inverter: Dynamic Characteristics Lecture Outline! Review: Symmetric CMOS Inverter Design! Inverter Power! Dynamic Characteristics
More informationJan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. November Digital Integrated Circuits 2nd Sequential Circuits
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic esigning i Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL
More informationGMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI esign Chapter IV esigning Sequential Logic Circuits (Chapter 7) 1 Sequential Logic Inputs Current State COMBINATIONAL LOGIC Registers Outputs Next state 2 storage mechanisms positive
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI esign Chapter IV esigning Sequential Logic Circuits (Chapter 7) 1 Sequential Logic Inputs Current State COMBINATIONAL LOGIC Registers Outputs Next state 2 storage mechanisms positive
More informationDigital Integrated Circuits A Design Perspective
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic esigning Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL LOGIC
More informationTopics. Dynamic CMOS Sequential Design Memory and Control. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics Dynamic CMOS Sequential Design Memory and Control Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance
More information! Inverter Power. ! Dynamic Characteristics. " Delay ! P = I V. ! Tricky part: " Understanding I. " (pairing with correct V) ! Dynamic current flow:
ESE 570: Digital Integrated ircuits and LSI Fundamentals Lecture Outline! Inverter Power! Dynamic haracteristics Lec 10: February 15, 2018 MOS Inverter: Dynamic haracteristics " Delay 3 Power Inverter
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2016 Final Friday, May 6 5 Problems with point weightings shown.
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.
More informationTopics. CMOS Design Multiinput delay analysis. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
Topics CMO Design Multiinput delay analysis pring 25 Transmission Gate OUT Z OUT Z pring 25 Transmission Gate OUT When is low, the output is at high impedance When is high, the output follows However,
More informationDigital Integrated Circuits A Design Perspective
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic esigning Sequential Logic Circuits November 2002 Naming Conventions In our text: a latch is level sensitive
More informationLOGIC CIRCUITS. Basic Experiment and Design of Electronics
Basic Experiment and Design of Electronics LOGIC CIRCUITS Ho Kyung Kim, Ph.D. hokyung@pusan.ac.kr School of Mechanical Engineering Pusan National University Outline Combinational logic circuits Output
More informationTopic 8: Sequential Circuits
Topic 8: Sequential Circuits Readings : Patterson & Hennesy, Appendix B.4  B.6 Goals Basic Principles behind Memory Elements Clocks Applications of sequential circuits Introduction to the concept of the
More informationUniversity of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering
University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering Final Examination ECE 241F  Digital Systems Examiners: J. Rose and
More informationCMPEN 411. Spring Lecture 18: Static Sequential Circuits
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 18: Static Sequential Circuits [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11
More informationLecture 9: Sequential Logic Circuits. Reading: CH 7
Lecture 9: Sequential Logic Circuits Reading: CH 7 Sequential Logic FSM (Finitestate machine) Inputs Current State COMBINATIONAL LOGIC Registers Outputs = f(current, inputs) Next state 2 storage mechanisms
More informationMODULE 5 Chapter 7. Clocked Storage Elements
MODULE 5 Chapter 7 Clocked Storage Elements 3/9/2015 1 Outline Background Clocked Storage Elements Timing, terminology, classification Static CSEs Latches Registers Dynamic CSEs Latches Registers 3/9/2015
More informationEE241  Spring 2000 Advanced Digital Integrated Circuits. Announcements
EE241  Spring 2 Advanced Digital Integrated Circuits Lecture 11 Low PowerLow Energy Circuit Design Announcements Homework #2 due Friday, 3/3 by 5pm Midterm project reports due in two weeks  3/7 by 5pm
More informationECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 7 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering SEQUENTIAL CIRCUITS: LATCHES Overview Circuits require memory to store intermediate
More informationSequential vs. Combinational
Sequential Circuits Sequential vs. Combinational Combinational Logic: Output depends only on current input TV channel selector (9) inputs system outputs Sequential Logic: Output depends not only on current
More informationChapter 13. Clocked Circuits SEQUENTIAL VS. COMBINATIONAL CMOS TG LATCHES, FLIP FLOPS. Baker Ch. 13 Clocked Circuits. Introduction to VLSI
Chapter 13 Clocked Circuits SEQUENTIAL VS. COMBINATIONAL CMOS TG LATCHES, FLIP FLOPS SETRESET (SR) ARBITER LATCHES FLIP FLOPS EDGE TRIGGERED DFF FF TIMING Joseph A. Elias, Ph.D. Adjunct Professor, University
More informationSynchronous Sequential Logic
1 IT 201 DIGITAL SYSTEMS DESIGN MODULE4 NOTES Synchronous Sequential Logic Sequential Circuits  A sequential circuit consists of a combinational circuit and a feedback through the storage elements in
More informationSpiral 2 7. Capacitance, Delay and Sizing. Mark Redekopp
27.1 Spiral 2 7 Capacitance, Delay and Sizing Mark Redekopp 27.2 Learning Outcomes I understand the sources of capacitance in CMOS circuits I understand how delay scales with resistance, capacitance
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2018 Final Monday, Apr 0 5 Problems with point weightings shown.
More informationLecture 81. Low Power Design
Lecture 8 Konstantinos Masselos Department of Electrical & Electronic Engineering Imperial College London URL: http://cas.ee.ic.ac.uk/~kostas Email: k.masselos@ic.ac.uk Lecture 81 Based on slides/material
More informationUNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER /2017
UNIVERSITY OF BOLTON TW35 SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING EXAMINATION SEMESTER 22016/2017 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationHomework Assignment #1 Solutions EE 477 Spring 2017 Professor Parker
Homework Assignment #1 Solutions EE 477 Spring 2017 Professor Parker Note: + implies OR,. implies AND, ~ implies NOT Question 1: a) (4%) Use transmission gates to design a 3input OR gate Note: There are
More informationChapter 7 Sequential Logic
Chapter 7 Sequential Logic SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,eizam@utm.my,ismahani@fke.utm.my} March 28, 2016 Table of Contents 1 Intro 2 Bistable Circuits 3 FF Characteristics
More informationUniversity of Toronto. Final Exam
University of Toronto Final Exam Date  Apr 18, 011 Duration:.5 hrs ECE334 Digital Electronics Lecturer  D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
More informationLecture 5. MOS Inverter: Switching Characteristics and Interconnection Effects
Lecture 5 MOS Inverter: Switching Characteristics and Interconnection Effects Introduction C load = (C gd,n + C gd,p + C db,n + C db,p ) + (C int + C g ) Lumped linear capacitance intrinsic cap. extrinsic
More informationClock Strategy. VLSI System Design NCKUEEKJLEE
Clock Strategy Clocked Systems Latch and Flipflops System timing Clock skew High speed latch design Phase locked loop ynamic logic Multiple phase Clock distribution Clocked Systems Most VLSI systems are
More informationLecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: 1st Order RC Delay Models. Review: TwoInput NOR Gate (NOR2)
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 14: March 1, 2016 Combination Logic: Ratioed and Pass Logic Lecture Outline! CMOS Gates Review " CMOS Worst Case Analysis! Ratioed Logic Gates!
More informationLecture 14: State Tables, Diagrams, Latches, and Flip Flop
EE210: Switching Systems Lecture 14: State Tables, Diagrams, Latches, and Flip Flop Prof. YingLi Tian Nov. 6, 2017 Department of Electrical Engineering The City College of New York The City University
More informationEET 310 FlipFlops 11/17/2011 1
EET 310 FlipFlops 11/17/2011 1 FF s and some Definitions Clock Input: FF s are controlled by a trigger or Clock signal. All FF s have a clock input. If a device which attempts to do a FF s task does not
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 16, 2016 MOS Inverter: Dynamic Characteristics Lecture Outline! Review: Symmetric CMOS Inverter Design! Inverter Power! Dynamic
More informationELEC Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 710)
ELEC 2200002 Digital Logic Circuits Fall 2014 Sequential Circuits (Chapter 6) Finite State Machines (Ch. 710) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: March 29, 2018 Memory Overview, Memory Core Cells Today! Charge Leakage/Charge Sharing " Domino Logic Design Considerations! Logic Comparisons!
More informationComputers also need devices capable of Storing data and information Performing mathematical operations on such data
Sequential Machines Introduction Logic devices examined so far Combinational Output function of input only Output valid as long as input true Change input change output Computers also need devices capable
More informationSequential Logic. Rab Nawaz Khan Jadoon DCS. Lecturer COMSATS Lahore Pakistan. Department of Computer Science
Sequential Logic Rab Nawaz Khan Jadoon DCS COMSATS Institute of Information Technology Lecturer COMSATS Lahore Pakistan Digital Logic and Computer Design Sequential Logic Combinational circuits with memory
More informationVidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution
. (a) (i) ( B C 5) H (A 2 B D) H S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution ( B C 5) H (A 2 B D) H = (FFFF 698) H (ii) (2.3) 4 + (22.3) 4 2 2. 3 2. 3 2 3. 2 (2.3)
More informationTopic 8: Sequential Circuits. Bistable Devices. SR Latches. Consider the following element. Readings : Patterson & Hennesy, Appendix B.4  B.
Topic 8: Sequential Circuits Bistable Devices Readings : Consider the following element Patterson & Hennesy, Appendix B.4  B.6 Goals Basic Principles behind Memory Elements Clocks Applications of sequential
More informationEE 434 Lecture 33. Logic Design
EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The twoinverter loop X Y X
More informationCircuit A. Circuit B
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Last modified on November 19, 2006 by Karl Skucha (kskucha@eecs) Borivoje Nikolić Homework #9
More informationF14 Memory Circuits. Lars Ohlsson
Lars Ohlsson 20181018 F14 Memory Circuits Outline Combinatorial vs. sequential logic circuits Analogue multivibrator circuits Noise in digital circuits CMOS latch CMOS SR flip flop 6T SRAM cell 1T DRAM
More informationLecture 3 Review on Digital Logic (Part 2)
Lecture 3 Review on Digital Logic (Part 2) Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ ircuit Optimization Simplest implementation ost criterion literal
More informationLecture 5. Logical Effort Using LE on a Decoder
Lecture 5 Logical Effort Using LE on a Decoder Mark Horowitz Computer Systems Laboratory Stanford University horowitz@stanford.edu Copyright 00 by Mark Horowitz Overview Reading Harris, Logical Effort
More information! Charge Leakage/Charge Sharing. " Domino Logic Design Considerations. ! Logic Comparisons. ! Memory. " Classification. " ROM Memories.
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 9, 8 Memory Overview, Memory Core Cells Today! Charge Leakage/ " Domino Logic Design Considerations! Logic Comparisons! Memory " Classification
More informationEECS 312: Digital Integrated Circuits Midterm Exam 2 December 2010
Signature: EECS 312: Digital Integrated Circuits Midterm Exam 2 December 2010 obert Dick Show your work. Derivations are required for credit; end results are insufficient. Closed book. No electronic mental
More informationUnit 7 Sequential Circuits (Flip Flop, Registers)
College of Computer and Information Sciences Department of Computer Science CSC 220: Computer Organization Unit 7 Sequential Circuits (Flip Flop, Registers) 2 SR FlipFlop The SR flipflop, also known
More informationUniversity of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS151/251A V. Stojanovic, J. Wawrzynek Fall 2015 10/13/15 Midterm Exam Name: ID
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 8: February 9, 016 MOS Inverter: Static Characteristics Lecture Outline! Voltage Transfer Characteristic (VTC) " Static Discipline Noise Margins!
More informationLecture 7: Logic design. Combinational logic circuits
/24/28 Lecture 7: Logic design Binary digital circuits: Two voltage levels: and (ground and supply voltage) Built from transistors used as on/off switches Analog circuits not very suitable for generic
More informationIntroduction to Computer Engineering. CS/ECE 252, Fall 2012 Prof. Guri Sohi Computer Sciences Department University of Wisconsin Madison
Introduction to Computer Engineering CS/ECE 252, Fall 2012 Prof. Guri Sohi Computer Sciences Department University of Wisconsin Madison Chapter 3 Digital Logic Structures Slides based on set prepared by
More informationVidyalankar S.E. Sem. III [ETRX] Digital Circuits and Design Prelim Question Paper Solution
S.E. Sem. III [ETRX] Digital Circuits and Design Prelim uestion Paper Solution. (a) Static Hazard Static hazards have two cases: static and static. static hazard exists when the output variable should
More informationName: Grade: Q1 Q2 Q3 Q4 Q5 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering CircuitLevel Modeling, Design, and Optimization for Digital Systems ESE370, Fall 205 Midterm Wednesday, November 4 Point values
More informationEE371  Advanced VLSI Circuit Design
EE371  Advanced VLSI Circuit Design Midterm Examination May 7, 2002 Name: No. Points Score 1. 18 2. 22 3. 30 TOTAL / 70 In recognition of and in the spirit of the Stanford University Honor Code, I certify
More informationECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN. Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Week 9 Dr. Srinivas Shakkottai Dept. of Electrical and Computer Engineering TIMING ANALYSIS Overview Circuits do not respond instantaneously to input changes
More informationMAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI
DEPARTMENT: ECE MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI 6 QUESTION BANK SUBJECT NAME: DIGITAL ELECTRONICS UNIT : Design of Sequential Circuits PART A ( Marks). Draw the logic diagram 4: Multiplexer.(AUC
More informationGates and FlipFlops
Gates and FlipFlops Chris Kervick (11355511) With Evan Sheridan and Tom Power December 2012 On a scale of 1 to 10, how likely is it that this question is using binary?...4? What s a 4? Abstract The operation
More informationSequential Logic Circuits
Chapter 4 Sequential Logic Circuits 4 1 The defining characteristic of a combinational circuit is that its output depends only on the current inputs applied to the circuit. The output of a sequential circuit,
More informationCMPEN 411 VLSI Digital Circuits Spring Lecture 14: Designing for Low Power
CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 14: Designing for Low Power [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp12 CMPEN
More informationEE141 Spring 2007 Digital Integrated Circuits
EE141 Spring 27 igital Integrated Circuits Lecture 19 Sequential Circuits 1 Administrative Stuff Project Ph. 2 due Tu. 5pm 24 Cory box + email ee141 project@bwrc.eecs.berkeley.edu Hw 8 Posts this Fr.,
More informationDigital Logic: Boolean Algebra and Gates. Textbook Chapter 3
Digital Logic: Boolean Algebra and Gates Textbook Chapter 3 Basic Logic Gates XOR CMPE12 Summer 2009 022 Truth Table The most basic representation of a logic function Lists the output for all possible
More informationDigital Integrated Circuits A Design Perspective
Digital Integrated Circuits Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC Dynamic Logic Introduction Digital IC 2 EE141 Dynamic
More informationLecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010
EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng 6.1 Outline Power and Energy Dynamic Power Static Power 6.2 Power and Energy Power is drawn from a voltage source attached to the V DD
More informationMODULE III PHYSICAL DESIGN ISSUES
VLSI Digital Design MODULE III PHYSICAL DESIGN ISSUES 3.2 Powersupply and clock distribution EE  VDD P2006 3:1 3.1.1 Power dissipation in CMOS gates Power dissipation importance Package Cost. Power
More informationDigital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo
Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Dynamic Logic Introduction Digital IC EE141 2 Dynamic logic outline Dynamic logic principle Dynamic logic
More informationLecture 320 Improved OpenLoop Comparators and Latches (3/28/10) Page 3201
Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 321 LECTURE 32 IMPROVED OPENLOOP COMPARATORS AND LATCHES LECTURE ORGANIZATION Outline Autozeroing Hysteresis Simple es Summary CMOS Analog
More informationEE40 Lec 15. Logic Synthesis and Sequential Logic Circuits
EE40 Lec 15 Logic Synthesis and Sequential Logic Circuits Prof. Nathan Cheung 10/20/2009 Reading: Hambley Chapters 7.47.6 Karnaugh Maps: Read following before reading textbook http://www.facstaff.bucknell.edu/mastascu/elessonshtml/logic/logic3.html
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified)
WINTER 17 EXAMINATION Subject Name: Digital Techniques Model Answer Subject Code: 17333 Important Instructions to examiners: 1) The answers should be examined by key words and not as wordtoword as given
More informationon candidate s understanding. 7) For programming language papers, credit may be given to any other program based on equivalent concept.
WINTER 17 EXAMINATION Subject Name: Digital Techniques Model Answer Subject Code: 17333 Important Instructions to examiners: 1) The answers should be examined by key words and not as wordtoword as given
More informationΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018
ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018 ΔΙΑΛΕΞΕΙΣ 1213: esigning ynamic and Static CMOS Sequential Circuits ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ttheocharides@ucy.ac.cy) (ack: Prof. Mary Jane Irwin and
More informationMOSFET and CMOS Gate. Copy Right by Wentai Liu
MOSFET and CMOS Gate CMOS Inverter DC Analysis  Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max
More informationChapter 5 CMOS Logic Gate Design
Chapter 5 CMOS Logic Gate Design Section 5. To achieve correct operation of integrated logic gates, we need to satisfy 1. Functional specification. Temporal (timing) constraint. (1) In CMOS, incorrect
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NORgate C = NOT (A or B)
1 Introduction to TransistorLevel Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More informationEEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this
More informationC.K. Ken Yang UCLA Courtesy of MAH EE 215B
Decoders: Logical Effort Applied C.K. Ken Yang UCLA yang@ee.ucla.edu Courtesy of MAH 1 Overview Reading Rabaey 6.2.2 (Ratioed logic) W&H 6.2.2 Overview We have now gone through the basics of decoders,
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 111:3 Thursday, October 6, 6:38:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationL4: Sequential Building Blocks (Flipflops, Latches and Registers)
L4: Sequential Building Blocks (Flipflops, Latches and Registers) Acknowledgements:., Materials in this lecture are courtesy of the following people and used with permission.  Randy H. Katz (University
More informationCOMBINATIONAL LOGIC. Combinational Logic
COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino npcmos Combinational vs. Sequential Logic In Logic
More informationCSE140: Components and Design Techniques for Digital Systems. Midterm Information. Instructor: Mohsen Imani. Sources: TSR, Katz, Boriello & Vahid
CSE140: Components and Design Techniques for Digital Systems Midterm Information Instructor: Mohsen Imani Midterm Topics In general: everything that was covered in homework 1 and 2 and related lectures,
More informationObjective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components
Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the
More informationUnit II Chapter 4: Digital Logic Contents 4.1 Introduction... 4
Unit II Chapter 4: Digital Logic Contents 4.1 Introduction... 4 4.1.1 Signal... 4 4.1.2 Comparison of Analog and Digital Signal... 7 4.2 Number Systems... 7 4.2.1 Decimal Number System... 7 4.2.2 Binary
More informationDesign of Analog Integrated Circuits
Design of Analog Integrated Circuits Chapter 11: Introduction to Switched Capacitor Circuits Textbook Chapter 13 13.1 General Considerations 13.2 Sampling Switches 13.3 SwitchedCapacitor Amplifiers 13.4
More information