# ESE 570: Digital Integrated Circuits and VLSI Fundamentals

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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 17: March 23, 2017 Energy and Power Optimization, Design Space Exploration, Synchronous MOS Logic

2 Lecture Outline! Energy and Power Optimization " Tradeoffs! Design Space Exploration " Design Problem Example: Match Circuit 2

3 Total Power! P tot = P static + P sc + P dyn! P sw = P dyn + P sc = a(c load V 2 f) + C sc V 2 f! P tot a(c load V 2 f) + C sc V 2 f + VI s (W/L)e-Vt/(nkT/q)! Let a = activity factor a = average #tran 0#1 /clock 3

4 Energy and Power Optimization

5 Power Sources Review: P tot = P static + P dyn + P sc

6 Worksheet Problem 1 V in I static I dynamic I sc 0V 140mV 400mV 500mV 600mV 860mV 1V 6

7 Worksheet Problem 1 V in I static I dynamic I sc 0V 180pA 126uA 140mV 6nA 100uA 400mV 36uA 18uA 500mV 36uA 600mV 36uA 18uA 860mV 6nA 100uA 1V 180pA 126uA 7

8 Energy and Power Optimization

9 Reminder: Worksheet Problem 1 V in I static I dynamic I sc 0V 180pA 126uA 140mV 6nA 100uA 400mV 36uA 18uA 500mV 36uA 600mV 36uA 18uA 860mV 6nA 100uA 1V 180pA 126uA 9

10 Reduce V dd (Worksheet #2)! V dd =520mV, V thn = V thp =300mV V in I static I dynamic I sc 0V 140mV 260mV 360mV 500mV 10

11 Reduce V dd (Worksheet #2)! V dd =520mV, V thn = V thp =300mV V in I static I dynamic I sc 0V 180pA 39.6uA 140mV 6nA 14.4uA 260mV 111nA 360mV 6nA 10.8uA 500mV 180pA 36uA 11

13 Reduce V dd! What happens as reduce V? " Energy? " Static " Switching " Delay? 13

14 Reduce V dd :! τ gd =Q/I=(CV)/I! I d =(µc OX /2)(W/L)(V gs -V TH ) 2! τ gd impact?! τ gd 1 V 14

15 Reduce V dd :! τ gd =Q/I=(CV)/I! I d =(µc OX /2)(W/L)(V gs -V TH ) 2! τ gd impact?! τ gd 1 V! Ignoring leakage: E V 2 Eτ 2 Const 15

16 Reduce V dd (Worksheet #3)! V thn = V thp =300mV, V in =V dd, estimate Eτ V dd I ds dd =1) E switch / (E dd =1) Eτ 1V 700mV 500mV 350mV 260mV 16

17 Reduce V dd (Worksheet #3)! V thn = V thp =300mV, V in =V dd, estimate Eτ V dd I ds dd =1) E switch / (E dd =1) Eτ 1V 126uA mV 72uA mV 36uA mV 9uA mV 111nA

18 Reduce Short-Circuit Power?! P sc = ac sc V 2 f # # E = V dd I peak t sc % 1& & % (( \$ \$ 2' ' Vin Vdd-Vthp Vthn time Vdd Vdd Isc Vout tsc tsc time 18

19 Increase V th (Worksheet #4)! What is impact of increasing threshold on " Delay? " Leakage?! V dd =1V, V in =V dd V thn = -V thp I ds th =300mV) I static (I th =300mV) I stat / 300mV 460mV 600mV 19

20 Increase V th (Worksheet #4)! What is impact of increasing threshold on " Delay? " Leakage?! V dd =1V, V in =V dd V thn = -V thp I ds th =300mV) I static (I th =300mV) I stat / 300mV 126uA 1 180pA 1 460mV 97uA pA mV 72uA fA

21 Idea! Tradeoff " Speed " Switching energy " Leakage energy! Energy-Delay tradeoff: Eτ 2 21

22 Design Space Exploration 22

23 Design Problem! Function: Identify equivalence of two 32bit inputs! Optimize: Minimize total energy! Assumptions: Match case uncommon " Ie. Most of the time, the inputs won t be matched! Deliberately focus on Energy to complement project " but will still talk about delay 23

24 Idea: Design Space Explore! Identify options " All the knobs you can turn! Explore space systematically! Formulate continuum where possible " i.e. formulate trends 24

25 Problem Solvable! Is it feasible? " First, make sure we have a solution so we know our main goal is optimization! How do we decompose the problem? 25

26 Problem Solvable! Is it feasible? " First, make sure we have a solution so we know our main goal is optimization! How do we decompose the problem?! What look like built out of nand2 gates and inverters? 26

27 Total Power! Static CMOS: " P tot a(½c load +C sc )V 2 f+vi s (W/L)e-Vt/(nkT/q)! What can we do to reduce power? 27

28 Knobs! What are the options and knobs we can turn? 28

29 Design Space Dimensions! Vdd! Topology " Gate choice, logical optimization " Fanin, fanout, Serial vs. parallel! Gate style / logic family " CMOS, Ratioed (N load, P load)! Transistor Sizing! Vth! The choices you make impact area, speed (delay), power 29

30 How Reduce Short-Circuit Power?! P sc = ac sc V 2 f # # E = V I t % 1& & dd % ( peak sc ( \$ \$ 2' ' 30

31 Gate! What gates might we build?! High fanin?! Serial-Parallel? 31

32 Logic Family! Considerations for each logic family? " CMOS " Ratioed with PMOS load " Ratioed with NMOS load 32

33 Sizing! How do we want to size gates? 33

34 Reduce Vdd! What happens as reduce V? " Energy? " Dynamic " Static " Switching Delay?! How low can we push Vdd? 34

35 Reduce V dd \$ τ gd =Q/I=(CV)/I \$ I d =(µc OX /2)(W/L)(V gs -V TH ) 2 \$ τ gd impact? \$ τ gd α 1/V 35

36 Increase V th?! What is impact of increasing threshold on " Dynamic Energy? " Leakage Energy? " Delay? 36

37 Design Problem! Function: Identify equivalence of two 32bit inputs! Optimize: Minimize total energy! Assumptions: Match case uncommon " Ie. Most of the time, the inputs won t be matched! Deliberately focus on Energy to complement project " but will still talk about delay 37

38 Design Space Dimensions! Vdd! Topology " Gate choice, logical optimization " Fanin, fanout, Serial vs. parallel! Gate style / logic family " CMOS, Ratioed (N load, P load)! Transistor Sizing! Vth! The choices you make impact area, speed (delay), power 38

39 Ideas! Three components of power " P tot = P static + P dyn + P sc! We know many things we can do to our circuits! Design space is large! Systematically identify dimensions! Identify continuum (trends) tuning when possible! Watch tradeoffs " don t over-tune 39

40 Sequential MOS Logic

41 Classes of Logic Circuits two stable op. pts. Latch level triggered. Flip-Flop edge triggered. one stable op. pt. One-shot single pulse output no stable op. pt. Ring Oscillator Combinational Circuits: a. Current Output(s) depend ONLY on Current Inputs. b. Suited to problems that can be solved using truth tables. Sequential Circuits or State Machines: a. Current Output(s) depend on Current Inputs and Past Inputs via State(s). b. Suited to problems that are solved by completing several steps using current inputs and past outputs in a specific order or a sequential manner. 41

42 Functions Using Sequential Operations 42

43 Sequential Circuit (or State Machine) Construct Inputs Outputs V o1 Vo2.... V o3 Present State -> Register is used to Store Past Values of State(s) and Output(s) -> Synchronous Sequential Circuit clock, outputs change with clock event -> Asynchronous Sequential Circuit no clock, outputs change after inputs change REGISTER.... Next State Clock 43

44 Static Bistable Sequential Circuits Basic Crosscoupled Inverter pair Q Q 44

45 Static Bistable Sequential Circuits Basic Crosscoupled Inverter pair Q Q 45

46 Static Bistable Sequential Circuits Basic Crosscoupled Inverter pair Q Q 46

47 Static Bistable Sequential Circuits Basic Crosscoupled Inverter pair Q V OH = V DD Q V OL = 0 maintain stable state. STATIC: V DD and GND are required to maintain a stable state. Basic Bistable Cross-coupled Inverter Pair has no means to apply input(s) to change the circuit's State. 47

48 Basic Sequential Circuits (Cells)! Latches! Registers 48

49 Latch! Level-sensitive device! Positive Latch " Output follows input if CLK high! Negative Latch " Output follows input if CLK low Q = CLK Q + CLK In 49

50 Register! Edge-triggered storage element! Positive edge-triggered " Input sampled on rising CLK edge! Negative edgetriggered " Input sampled on falling CLK edge 50

51 Shift Register! How do you make a shift register out of latches? 51

52 Two Phase Non-Overlapping Clocks! Build master-slave register from pair of latches! Control with non-overlapping clocks 52

53 Two Phase Non-Overlapping Clocks! Build master-slave register from pair of latches! Control with non-overlapping clocks 53

54 Two Phase Non-Overlapping Clocks! Build master-slave register from pair of latches! Control with non-overlapping clocks 54

55 Two Phase Non-Overlapping Clocks! What could go wrong if the overlap? 55

56 Clocking Discipline! Follow discipline of combinational logic broken by registers! Compute " From state elements " Through combinational logic " To new values for state elements! As long as clock cycle long enough, " Will get correct behavior 56

57 CMOS SR Latch NOR2 * * 57

58 CMOS SR Latch NOR2 basic crosscoupled inverter pair 58

59 CMOS SR Latch NOR2 basic crosscoupled inverter pair 59

60 CMOS SR Latch NOR2 SET OP: S = 1, R = 0 basic crosscoupled inverter pair 60

61 CMOS SR Latch NOR2 RESET OP: R = 1, S = 0 basic crosscoupled inverter pair 61

62 CMOS SR Latch NOR2 HOLD OP: S = 0, R = 0 basic crosscoupled inverter pair 62

63 CMOS SR Latch NOR2 HOLD OP: S = 0, R = 0 basic crosscoupled inverter pair 63

64 CMOS SR Latch NOR2 ACTIVE HIGH * * 64

65 CMOS SR Latch NAND2 basic cross-coupled inverter pair 65

66 CMOS SR Latch NAND2 ACTIVE LOW * * * * 66

67 Synchronous Latches NAND SR SR Latch LATCH NOTE: S and R are asynchronous. S/R S /R' CK 67

68 Synchronous Latches NAND SR SR Latch LATCH NOTE: S and R are asynchronous. S/R S /R' CK SET STATE: CK = 1, S = 1, R = 0 => S' = 0, R' = 1 => Q n+1 = 1, Q n+1 = 0 RESET STATE: CK = 1, S = 0, R = 1 => S' = 1, R' = 0 => Q n+1 = 0, Q n+1 = 1 NOT ALLOWED: CK = 1, S = 1, R = 1 => S' = 0, R' = 0 IS CK = 1, S = 0, R = 0 a HOLD STATE? 68

69 Synchronous Latches HOLD STATE: CK = 1, S = 0, R = 0 T glitch Q error due to glitch on S R 69

70 Latch! Level-sensitive device! Positive Latch " Output follows input if CLK high! Negative Latch " Output follows input if CLK low Q = CLK Q + CLK In 70

71 Static CMOS D-Latch S If CK = 1 R LATCH If CK = 0, HOLD 71

72 Static CMOS D-Latch S If CK = 1 R LATCH If CK = 0, HOLD 18 Transistors CK D S' R' Q n+1 Q n SR-Set SR-Reset 0 x 0 0 Q n Q n SR-Hold + NO TOGGLE + NO NOT-ALLOWED INPUTS 72

73 Static CMOS TG D-LATCH 8 Transistors 8 Transistors **Transistor level implementation using transmission gates requires fewer transistors 73

74 Static CMOS TG D-LATCH CK D CK Q CK Q CK 74

75 Static CMOS TG D-LATCH When CK = 1 output Q = D, and tracks D until CK = 0, the D-Latch is referred to positive level triggered. When CK 1 to 0, the Q = D is captured, held (or stored) in the Latch. 75

76 D-LATCH Timing Requirements 76

77 Ideas! Synchronize circuits " to external events (eg. Clk) " disciplined reuse of circuitry! Leads to clocked circuit discipline " Uses state holding element (eg. Latches and registers) " Prevents " Timing assumptions " (More) complex reasoning about all possible timings 77

78 Admin! HW 6 due midnight 78

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