Topics. CMOS Design Multi-input delay analysis. John A. Chandy Dept. of Electrical and Computer Engineering University of Connecticut
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1 Topics CMO Design Multi-input delay analysis pring 25
2 Transmission Gate OUT Z OUT Z pring 25
3 Transmission Gate OUT When is low, the output is at high impedance When is high, the output follows However, OUT can only rise to V DD DD -V T, T, at which point the transistor will shut off pring 25
4 Transmission Gate OUT When is high,, the output is at high impedance When is low,, the output follows However, OUT can only fall to V T, at which point the transistor will shut off pring 25
5 Transmission gate Requires both nmo and pmo transistors ingle nmo or single pmo will cause signal degradation pring 25
6 Transmission Gate OUT pring 25
7 Multiplexer OUT OUT OUT = + pring 25
8 CMO Logic Implementation Multiplexer OUT = + OUT pring 25
9 Multiplexer Transmission gate based OUT OUT pring 25
10 Memory Use feedback loops to store bits How do you get the bit in the loop? pring 25
11 Memory Use transmission gates to control entry to the loop D TG TG CTL Level sensitive D-latch pring 25
12 Latches Level sensitive latches do not allow you to isolate output from input when control is high. olution is to use a master-slave setup where master latches input and then slave latches the output pring 25
13 Master -slave latch D TG Q TG Q2 TG TG CTL pring 25
14 Master -slave latch CTL D Q Q2 Negative edge-triggered flip-flop pring 25
15 CMO Logic etup time is how much time before the clock edge that the data should be ready If setup time is not met, the data will not have time to get through transmission gate and into the feedback loop Hold time is the time that the data is required to be stable after the clock edge. If hold time is not met, invalid data may get past the transmission gate and into the feedback loop. pring 25
16 CMO Logic Flip-Flops D Q Q R Q Q J K Q Q X X X X X X X X pring 25
17 CMO Logic Registers N-bit collection of flip-flops pring 25
18 CMO Logic Gate Design How do you characterize delay for a gate more complicated than an inverter? eff is determined by the structure of the logic gate k eff t d = C L k eff pring 25
19 Delay time analysis Multi-input gates P N P 2 OUT For pull down (falling delay time) k neff = + k n k n2 = k n 2 For pull up (rising delay time) k peff = k p N 2 pring 25
20 NND k eff n = k n 2 k eff p = k p Falling delay has doubled pring 25
21 Delay time analysis Multi-input gates For equal delay times k n = 2k p P P 2 OUT W n L n k' n = 2 W p L p k' p N N 2 pring 25
22 NND 2x 2x 2x k n = 2k p 2x W n L n k' n = 2 W p L p ince k' n 2k' p and assume L n = L p k' p we get W n = W p pring 25
23 Delay time analysis P 2 For pull down (falling delay time) k n eff = k n (single transistor on) P N N 2 OUT For pull up (rising delay time) k p eff = + k p k p 2 = k p 2 pring 25
24 NOR + k eff n = k n k eff p = k p 2 Rising delay has doubled pring 25
25 Delay time analysis P 2 For equal delay times 2k n = k p P OUT 2 W n L n k' n = W p L p k' p N N 2 pring 25
26 NOR 4x 4x + 2 W n L n 2k n = k p k' n = W p L p k' p x x ince k' n 2k' p and assume L n = L p we get 4W n = W p pring 25
27 Multi-input NOR C k eff n = k n k eff p = k p 3 Rising delay has tripled ++C pring 25
28 Multi-input NOR C 6x 6x 3k n = k p 6x 3 W n L n k' n = W p L p k' p ++C ince k' n 2k' p and assume L n = L p x x x we get 6W n = W p pring 25
29 C C k eff n = k n 3 C F k eff p = k p 2 Falling delay has tripled Rising delay has doubled C pring 25
30 4x 4x C 4x 4x C 4x F 3x C 2x 2k n = 3k p 3x 2x 2 W n L n k' n = 3 W p L p k' p C 3x ince k' n 2k' p and assume L n = L p we get 4W n = 3W p pring 25
31 4x 4x C 4x 2x 4x C 4x x C 3x 3x 3x C 2x 2x F Without sizing t p = C in + C L k k 3 7 t p 2 = 3 C in + C L k k With sizing pring 25
32 CMO Logic Gate Delays Increasing transistor sizes can reduce the delays, but it Increases area Increases load capacitance for driving gates Multi-input gates may not always be good pring 25
33 Next class Gate Delays Logical Effort Chapter 6.2 pring 25
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