# Objective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components

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1 Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the professors who created such good works onthose lecture notes. Without them, these slides could have not been presented to you. 2

2 CMOS Technology 3 HDD: Shallow High-doped drain (no LDD) Scaling LDD: Lightly Doped Drain Reduce hot carrier effects Introduction ti 4

3 Dynamic Power Consumption 5 Power Consumption Static Power (no input/output change) 1. Leakage current. 2. Sub-threshold conductance. 3. Pseudo-NMOS has a static current (direct current path between supply and ground) when output is low. Dynamic Power (during input/output change) 1. Capacitive Power due to charging/discharging of capacitive load. Note that sometimes only refer to this component as the dynamic power. 2. Short-circuit power due to direct path currents when there is a temporary connection between power and ground. Note that sometimes only refer to this component as the short circuit power. 6

4 Dynamic Power Dissipation i P 0 1 & P 1 0 i out v out 7 Dynamic Power Consumption 8

5 Lowering Dynamic Power 9 Dissipated i Energy Charging: E dis0 1 =E Vdd E C =C L.V dd2 /2 Discharging: E dis1 0 =E C 0=C L.V dd2 /2 Total dissipation E dis1 0 +E dis1 0 = C L.V dd 2 10

6 Dynamic Power Dissipation i P dynamic = C L.V DD2.f y Assume P 0 1 for all gates 1. Example 1.2 μm CMOS chip 100 MHz clock rate Average load capacitance of 30 ff/gate 5V power supply Power consumption/gate = 75 μw Design with 200, gates: 15W! Pessimistic evaluation: not all gates switch at the full rate Reducing V DD has a quadratic effect on P dynamic 11 Node Transition Activity it (Switching Activity it Factor) Consider switching a CMOS gate for N clock cycles E = C V N L 2 nn dd ( ) E N : the energy consumed for N clock cycles n(n): the number of 0->1 transition in N clock cycles P = lim avg N E N N f clk = nn lim ( ) 2 C N N V dd fclk L α 0 1 = n( N lim ) N N P avg = α 0 1 C L V dd 2 fclk 12

7 Pi Principles il for Dynamic Power Reduction Rd 13 Dynamic Power Consumption is Data Dependent 14

8 NOR Gate Transition Probabilities biliti 15 Transition Probabilities biliti for Some Basic Gates P 0 at the inverter input is equal to P 1 at its output. 16

9 Transition Probabilities biliti as a Function of Input Numbers Note: XOR n (x 1, x 2,...,x n ) = x 1 x 2... x n 17 Inter-Signal Correlations 18

10 Inter-Signal Correlations P(Z=1) = = 0.5 X 19 Become complex and intractable fast! Logic Restructuring t 20

11 Logic Restructuring t Chain Tree 21 Input Re-Ordering Od Worse Better 22

12 Input Re-Ordering Od P X (1) = P A (1).P B (1) = 0.1 P X (0) = 1 P X (1) = 0.9 P X (0 1)= P F (1) = P X (1).P C (1) = 0.01 P F (0 1) = P X (1) = P A (1).P B (1) = 0.02 P X (0) = 1 P X (1) = 0.98 P X (0 1)= P F (1) = P X (1).P C (1) = 0.01 P F (0 1) = Glitching in Static ti CMOS Networks 24

13 Glitching in Static ti CMOS Networks Glitch 25 Spurious Transition at a Node Glitching Power 26

14 Example: Glitching in an Ripple Carry Adder (RCA) Complete Charge Complete Discharge Time (ns) Ripple carry adder generates the carry of each bit based on the sum of the previous bits. 27 Balanced Delay Paths to Reduce Glitching 28

15 Solution: Balanced Delay Paths The diagrams only schematically shows the idea behind each type of adder. Carry lookahead adder generates the carry of each bit based on the previous bits without waiting for the sum of the previous bits to propagate Make the delay of all carry almost the same 29 Factors Affecting Transition Activity: it α 0 1 # of inputs (Type and style) 30

16 Short Circuit it Currents I SC is determined by the two voltages of the n and p transistors: 1) V GS (t) is a function of the input slope. Determines on/off state of the transistors. 2) V DS (t) is a function of the output slope-determined by C L. Determines the region of operation (linear/saturation) of the transistors. Note: The current used for charging the capacitor is not wasted. 31 Short Circuit it Currents I mean is the average short circuit current for one period that the output make a transition. 32

17 Symmetrical Inverter Without t Load 33 Symmetrical Inverter Without t Load 34

18 Short Circuit it Currents I mean = I peak.t sc /T mean peak sc determines t sc. 35 Output t Transitions under Different tloads 5 36

19 Impact of fc L on P sc C L remain short circuit till the end of the C L quickly becomes open circuit and input transition. (Bad for cascaded logic) the current is determined by the ratio of The current used for discharging the the two transistors on-resistances. Since capacitance is not considered as the short this current is not used in charging the circuit current. capacitor, it is wasted 37 I peak as a Function of fc L 38

20 Short-Circuit it Current Short circuit current goes to zero if t fall(output) >> t rise(input) But cannot do this for cascaded logic Keep input and output rise/fall times the same Less than 10% of the total consumption For small C L s (less dynamic power), the power is mainly due to short circuit current 39 Short Circuit it Current Conclusions: Vd d If inverter is lightly loaded (small C L, so output t r, t f Vin Vout are shorter than input t r,t f then P SC becomes comparable to dynamic dissipation C L When input and output have equal rise and fall times, P SC is small Must make input t r, t f equal to output t t r, t f. I VDD (ma) V in (V)

21 P sc as a Function of Rise/Fall Times (P sc /P sc0 ) (P sc0 ) 41 Static ti Power Consumption Vdd I stat V out V in =5V C L P stat = P (In=1).V dd. I stat Wasted energy Should be avoided almost in all cases. 42

22 Leakage Components of the Static Power Dissipation 1. pn junction reverse bias current 2. Weak inversion 3. Drain-induced i d barrier lowering (DIBL) 4. Gate-induced drain leakage (GIDL) 5. Punch-through 6. Narrow width effect (for trench isolation) 7. Gate oxide tunneling 8. Hot carrier injection 43 Subthreshold h (Weak Inversion)/Reversed Biased PN Junction Currents db (PMOS) pn junction: V db = 0 db (NMOS) pn junction : V db = V DD Long channel model if V t does not contain DIBL effect. 44

23 Reverse Biased pn Junction Leakage current through the reverse biased diode junctions For typical devices it is between 10pA 500pA at room temperature For a die with 1 million devices operated at 5 V, this results in 0.5mW power consumption not much Junction leakage current is caused by thermally generated carriers therefore is a strong function of temperature (J S doubles for every 9 deg C!) For 0.25 μm CMOS: J S = pa/ μm 2 at 25 deg C. GATE p + p+ N + - V dd I DL = J S A Reverse Leakage Current 45 Subthreshold Leakage Component The sub-threshold leakage is very important when the threshold voltage is close to 0. Sub-threshold current is one of most compelling issues in low-energy circuit design! 46

24 Leakage as a Function of fv T 47 Gate Oxide Tunneling Not correct dimension (see next slide ox1 I ) I GD 48

25 HighE ox electric field across oxide layer causes: Direct electron tunneling through gate I ox1 e e ct ox dv ox Fowler-Nordheim (FN) tunneling through oxide bands (usually only at higher E ox than chips use) I ox2 = AE 2 ox e b / E ox Currently is a non-issue, expected to become dominant leakage condition as oxides get thinner Gate Oxide Tunneling 49 Temperature Dependence of fthese Components 50

26 Gate-Induced ddrain Leakage (GIDL) High field between gate and drain (small gate and large drain voltages) increases the hole-electron generation injecting holes into substrate and electron into the drain substrate leakage and drain current increase. Some electrons tunnel from gate to drain using surface traps and/or band-to-band tunneling. gate leakage and drain current increase. This component is not considered as GIDL. Depletion due to MIS structure of Gate/Oxide/Drain (LDD) 51 Gate-Induced ddrain Leakage (GIDL) Increasing current for negative V G values Localized along channel width between gate and drain Major problem in I off current: Caused by thinner t ox, higher V DD, and lightly doped drains. Contributes to standby power, so must control this by increasing oxide thickness, increasing drain doping, or eliminating traps. For high performance device (low V th ), is not a major issue. 52

27 Drain-Induced d Barrier-Lowering i (DIBL) Depletion region of drain interacts with source near channel surface Voltage at the drain lowers the potential barrier at the source Lowers V Th Increases subthreshold current without any change ons Causes source to inject carriers into channel surface independent of the gate voltage More DIBL at higher V D and shorter L eff Moves curve up, to right, as V D increases SurfaceDIBL happens before deep bulk punchthrough Fix DIBL: Higher surface & channel doping Shallow source/drain junction depths 53 Punchthrough h Happens when drain and source depletion regions approach each other and touch. Letschannel current exist deep in sub-gate region and in the surface Gate loses control of sub-gate region. Variesquadratically with V D and with V S. Viewed as subsurface (deep in bulk) version of DIBL 54

28 Trench isolation: Narrow-Width Effect Dig trench in substrate and fill with SiO 2 to isolate n and p MOSFETs Non-trench isolated technologies (LOCOS): V t increases for gate widths of 0.5 μm Trench isolated technologies: V t decreases for effective channel widths W 0.5 μm 55 DIBL, GIDL, Weak Inversion DIBL Moves curve up, to right as V D increases V D going from 0.1 to 2.7 V, I D changed 1.68 decades 1.55V/decade change of I D Large V G s means less GIDL 56

29 Leakage Components GIDL dominates DIBL dominates Weak inversion dominates 57 CMOS Energy & Power Equations t leakage t leakage /T 58

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