# C.K. Ken Yang UCLA Courtesy of MAH EE 215B

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1 Decoders: Logical Effort Applied C.K. Ken Yang UCLA Courtesy of MAH 1

2 Overview Reading Rabaey (Ratio-ed logic) W&H Overview We have now gone through the basics of decoders, and logical effort. This lecture will use logical effort to optimize the performance of a decoder, d and in the process motivate t some creative ways to build CMOS logic gates. One result of this process will be a need to analyze slightly more complex structures than a single RC network. Another issue that will come up is power dissipation. We will talk about power dissipation in this lecture, but will leave the more complex RC networks for the next lecture. 2

3 Decoder Review N address 2N lines A0, A0_b both needed Each decoder an AND gate Large fanin Must drive wordline 2 N gates Fanout on Address lines large ½ of the number of decode d gates 2N address lines 3

4 Decoder Review Decoder has two main jobs: Logic function Using N address bits Needs to select 1 of 2 N wordlines This means the logical effort of the chain will be larger than 1 Similar to LE of an N input AND gate Act as a buffer chain The address line has a large fanout Each address line ultimately needs to drive every AND gate A0 drives ½ of the decoders and A0_b drives the other ½ The wordline capacitance can be large It has 2 M cells on it, and a large wire capacitance Total fanout is proportional to the Size of the memory 4

5 Example Assume we are building a 256x256 memory (8KB memory) Assume that t C add = 4* C cell A0 drives 2* C cell and A0_b drives 2* C cell Total fanout on each address input (A0,A0_b) is then 2 14 What is the minimum logical effort for 8-AND function? Since fanout is large don t need to worry about # of stages We will need lots of inverters anyhow Many possibilities 2NAND -Inv trees 2 NAND - 2 NOR trees 4 NAND - Inv tree Etc 5

6 Optimal Static Decoder Logical Effort of building 8 input AND 1. Three 2-NAND gates is 4/3 3 = NAND, 2-NAND is 2*4/3= NAND, 2-NOR, 2-NAND is 4/3 2 *5/3 = NAND 10/3=3.33 Which is best? Depends on the number of levels of logic you need 6 8 to 4, 4 to 2, 2 to 1 (3 inv) 4 8 to 2, 2 to 1 (2 inv) 4 8to4,4to2,2to1(1inv) to 1 (1 inv) If you need lots of gates, 2-input gates are often the best 6

7 Number of Stages of Logic For our decoder (assuming 2-NAND gates) The decoder d has a total t effort of 2.4 (which is 4/3 cubed) * FO (BH, which is 2 14 ) Note that using other gates would not change this result very much, so don t worry about which gate you are going to use when you figure out the total effort. For a effective stage effort (fanout) of around 4 per stage This design would need around 7.5 stages which is Log 4 (2 15 ) Note that using other gates would change the total effort by less than 2x. Does not change stage effort much! (but can change speed!) But how is it going to be put together? How do we size the individual gates? Which wires do we run up the decoder? 7

8 Predecode Options Two basic choices Can do a 2-4 predecode d in 4 groups, with a 4t to 1fi final gate Final gate has two level of and gates Uses only 16 address wires running across the decoder Final gates are larger (Area concern) Can do a 4-16 predecode in 2 groups, with a 2-1 final gate Uses 32 address lines running across the decoder Final gates are smaller Generally doing a larger predecode is better for two reasons More levels of logic before the intermediate wire capacitance Less capacitance switches each cycle (lower power) 8

9 General Predecode Consider the 4 to 16 decoder: branching effort = 2 for n inputs BEpis approx 2 n-1 x 4 a1 a0a1 a0a1a2a3 C L logical effort = a x x x x 3 3 total path effort PE= (LEp)(BEp) (FOp) =(4/3)2(2)(4)C L /Cin This formula has A0 and A0_b as separate inputs Otherwise branching effort would be 2 n 9

10 Decode Path By using a 4-16 predecode we have moved more stages of logic before the long wire This decreases its effect on the circuit, since it naturally give us more stages of buffers before driving the wire Otherwise we would need more stages in the predecode, just to drive the wire A0A1A2A3 C L to 16 predecoder A0 A1 A2 A3 10

11 Logical Effort of Predecoder This works back from the load on the predecoder for both a 2-4 predecoder, d and a 4-16 predecode 4/3 / f 2 1/f 2 to 4 decoder 1 4/3 / f 2 1/f 1 If this gives you a input capacitance that is too high, you need to add extra buffer stages (4/3) *4/ f 3 (4/3) 2 *4/ f 4 portion of 4 to 16 decoder (4/3) 2 *8/f 4 load stages (4/3*2) / f 2 is the load here (16/9*8)/f 4 4 to 16 decoder 11

12 Logical Effort in Real Life There are fixed side loads you need to deal with For a memory, the side load is the wire capacitance of the predecoder outputs Since these capacitances don t scale with sizing, they don t fit in nicely to the logical effort frame work They can also be caused by loading of non-critical gates 12

13 Handling of Side Loads w x y Small side loads < parasitic loading, p Ignore the capacitance Increase the self-load, p, since short wires will scale (somewhat with gate size). Very large side loads > gate loading, A >> y Optimally size gates before the large side load (w, x) Find f opt. Use same f opt for y (or use FO ~4) A B 13

14 Medium Fixed Side Loads w x y A B If B=64 and A=0, then w=1, x=4, y=16 (easy) If B=64 and A=8, things get more difficult. Formally we can add the sideload and solve the problem again using the fact that d = x/w + (A+y)/x + B/y and (d/dx)d=(d/dy)d=0. These equations can be rewritten in an iterative form and then solved. After iterating, this produces x=5 y=18. Let p = 1, d = (p) = 16.4 But increasing the size of y makes a very small difference and adds power and area. It is probably not a good idea. 14

15 Simplified Handling of Medium Side Loads First solve the problem without the side load: gives w=1, x=4, y= Use y=16, re-optimize for sizing of w and x. Example: y = 16 (from before) Solve for w and x; H=24, f opt = ~5 x = 4.9 With p =1, d = (p) =16.8 Compared to optimal, the difference is small. w x y A B 15

16 SRAM Array Decode is in critical path Fanout is FIXED! Only way to improve speed Decrease logical effort If the logical effort was 1 (Ignore logic) Use static inverter Address input Delay would be ln 4 (Size*C cell / C addr) ) ln 4 (Size) + ln 4 (C cell / C addr) ) Read enable Row decoder 2 n n m Column decoder Sense en Write en Read-write control 2 m word line bitline Column Mux Sense amplifier Write driver Data in Data out 16

17 Faster Static Decoder We can do better than simple static gates Spend power for speed The input drives both nmos and pmos. nmos size is doubled because of the series stack. Remove the series stack? Drive only pmos? Or nmos (for a NOR)? A B O A B O 17

18 Pseudo-nMOS Logic Better to use nmos logic pull-down because nmos is faster than pmos. Pull down implements f_b Resistors are not readily available in digital it process flow Use pmos with gate tied to ground. That s why it is called pseudo - nmos Favors NOR structures, not NAND Less series stacking A B Pul ll-down Lo ogic, f O 18

19 Example: Pseudo-nMOS 3-NOR Output Levels Output t HIGH = V OH <V DD Output LOW = V OL > 0 Degraded logic values Constant DC current Power hungry Avoid more problems if we drive input with CMOS gate. W W W W At least V OH =V DD 19

20 Pseudo-nMOS Design Considerations Ratioed logic Output t levels l depend d on relative size of PN. For a given PMOS size, The worst-case pull down (a single NMOS path V IN =V OH ) should fight the resistor to reach < V OL. The maximum # of parallel pull down path is limited Small current may flow even when devices are nominally off (V OL <V TN ) When designing, set all inputs=v OL, the output should be >V OH. Up/down speed depends on relative size of PN Current available for charging/discharging the load is less because of the other current path. Speed depends on V OL. Can be very asymmetric Equal Rise and Fall can result in V OL >V TN. (more power hungry) 20

21 Logical Effort of Pseudo-nMOS W W W W Sizing for roughly equal rise and fall. Logical Effort for this gate is 2/3! (It is less than 1) The 2/3 is because we are not really using a resistor model. Rather we assume that the transistors produce a current and when the nmos fights the pmos, the current fighting the pmos can t drive the capacitance load. 21

22 Lower Power Pseudo-nMOS No need to make the gate dissipate power all the time Can have the pmos gate connected to one of the inputs One input might be available early Or you can rotate which input you use For decoder (NOR) almost all inputs are HIGH Except for the set that contains the final asserted WL., ½*16, ¼*32, 1/16*256 Notice the nmos can be smaller, Since it does not need to fight the pmos Might keep it the same size W W/2 W W 22

23 Faster Static Decoder What happens if you make the input pulses A*Clk ; A_b*Clk (both signals are qualified by clock) Both inputs go low when the clock is low Does that make it possible to make a faster decoder? Know BOTH inputs are low for rising output of NAND gate W W 2W 2W Logical effort of 2 NAND is 1 (w/ vel sat around.8) But you really want the LE of the inverters to improve too 23

24 Logical Effort of Asymmetric Gates What happens if rising and falling delay are not the same 1 1 Main Issue: Need to calculate rising delay and falling delay separately LE of the gate will be different for the different edges Need to use in a situation ti where there is a default state t And only one edge can be on the critical path Size for that edge 24

25 Pulsed Input What happens if we decide that the falling transition of the WL can be slower than the rising edge (slow de-assert) Can make the pmos in NAND gates even smaller Or can make the nmos in the inverter smaller W/2 W/2 2W 2W 2W W/2 Now logical effort of all gates on the path is 5/6 De-assert will be twice the delay of the assert edge 25

26 Precharged Gates If we are using pulses anyhow Why not use precharged gates You can but You generally need to use NAND gates not NOR gates THE PROBLEM: Think about a precharged NOR decoder All the outputs start high After evaluation all but one of the lines are low That means N-1 outputs change value each cycle In a precharged NAND decoder All outputs start high After evaluation only the selected output changes If I invert the output, I get the wordline that I want If you use a precharged structure, you need to create a clock 26

27 Logical Effort of Dynamic Gates LE= 1 LE=2/3 What about the foot transistor? Does it need to be sized the same? NAND structure might not need a footing transistor. 27

28 Precharged NAND Decoder Generally Built with NAND gates If you don t use clocked transistors t Can get lower logical effort CLK W/2 4W If we used NAND gates with skewed inverters afterward Assume inputs are pulses Average Logical Effort is Sqrt(2/3 * 5/6) = W 2W W 28

29 Faster Decode NAND Gates Can use a strange switch logic NAND gate The logical l effort from A0 is small 1/3 The speed from A1 is also fast Buffer driving A1 is very large For LE calculation, one needs to know the buffer strength Need to solve a more complex RC network Have two large caps separated by a resistor Clk A0 A1_b W W Look as solving this next lecture RA 1 CA1_ b Cout 29

30 Important Aside: Decoder Area An important metric to not ignore is the area Area is in the wires Gates with large repeat factor This means all the area is in the final decoder Needs to pitch match cells Long and narrow, since cell pitch is small Want it to be compact There is strong pressure to undersize gates in final decoder Lowers capacitance on predecode lines Reduces final layout area Speed change is small Remember delay vs. fanout is pretty flat 30

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