Chapter 5. The Inverter. V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov Inverter

Transcription

1 Chapter 5 The Inverter V1. April 10, 03 V1.1 April 25, 03 V2.1 Nov.12 03

2 Objective of This Chapter Use Inverter to know basic CMOS Circuits Operations Watch for performance Index such as Speed (Delay calculation) Optimal Transistor Sizing for speed and Energy Power Consumption and Dissipation

3 The CMOS Inverter: A First Glance V DD V in V out C L

4 CMOS Inverter N Well V DD V DD PMOS PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND A=WxL

5 Two Inverters Share power and ground Abut cells V DD Connect in Metal Vin Vout Vout Vin

6 CMOS Inverter First-Order DC Analysis V DD V DD V out R p V out V OL = 0 V OH = V DD R n V in = V DD V in = 0

7 Delay Definitions (circuit speed) V in 50% t V out t phl t plh 90% 50% 10% t t f t r

8 CMOS Inverter: Transient Response V DD V DD R p t phl = f(r on.c L ) = 0.69 R on C L V out V out ln(2)=0.69 C L C L R n V in = 0 (a) Low-to-high V in = V DD (b) High-to-low

9 Voltage Transfer Characteristic

10 PMOS Load Lines (Vdd = 2.5V in 0.25um CMOS Process) (Vt = 0.4V as shown in Table 3-2) V in = V DD + V GS, p I Dn I D, n = I D, p V out = V DD + V DS, p V out I Dp V in =0 I Dn I Dn V in =0 V in =1.5 V in =1.5 V GSp =-1 V DS,p V DS,p V out V GSp =-2.5 I V in D, n = V DD = I D, p + V GS, p V out = VDD + V DS, p

11 CMOS Inverter Load Characteristics I Dn V in = 0 V in = 2.5 PMOS V in = 0.5 V in = 2 NMOS V in = 1 V in = 1.5 V in = 1.5 V in = 1 V in = 2 V in = 1.5 V in = 1 V in = 0.5 V in = 2.5 V in = 0 V out

12 CMOS Inverter VTC V out NMOS off PMOS res NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat VM: Vin = Vout Switching Threshold Voltage NMOS res PMOS off V in Inverter

13 Switching Threshold as a Function of Transistor Ratio NMOS and PMOS are in Saturation Modes rvdd V M (when VDD >> V 1+ r DSAT For r = 1, and saturated velocity NMOS = 2 PMOS, Wp = 2Wn, V Tn, V Tp )

14 Switching Threshold as a Function of Transistor Ratio V (V) M W p /W n

15 Simulated VTC V out (V ) V in (V)

16 Impact of Process Variations 2.5 V out (V) Good NMOS Bad PMOS Nominal Good PMOS Bad NMOS V in (V) Good definition: Smaller oxide thickness, smaller L, higher W, smaller VT Inverter

17 Propagation Delay Inverter

18 CMOS Inverters V DD PMOS In Out 1.2 µm =2λ Metal1 Polysilicon NMOS GND

19 CMOS Inverter Propagation Delay V DD t phl = f(r on.c L ) = 0.69 R on C L V out V out ln(0.5) R on C L 1 V DD V in = V DD R on C L t

20 The Transistor as a Switch V GS V T S Ron D I D V GS = V DD R mid R 0 V DD /2 V DD V DS

21 The Transistor as a Switch 7 x R eq (O hm ) V DD (V )

22 The Transistor as a Switch Inverter

23 Transient Response 3 2.5? V out (V ) t p = 0.69 C L (R eqn +R eqp )/2 0.5 t plh t phl t (sec) x 10-10

24 Delay (speed degrade) as a function of V DD t p (norm alized) when t phl V DD >> V Tn + V C 0.52 ( W / L) k V L ' n DSATn DSATn / V DD (V ) Similar to Rn curve! Sharp change at 2Vt

25 Design for Speed Performance Keep loading capacitances (CL) small Increase transistor ratio (W/L) (adding CMOS gain) Watch out for self-loading (for the previous stage)! Increase Vdd! Trade power/energy dissipation for performance!

26 Propagation delay v.s. Transistor size NMOS-to-PMOS Ratio: Symmetrical tphl and tplh PMOS is 2.5~3.5 wider than NMOS in width under same L Is there better propagation delay (tp), or a better N-to-P ratio for overall tp can be found? Consider two identical cascaded CMOS inverters. The approximated load cap of the 1 st gate is C = ) + C L ( Cdp 1 + Cdn 1) + ( Cgp2 + Cgn2 W C C C, dp1 dn1 C, gp2 gn2 Is drain capacitance of PMOS and NMOS of 1 st stage Is gate capacitance of PMOS and NMOS of 2 nd stage Inverter

27 Propagation delay v.s. Transistor size Inverter When the PMOS device is made β times larger than the ( W / L) p NMOS β = Then CL becomes From (5.20), we have t p = eqp where γ = is the resistance ratio of equal-size NMOS and PMOS C = (1 ( W / L) n βc C βc dp1 dn1 and gp2 gn2 C = ) + C L ( 1+ β )( Cdn 1 + Cgn2 [(1 + β )( C + C ) + C ] dn1 ( R γ [ + β )( C + C ) + C ] R (1 + ) R R eqn dn1 gn2 gn2 W W eqn eqn + R eqp β β ) W

28 NMOS/PMOS ratio t p (sec) x tplh 1.9 tphl β Fig tp β opt β = W p /W n From Table 3.3 β= 31Κ/13Κ = 2.4 when β = opt = γ (1 + ( C C 1 + C 2 dn γ CW + C dn1 gn2 gn >> C Inverter ) W

29 Sizing Inverter

30 Inverter Chain In Out 1 f1 f2 C L If C L is given: - How many stages are needed to minimize the delay? - How to size the inverters? May need some additional constraints.

31 Notation Definition Unit-size NMOS Transistor: the NMOS with minimum Lmin and Wmin that meets the layout design rule (assume L is fixed, and W is varied) : Intrinsic Cap. of unit-size NMOS transistor C unit R unit C g R W : Channel resistance of unit-size NMOS transistor : Gate cap of unit-size NMOS transistor : Channel resistance of W-sized NMOS transistor : Self-loading or intrinsic cap of the inverter C int (diffusion cap and gate-drain overlap (Miller) cap)

32 Delay Minimum length devices, L=0.25µm Assume R P = 2R N and W P = 2W N =2W same pull-up and pull-down currents approx. equal resistances R N = R P approx. equal rise t plh and fall t phl delays Analyze as an RC network Delay (D): t phl = (ln 2) R N C L t plh = (ln 2) R P C L 2W W W W unit unit R P = (2Runit ) Runit = RN = W P W N Load for the next stage: C = 3 gin R W W W unit (R of unit size NMOS) C unit Inverter

33 with Load Delay R P 2W R W W C L Load (C L ) t p = kr W C L k is a constant, equal to 0.69 Assumptions: no load zero delay t phl = (ln 2) R N C L t plh = (ln 2) R P C L Inverter

34 with Load and Para. Cap. C P = 2C unit Delay 2W W C int C L C N = C unit Load Delay = kr W (C int + C L ) = kr W C int + kr W C L = Delay (Internal) + Delay (Load) = kr W C int (1+ C L /C int ) Inverter

35 Delay Formula Delay ~ R W ( C + C ) int L t p = kr W C int ( 1 + C / C ) = t ( 1 + f / γ ) L int p 0 C int = γc g,in with γ 1 f = C L /C g,in : Effective fanout RW = R unit / W ; C int =WC unit t p0 = 0.69R unit C unit (Intrinsic or unloaded delay) Not function of transistor size!! Inverter

36 Apply to Inverter Chain In Out 1 2 N C L t p = t p1 + t p2 + + t pn C gin, j+ 1 t + pj ~ RunitCunit 1 γcgin, j N N C gin j t p = t p j = t, + 1, p0 1 +, Cgin N = j i C, + 1 = 1 = 1 γ gin, j C L

37 Optimal Tapering for Given N Delay equation has (N-1) unknowns, C gin,2 ~ C gin,n Minimize the delay, find (N 1) partial derivatives Result: C gin,j+1 /C gin,j = C gin,j /C gin,j-1 Size of each stage is the geometric mean of two neighbors C gin, j = Cgin, j 1C gin, j+ 1 - Each stage has the same effective fanout (C out /C in ) - Each stage has the same delay

38 Optimum Delay and Number of Stages When each stage is sized by f and has same effective fanout f N f = F = C Effective fanout of each stage: Minimum path delay p L f = N F t = Nt + p0 / Cgin,1 ( 1 /γ ) N F

39 Example In C 1 1 f f 2 Out C L = 8 C 1 C L /C 1 has to be evenly distributed across N = 3 stages: f = 3 8 = 2

40 Optimum Number of Stages Given load, C L and given input capacitance C in Find optimal sizing f t C p L = = F C Nt p0 in = f N C in with N = t ln ( ) p0 F / γ + 1 = + γ ln ln F F f f ln f γ ln f t f p = t p0 ln γ F ln f 1 γ 2 ln f f = 0 f = exp 1+ ( γ f ) For γ = 0, f = e, N = lnf

41 Optimum Effective Fanout f f ( γ f ) = exp 1+ f opt = 3.6 for γ=1, f opt = for γ=0

42 Normalized delay function of F t = Nt + p p0 ( 1 /γ ) N F

43 Buffer Design N f t p Without considering the internal capacitance Inverter

44 Power Dissipation Inverter

45 Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking diodes and transistors

46 Dynamic Power Consumption E VDD = 0 dvout 2 VDD( t) VDDdt = VDD CL dt = VDDCL dvout CLVDD dt = 0 0 i

47 Dynamic Power Dissipation Vdd Vin Vout C L Energy/transition = C L * V dd 2 Power = Energy/transition * f = C L * V dd 2 * f Not a function of transistor sizes! Need to reduce C L, V dd, and f to reduce power. E C 2 dvout CLVDD = ivdd( t) voutdt = CL voutdt = Energy in CL dt 2 0 0

48 Node Transition Activity and Power Consider switching a CMOS gate for N clock cycles E = C V N L 2 nn dd ( ) E N : the energy consumed for N clock cycles n(n): the number of 0->1 transition in N clock cycles P = lim avg N E N f N clk = nn lim ( ) C N N L V dd 2 fclk α 0 1 = nn lim ( ) N N P avg = α 0 1 C L V dd 2 fclk P AVG = ( α0 1 C L ) V 2 DD f CLK = C Eff V 2 DD f CLK ( C Eff : Effective Capacitance) Inverter

49 Switching Activity (Example 5.12) α0 1 = 2 / 8 = 0.25

50 Transistor Sizing for Minimum Energy Goal: Minimize Energy of whole circuit while maintaining the speed speed performance Design parameters: f and V DD tp tp,ref of referenced circuit with f=1 and Vdd =V ref In Out C g1 1 f C ext t t p p0 f = t p γ VDD V V DD TE F fγ ( F = C ext / C g 1) ( V TE = VT + VDSAT / 2)

51 Transistor Sizing (2) Transistor Sizing (2) Performance Constraint (γ=1) Vdd(f) Energy for single transition Energy ratio of the design and reference circuit ( ) ( ) = = = F f F f V V V V V V F f F f t t t t TE DD TE ref ref DD ref p p pref p = F F f V f V E E ref DD ref ) ( 2 [ ] ] ) )(1 1 1[( F f C V F f f C V E g DD g DD = = γ γ γ

52 Transistor Sizing (4) V DD =f(f) E/E ref =f(f) Required Supply Voltage Energy v.s. Sizing factor

53 Sizing factor for Speed and Energy Device sizing, combined with supply voltage reduction, is a very effective way in reducing energy consumption of a logic network. The gain can be up to 10 for large fanout. Oversizing beyond the optimal value comes at a hefty price in energy. Optimal size for energy is smaller than the optimal sizing for performance. For example, f(energy) = 3.53, f(performance) = 4.47= 20, for F=20

54 Short Circuit Currents (during switching) Vd d Vin Vout C L 0.15 I VDD (ma) V in (V)

55 Minimizing Short-Circuit Power Inverter

56 Neil Weste Textbook Inverter

57 Leakage Current Sub-threshold current is one of most compelling issues in low-energy circuit design!! P = I stat stat V DD

58 Reverse-Biased Diode Leakage GATE p + p+ N + - V dd Reverse Leakage Current I DL = J S A JS = pa/µm2 at 25 deg C for 0.25µm CMOS JS doubles for every 9 deg C!

59 Subthreshold Leakage Component Inverter

60 Subthreshold Leakage Component (2) Inverter

61 Putting All Together P total = P dyna + P dp + P stat = ( C V L 2 DD + V DD I peak t s ) f V DD I leak In a typical CMOS circuits, the capacitive dissipation is by far the dominant factor. Leakage is ignorable at present, but will be major issue in deep-submicron CMOS circuits.

62 Principles for Power Reduction Prime choice: Reduce voltage! Recent years have seen an acceleration in supply voltage reduction Design at very low voltages still open question (0.6,, 0.9 V by 2010!) Reduce switching activity (at different levels) Reduce physical capacitance Device Sizing: for example, for F = 20 f opt (energy)=3.53, f opt (performance)=4.47.

63 Power-Delay Product (PDP) PDP = P t av p f = 1/(2t ) max L p CLV DD DD fmaxt p PDP = C V = PDP stands for the average energy consumed per switching event (0 1, 1 0)

64 Energy-Delay Product (EDP) Measure of both Performance and Energy EDP = PDP t C V α p = P av t 2 p = CLV 2 L DD t p, VTE = VT + VDSAT VDD VTE 2 DD t p / 2 (5.21) 2 3 CLVDD EDP = α, VDD, opt = 2( V V ) DD TE 3 2 V TE (5.59) The value of supply voltage that simultaneously optimizes performance and energy. For Vt=0.5V, the VDD is around 1V.

65 Energy-Delay Product (EDP) V V Tn Tp = 0.42V, = 0.4V, V V Dsat, n Dsat, p = 0.63V, V = 1V, V TE, n TE, p = 0.74V = 0.9V V TE = ( V TE, n + V TE, p ) / 2 = 0.8V V DD, opt = (3/ 2) 0.8V = 1.2V Note: Vdd for minimum EDP May not be the Optimal Vdd for a given design problem (speed contraint)

66 Summary Inverter Speed (delay), sizing, and power are discussed. The concept can be extended to complex gates in next chapter and future discussions Very important for the 1 st -order guess/approximation for designers in considering power/area/speed of the target CMOS circuits