DC and Transient Responses (i.e. delay) (some comments on power too!)


 Lenard Stafford
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1 DC and Transient Responses (i.e. delay) (some comments on power too!) Michael Niemier (Some slides based on lecture notes by David Harris) 1 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
2 Today 1st Outline Quickly review material from last time 2nd Briefly think about transistor operation in context of logic gates 3rd Use basic logic gates to study trends relating to power & delay in context of device scaling 2 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
3 MOSFET cross section With applied V gs, depletion region forms n n P 3 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
4 Review: MOS Capacitor Gate and body form MOS capacitor Operating modes V g < 0 V g < 0 + V g < polysilicon gate polysilicon dioxide gateinsulator polysilicon gate ptype silicon body dioxide insulator silicon dioxide insulator ptype body ptype body (a) (a) (a) 0 < V g < V t 0 < V g < V t depletion region + depletion region (b) (b) V g > V t V g > V t inversion region depletion inversion region depletion region (c) (c) 4 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
5 Review: nmos Cutoff No channel formed, so no current flows I ds = 0 V gs = g +  V gd s d n+ n+ ptype body b 5 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
6 Review: nmos Linear Channel forms V Current gs > V t flows from d to s e  from s to d I ds increases n+ with n+ V V ds = 0 ds ptype body Similar to linear resistor V gs > V t s g b g +  V gd = V gs d +  V gs > V gd > V t V gs > V t +  s n+ n+ g ptype body b +  V gd = V gs V gs > V t V ds = 0, no current d V ds = 0 s d I ds n+ n+ ptype body b 0 < V ds < V gs V t V gs > V t V ds > 0, but < (V gs  V t ) (current flows) 6 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
7 Review: nmos Saturation Channel pinches off I ds independent of V ds We say current saturates Similar to current source V gs > V t +  g +  V gd < V t s d I ds n+ n+ V ds > V gs V t ptype body b V ds > V gs  V t Essentially, voltage difference over induced channel fixed at V gs  V (current flows, but saturates) (or i ds no longer a function of V ds ) 7 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
8 nmos IV Summary Shockley 1 st order transistor models " # 0 Vgs < V # V I =! $ V V ds % ) ' & & V V V 2 ( < # * + #! ( V V ) 2 # & V > V, 2 ds gs t ds ds dsat gs t ds dsat t cutoff linear saturation 8 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
9 We ll start by considering logic gates in the context of transistor currents (for CMOSbased circuits ) 9 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
10 4input CMOS NOR gate CMOS Gate Design A A B Out B C D Y (2input NOR for reference) 10 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
11 High noise margins: Why CMOS? Voltage swing ~ = supply voltage No direct path between supply and ground rails under steadystate operating conditions (I.e. when input and outputs remain constant) Absence of current flow = no static power But this isn t exactly true as we ll see All early Intel microprocessors NMOS only (see NMOS inverter at right) Hard to achieve 0 static power Put firm upper bound on # of gates Necessitated move to CMOS in 1980s Single transistor pulls signal low. 11 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
12 1st, DC Response DC Response: V out vs. V in for a gate Ex: Inverter When V in = 0 > V out = When V in = > V out = 0 In between, V out depends on transistor size and current Want: I dsn = I dsp We could solve equations V in But graphical solution gives more insight I dsp I dsn V out 12 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
13 Transistor Operation Current depends on region of transistor behavior For what V in and V out are nmos and pmos in Cutoff? Linear? Saturation? 13 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
14 Recall Cutoff nmos Operation Linear Saturated V gsn < V tn V gsn > V tn Same V gsn > V tn V dsn <V gsn V tn V dsn >V gsn V tn No Current V ds <V gs V t V ds <V gs V t In inverter context, what is V gs, V ds for NMOS device? V in I dsp I dsn V out 14 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
15 nmos Operation Cutoff V gsn < V tn Linear V gsn > V tn Saturated V gsn > V tn V dsn <V gsn V tn V dsn >V gsn V tn V gsn = V in I dsp V dsn = V out V in I dsn V out 15 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
16 nmos Operation (in context of inverter input V) Cutoff V gsn < V tn V in < V tn Linear V gsn > V tn V in > V tn V dsn <V gsn V tn V out <V in  V tn Saturated V gsn > V tn V in > V tn V dsn >V gsn V tn V out >V in  V tn V gsn = V in I dsp V dsn = V out V in I dsn V out 16 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
17 pmos Operation (for reference) Cutoff V gsp > V tp V in > + V tp Linear V gsp < V tp V in < + V tp V dsp >V gsp V tp V out >V in  V tp Saturated V gsp < V tp V in < + V tp V dsp <V gsp V tp V out <V in  V tp V gsp = V in  V tp < 0 V dsp = V out  V in I dsp I dsn V out 17 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
18 IV Characteristics Make pmos is wider than nmos such that β n = β p V gsn5 I dsn V gsn4 V gsn3 V dsp V gsp1 V gsp20 V gsn2 V gsn1 V gsp3 V dsn V gsp4 V gsp5 I dsp Can plot I ds as function of V gs, V dd (sign conventions from PMOS/NMOS devices) 18 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
19 Load Line Analysis For a given V in : (Translate lines onto same set of axes ) Plot I dsn, I dsp vs. V out V out must be where currents are equal in (For DC operating point to be valid  consider graphical intersection of load lines i.e. current in pmos > current in nmos V in0 pmos nmos V in5 I dsn, I dsp V in1 V in4 I dsp V in V out V in2 V in3 I dsn V in3 V in4 V in2 V in1 V out 19 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
20 DC Transfer Curve Transcribe points onto V in vs. V out plot A B V in0 V in5 V in1 V in4 V out C V in2 V in3 V in3 V in4 V in2 V in1 0 D E V tn /2 +V tp V out V in 20 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
21 Comments: All operating points are located near high or low output levels The VTC of the inverter exhibits a very narrow transition zone This results from high gain during the switching transient (When both NMOS, PMOS are in saturation and on simultaneously) (In this region, small change in the input voltage results in a large output variation) 21 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
22 Operating Regions Revisit transistor operating regions Region A nmos Cutoff pmos Linear A B B C Saturation Saturation Linear Saturation V out C D E Linear Linear Saturation Cutoff 0 D E V tn /2 +V tp V in 22 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
23 A few more interesting points 23 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
24 Beta Ratio If β p / β n 1, switching point will move from /2 Called skewed gate Other gates: collapse into equivalent inverter V out! p 0.1! = n! p 10! = n V in 24 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
25 Noise Margins How much noise can a gate input see before it does not recognize the input? Logical High Output Range Output Characteristics V OH NM H Input Characteristics Logical High Input Range V IH V IL Indeterminate Region Logical Low Output Range V OL NM L GND Logical Low Input Range 25 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
26 Logic Levels To maximize noise margins, select logic levels at unity gain point of DC transfer characteristic Acceptable low input to get high output V out Unity Gain Points Slope = 1 V OH! p /! n > 1 V in V out V OL 0 V tn V IL V IH  V tp V in Acceptable high input to get low output 26 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
27 Supply voltage scaling As supply voltage scales down  which can be good as we ll see  can have problems To a point (~0.5V), scaling Vdd improves gain Beyond, DC characteristics become increasingly sensitive to variations in the device parameteres E.g. transistor threshold Scaling supply voltages reduces signal swing Makes design more sensitive to external noise sources that don t scale. 27 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
28 Next, board discussion on transient response, power. 28 Lecture 02  CMOS Transistor Theory & the Effects of Scaling  CSE 40547/60547
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