Digital Integrated Circuits A Design Perspective


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1 Digital Integrated Circuits Design Perspective Designing Combinational Logic Circuits Fuyuzhuo School of Microelectronics,SJTU Introduction Digital IC
2 Dynamic Logic Introduction Digital IC 2 EE141
3 Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Dynamic logic cascade solution Digital IC 3
4 first glance of dynamic logic Basic components PDN,just like CMOS and pseudonmos Clock control transistors, seperate circuit to two phases Dynamic logic s two phases precharge evaluation Digital IC 4
5 Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path. fanin of n requires 2n (n Ntype + n Ptype) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 Ntype + 1 Ptype) transistors Digital IC 5
6 Dynamic Gate M p M p Out Out In 1 In 2 In 3 PDN C L B C M e M e Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1) Digital IC 6
7 Dynamic Gate M p Out M p off on 1 Out In 1 In 2 In 3 PDN C L B ((B)+C) C M e Two phase operation Precharge ( = 0) Evaluate( = 1) M e off on Digital IC 7
8 Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on C L Digital IC 8
9 Dynamic Logic Dynamic gates uses a clocked pmos pullup Two modes: precharge and evaluate 2 1 2/3 4/3 1 1 Static PseudonMOS Dynamic Precharge Evaluate Precharge Digital IC Slide 9
10 The Foot What if pulldown network is ON during precharge? Use series evaluation transistor to prevent fight. precharge transistor inputs f inputs f foot footed unfooted Digital IC Slide 10
11 Logical Effort Inverter NND2 NOR2 unfooted 1 1 g d = p d = B g d = p d = 1 1 B 1 g d = p d = footed B 3 2 B 2 g d = g d = 2 p d = 3 p d = 2 g d = p d = Digital IC Slide 11
12 Logical Effort Inverter NND2 NOR2 unfooted 1 1 g d = 1/3 p d = 2/3 B g d = 2/3 p d = 3/3 1 1 B 1 g d = 1/3 p d = 3/3 footed B 3 2 B 2 g d = 2/3 g d = 3/3 2 p d = 3/3 3 p d = 4/3 2 g d = 2/3 p d = 5/3 Digital IC Slide 12
13 Monotonicity Dynamic gates require monotonically rising inputs during evaluation 0 > 0 0 > 1 1 > 1 But not 1 > 0 violates monotonicity during evaluation Precharge Evaluate Precharge Output should rise but does not Digital IC Slide 13
14 Monotonicity Woes But dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another! = 1 X Precharge Evaluate X Precharge Digital IC Slide 14
15 Monotonicity Woes But dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another! = 1 X Precharge Evaluate X Precharge X monotonically falls during evaluation should rise but cannot Digital IC Slide 15
16 Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Dynamic logic cascade solution Digital IC 16
17 Properties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (V OL = GND and V OH = V DD ) Nonratioed sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance (C in ) reduced load capacitance due to smaller output loading (C out ) Digital IC 17
18 Properties of Dynamic Gates Overall power dissipation usually higher than static CMOS no static current path ever exists between V DD and GND (including P sc ) No glitching higher transition probabilities extra load on PDN starts to work as soon as the input signals exceed V Tn, so V M, V IH and V IL equal to V Tn low noise margin (NM L ) Needs a precharge/evaluate clock Digital IC 18
19 Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Chargeleakage Chargesharing Backgate Coupling Clock feedthrough Dynamic logic cascade solution Digital IC 19
20 Issues in Dynamic Design 1: Charge Leakage CLK M p Out C L M e Leakage sources V Out Precharge Evaluate Dominant component is subthreshold current Digital IC 20
21 Solution to Charge Leakage M p M kp Keeper Width:min Length:L B C L Out Option! M e Same approach as level restorer for passtransistor logic Digital IC 21
22 Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Chargeleakage Chargesharing Backgate Coupling Clock feedthrough Dynamic logic cascade solution Digital IC 22
23 Issues in Dynamic Design 2: Charge Sharing M p C L Out Charge stored originally on C L is redistributed (shared) over C L and C leading to reduced robustness B=0 C M e C B Could we move it to there? Digital IC 23
24 Charge Sharing Dynamic gates suffer from charge sharing B = 0 x C x C Charge sharing noise x V x = V = Digital IC Slide 24
25 Charge Sharing Dynamic gates suffer from charge sharing B = 0 x C x C Charge sharing noise x C V = V = V x DD Cx + C Digital IC Slide 25
26 Solution to Charge Redistribution M p M kp Out B M e Precharge internal nodes using a clockdriven transistor (at the cost of increased area and power) Digital IC 26
27 Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Chargeleakage Chargesharing Backgate Coupling Clock feedthrough Dynamic logic cascade solution Digital IC 27
28 Issues in Dynamic Design 3: Backgate Coupling =0 M p C L1 Out1 =1 Out2 =0 C L2 In B=0 M e 3 Dynamic NND Voltage 2 1 Static NND Out1 0 In Out21 Digital IC Time, ns
29 Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Chargeleakage Chargesharing Backgate Coupling Clock feedthrough Dynamic logic cascade solution Digital IC 29
30 Issues in Dynamic Design 4: Clock Feedthrough B M p M e C L Out Coupling between Out and input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above V DD. The fast rising (and falling edges) of the clock couple to Out. Digital IC 30
31 Voltage Clock Feedthrough Out 2.5 Clock feedthrough In 1 In In 3 In In & Out Time, ns 1 Clock feedthrough Digital IC 31
32 Dynamic logic outline Dynamic logic principle Dynamic logic properties Dynamic logic design issues Chargeleakage Chargesharing Backgate Coupling Clock feedthrough Dynamic logic cascade solution Digital IC 32
33 Domino Gates Follow dynamic stage with inverting static gate Dynamic / static pair is called domino gate Produces monotonic outputs Precharge Evaluate Precharge domino ND W W X Z X B C Z dynamic NND static inverter B W H C X H X Z = B C Z Digital IC Slide 33
34 Designing with Domino Logic V DD V DD V DD M p Out1 M p M r Out2 In 1 In 2 PDN In 4 PDN In 3 Can be eliminated! M e M e Inputs = 0 during precharge Digital IC 34
35 Footless Domino V DD V DD V DD M p Out 1 M p Out 2 M p Out n In In In 3 In n The first gate in the chain needs a foot switch Precharge is rippling shortcircuit current solution is to delay the clock for each stage Digital IC 35
36 npcmos In 1 M p Out1 In 4 M e PUN In 2 In 3 PDN M e In 5 M p Out2 (to PDN) Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN Digital IC 36
37 Domino Summary Domino logic is attractive for highspeed circuits 1.5 2x faster than static CMOS But many challenges: Monotonicity Leakage Charge sharing Noise Widely used in highperformance microprocessors Digital IC Slide 37
38 Summary Static CMOS gates are very robust Logic effect Fanin relate to the delay Power evalutation Other circuits suffer from a variety of pitfalls Pseodu NMOS logic Pass transistor cascade problem,restorer(keeper),some pass logic Dynamic logic Characteristic Cascade issue Domino logic Some pitfalls of dynamic logic Digital IC Slide 38
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